Abstract: Provided are techniques for receiving a packet transmitted in conjunction with a security association associated with Internet Protocol Security (IPSec); determining, based upon the security Association that the packet is faulty; incrementing a count corresponding to previous faulty packets received; determining that the count exceeds a threshold; and disabling IPSec accelerator hardware in response to the determining that the count exceeds the threshold.

Abstract: An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014. An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024. The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value.

Abstract: A method and apparatus for encoding channel quality indicator (CQI) and precoding control information (PCI) bits are disclosed. Each of the input bits, such as CQI bits and/or PCI bits, has a particular significance. The input bits are encoded with a linear block coding. The input bits are provided with an unequal error protection based on the significance of each input bit. The input bits may be duplicated based on the significance of each input bit and equal protection coding may be performed. A generator matrix for the encoding may be generated by elementary operation of conventional basis sequences to provide more protection to a most significant bit (MSB).

Abstract: The present invention describes how to handle errors occurring during communication in a frame-based communication system that uses a communication protocol having a first error handling mechanism responsive to receipt of an incorrect protocol symbol. The invention provides a method and apparatus that allow several errors to occur without the communication system responding by initiating the first error handling mechanisms. Under circumstances where errors occur, the method and apparatus may improve throughput.

Abstract: Provided are an apparatus and method for processing an ARQ in a MIMO system. The apparatus includes a storing unit for storing reordering thresholds of each receiving terminal and retransmission data; a priority managing unit for assigning a priority to a plurality of antenna groups in ascending order of a bit error rate of a wireless channel of each antenna group and managing the plurality of antenna groups based on the priorities; a data transmitting unit for transmitting retransmission data; and a controlling unit for controlling the data transmitting unit to transmit retransmission data within a range not exceeding a reordering threshold of a corresponding receiving terminal sequentially using an antenna group having the highest priority first.

Abstract: A method of adjusting an interface voltage includes transferring data between a memory device and a controller, and detecting whether an error occurred in the transfer of data. An interface voltage of at least one of the memory device and the controller is adjusted based on the detection.

Abstract: The subject disclosure describes a method for reducing a sector error rate in a flash memory device, the method comprising, identifying a first program verify level having a first value, selecting an adjustment value for the first program verify level and programming the adjustment value to the first program verify level to replace the first value and to shift a first programming distribution associated with the first program verify level, wherein the shift in the first programming distribution is associated with a decrease in a sector error rate, wherein the shift in the first programming distribution is associated with an increase in a bit error rate. A flash storage device and computer-readable media are also provided.

Abstract: The subject disclosure provides a method for generating a read-level error signal, comprising, correcting a plurality of bits read from a flash memory, determining a first error rate of a first error type corrected in the bits and determining a second error rate of a second error type corrected in the bits. In certain aspects, methods of the subject technology further provides steps for comparing the first error rate with the second error rate and generating a read-level error signal based on the comparison of the first error rate and the second error rate. A decoder and flash storage device are also provided.

Abstract: An apparatus for data communication that receives a plurality of pulses from a remote communications device, determines a pulse puncturing rate based on the pulses, and punctures or discards subsequent pulses based on the pulse puncturing rate. During intervals when punctured pulses are expected, the apparatus operates in a lower power consumption mode for the purpose of conserving power. In another aspect, a receiving apparatus determines the pulse puncturing rate based on received pulses, and transmits the pulse puncturing rate information to a transmitting apparatus. In response, the transmitting apparatus sends a subset of the pulses it would have transmitted based on the pulse puncturing rate. Because the receiving apparatus receives fewer pulses (e.g., a subset), the receiving apparatus may operate in a lower power consumption mode for longer periods in order to conserve power.

Abstract: Scheduler 304 performs scheduling such that the communication terminal apparatuses to transmit packets to are determined according to the order in CIR information output from demodulator 303, and determines the modulation schemes and coding rates of the packets. Command detector 305 detects an ARQ command transmitted from the communication terminal apparatus determined in scheduler 304, outputs an ACK/NACK signals to buffer 306, and outputs a SUSUPEND signal or a GIVEUP signal to scheduler 304. Scheduler 304 stops retransmission upon receiving a SUSPEND signal or a GIVEUP signal from command detector 305, and redoes the scheduling. Thus, it is possible to improve overall system throughput in a wireless communication system that performs packet transmission.

Abstract: Embodiments of the present invention provide systems, methods, and computer-readable media for modifying frame error rates associated with a mobile device. In embodiments, a mobile device is assigned an initial frame error rate. In response to determining the initial frame error rate does not match a desired frame error rate, a frame error rate modification request is generated. The frame error rate modification request is transmitted to a base station. At the base station, a modified frame error rate that matches the desired frame error rate is associated with the mobile device.

Abstract: Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels.

Abstract: A method and apparatus is disclosed wherein a user equipment (UE) receives control information on a first channel and uses the control information to process a second channel.

Abstract: The instant disclosure relates to a raw data compression method for the fabrication process. The method includes the steps of: inputting into a signal converter a collection of raw data points representing operational parameter of a semiconductor equipment within a predetermined time period; obtaining an approximation of the raw data points with a Fourier series; computing the Fourier coefficients and the residuals between the raw data points and the corresponding predicted values predicted by the Fourier series; determining if the residuals exceed an error threshold; recording and storing the Fourier coefficients as the compressed data if none of the residuals exceeds the error threshold; and recording the raw data point as abnormal data point if the corresponding residual exceeds the error threshold before recording and storing the Fourier coefficients and the abnormal data point as the compressed data.

Abstract: In one embodiment an example apparatus includes a memory with an error detection system (EDS) that detects an error event in the memory. The error event involves at least one bit in the memory changing state erroneously. The apparatus also includes a scrub logic to scrub the memory and correct memory errors (e.g., bit errors). The apparatus also includes a scrub rate adaptive logic to selectively control a memory scrub frequency associated with the scrub logic where the control is based, at least in part, on a number of error events detected by the EDS during an interval of time. A memory scrub frequency is the rate that a memory is periodically scrubbed to remove errors.

Abstract: A two-dimensional self-RAID method of protecting page-based storage data in a MLC multiple-level-cell flash memory device. The protection scheme includes reserving one parity sector across each data page, reserving one parity page as the column parity, selecting a specific number of pages to form a parity group, writing into the parity page a group parity value for data stored in the pages of the parity group. The parity sector represents applying a RAID technique in a first dimension. The group parity represents applying a RAID technique in a second dimension. Data protection is achieved because a corrupted data sector can likely be recovered by the two dimensional RAID data.

Abstract: A premises based multimedia communication system includes a source device that produces multimedia content, a rendering device that presents the multimedia content, and a premises communication network coupling the source device to the rendering device. The system determines a bit error rate of the premises communication network, transfers the multimedia content from the source device to the rendering device, and when the bit error rate exceeds a bit error rate threshold, the system at least partially disables link layer encryption of video frames of the multimedia content transfer. With the link layer operations at least partially disabled, the system can enable, at least partially, content layer encryption operations for the transfer of the multimedia content from the source device to the rendering device.

Abstract: A receiving station repeatedly performs decoding processing of data in a decoding processing portion, performs error detection of the decoding results, and transmits to a transmitting station an error detection result (ACK/NACK) for decoding results for a preset number of executions, and moreover issues a request to the transmitting station to modify the data transmission interval based on the data reception characteristic. The transmitting station transmits data at transmission intervals according to the transmission interval modification requests sent from the receiving station. The receiving station selectively inputs to the decoding processing portion the data received from the transmitting station and the previous decoding result data.

Abstract: Disclosed is an apparatus and method for adjusting a memory parameter in a non-volatile memory circuit. On a trigger event, a parameter is determined in accordance with a circuit characteristic associated with the memory block. The parameter may be a new read level voltage to apply to a page of a memory block, or a program verify level voltage used to program a page of a memory block. On determining the parameter a command is sent to the memory circuit to apply the parameter to the page of the memory block. The method can be triggered by an event such as P/E cycle times and the condition is dynamically adjusted to extend the life of the memory circuit.

Abstract: A method and device for selectively refreshing a region of a non-volatile memory of a data storage device is disclosed. In a particular embodiment, a method is disclosed that includes comparing a time stamp received from a host device to a first time stamp retrieved from a data storage device for a first region of a non-volatile memory, the first region including a least recently accessed region of a memory array within the data storage device. The method also includes selectively refreshing the first region based on a comparison of a difference between the time stamp received from the host device and the first time stamp as compared to a threshold, where the threshold is adjusted based on a first error count corresponding to a number of errors detected by an error correction code (ECC) engine with respect to data retrieved from the first region.

Abstract: A system involves a first SerDes link from a first integrated circuit (IC) to a second IC and a second link from the second IC to the first IC. Power consumption settings in circuitry of the first link are adjusted to control power consumption such that the bit error rate of the first link is maintained in a range, where the lower bound of the range is substantially greater than zero. Power consumption settings in circuitry for the second link are adjusted to control power consumption such that the bit error rate of the second link is maintained in range, where the lower bound of the range is substantially greater than zero. In one example, circuitry in the second IC detects errors in the first link and reports back via the second link. The first IC uses the reported information to determine a bit error rate for the first link.

Abstract: Methods and systems are provided for implementing quality of service (QoS) by using Hybrid ARQ (HARQ) response for triggering the EV-DO reverse activity bit (RAB). In an embodiment, an access node provides service to a plurality of access terminals, the plurality including a select group of one or more access terminals. The access node detects that it has, over a time period, sent more than a threshold number of HARQ negative acknowledgements (NACKs) with respect to reverse-link communication of the select group, and responsively (1) sets the RAB for the first wireless coverage area and (2) instructs the select group of access terminals to ignore the RAB. The select group ignores the RAB, while the rest of the access terminals obey the RAB.

Abstract: A method for performing a program operation in a non-volatile memory device includes applying a programming pulse to a plurality of memory cells, verifying whether the plurality of the memory cells are programmed to produce a verification result, determining whether all of the plurality of the memory cells are programmed in response to the verification result to produce a first determination result and determining whether at least a first number of memory cells are programmed among the plurality of the memory cells in response to the first determination result to produce a second determination result.

Abstract: An apparatus is operable to receive a digital video signal transmitted over a channel and comprises an operational module configured to operate in a first mode of operation and in a second mode. The apparatus is configured to switch operation of the operational module from the first mode to the second mode in dependence of an estimate of an environment (condition) of the channel.

Abstract: Memory devices and methods are described that include a stack of memory dies and a logic die. Method and devices described include those that provide for repartitioning the stack of memory dies and storing the new partitions in a memory map. Repartitioning in selected configurations allows portions of memory to be removed from use without affecting the rest of the memory device. Additional devices, systems, and methods are disclosed.

Abstract: Handling of integrity check failure in a wireless communication system can safely send the mobile station to the idle mode upon detection of security failure. Alternatively or in addition, attempts to recover from the security failure situation can be enabled without forcing the mobile station to enter idle mode. The mobile station autonomously transitions to idle mode when the integrity check failure is detected a certain threshold number ‘X’ times during a specified period ‘Y’. Whereupon, the mobile station initiates the Radio Resource Control (RRC) connection re-establishment procedure after integrity check failure is detected. In the RRC connection re-establishment procedure, the security parameters are re-initialized to provide a possibility to recover from the failure situation.

Abstract: An integrated circuit includes a plurality of processing stages each including processing logic, a non-delayed signal-capture element, a delayed signal-capture element and a comparator. The non-delayed signal-capture element captures an output from the processing logic at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element also captures a value from the processing logic. An error detection circuit and error correction circuit detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator. The comparator compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value.

Abstract: Disclosed is a communication system that transmits data through a transmission path between a transmission side apparatus and a reception side apparatus, wherein the transmission side apparatus comprises a coding apparatus that creates redundantly-coded data from original data; a transmitting apparatus that sends the coded data coded by the coding unit to the transmission path; and a coding rate determining apparatus that sets and controls a coding rate in the coding unit, wherein the reception side apparatus comprises a receiving apparatus that receives the coded data sent through the transmission path; a decoding apparatus that decodes the original data from the coded data received; and a loss rate estimating apparatus that measures the loss rate on the path of the coded data sent, and wherein the coding rate determining apparatus of the transmission side apparatus varies and controls the coding rate in the coding apparatus based on the loss rate obtained.

Abstract: A receiver is provided, which is adapted to receive MPE-FEC frames and to correct erroneous sections within a received MPE-FEC frame by detecting unreliable sections and storing in an erasure list (“ESL”) table compressed data that includes the base address of each detected erroneous section, together with the respective section's size. The size of the ESL table may be fixed, or it may correlate, or dynamically change according to the actual number of detected erroneous sections. The data stored in the erasure list may then be forwarded to a decoder to correct erroneous sections. The erroneous sections may be detected by using CRC, and the decoder may be a Reed-Solomon decoder.

Abstract: Methods and apparatus are provided for serializer/deserializer transmitter synchronization. A plurality of channels are synchronized in one or more serializer/deserializer devices by generating a synchronization request in one or more of the channels; generating an enable signal in response to the synchronization request; and generating a gated synchronization signal for only one or more periods of a synchronization signal in response to the enable signal. The gated synchronization signal can optionally be deasserted after the one or more periods of a synchronization signal.

Abstract: An apparatus for testing a communication circuit includes a detection module and a capture module. The detection module provides an enable signal in response to receiving at least one predetermined plurality of data from a communication device under test. The capture module captures at least one other predetermined plurality of data in response to the enable signal.

Abstract: A method for operating a memory that includes multiple analog memory cells includes storing data in the memory by writing first storage values to the cells, so as to cause the cells to hold respective electrical charge levels. After storing the data, second storage values are read from at least some of the cells, including at least one interfered cell that belongs to a group of cells. A Back Pattern Dependency (BPD) distortion caused by the electrical charge levels of one or more interfering cells in the group to at least one of the second storage values read from the at least one interfered cell is detected and canceled. The second storage values, including the at least one of the second storage values in which the BPD distortion was canceled, are processed so as to reconstruct the data.

Abstract: In one embodiment, the semiconductor device includes at least one circuit element configured to generate output data. At least one control circuit is configured to adaptively control a power of the output data based on feedback from a receiving semiconductor device, which receives the output data.

Abstract: A data-transmission control method is implemented when transmitting data after dividing the data into a plurality of blocks and performing error correction when performing data transmission. The method includes obtaining additional information indicating a result of error correction process of received data and a result of data transmission (ACK/NACK) from a reception station, and deciding a data length of data to be retransmitted when NACK is obtained as the result of data transmission so that a rate of occurrence of transmission errors upon retransmission is minimized, based on a number of blocks in which error correction has failed indicated by the additional information.

Abstract: The present invention discloses an apparatus and method for adapting a transmission parameter in a transmitting node of a data communication system to the current link quality of a data communication channel. The adapted transmission parameter is selected by the transmitting node from a set of transmission parameters in dependence on a number of successful transmissions. The number of successful transmissions is compared in the transmitting node against one of a first threshold value corresponding to a first state of the transmitting node and a second threshold value corresponding to a second state of the transmitting node.

Abstract: An interface system is provided between a source component (210) and a destination component (220) having multiple parallel lines for transmitting data or parity bits (231-234, 251-253) and one or more spare lines (241-243). An error detection means (222) identifies one or more faulty lines. A mapping means (228) re-routes data or parity from a faulty line to a spare line. A communication link (208) is provided for communicating the re-routing between the source component (210) and the destination component (220). The error detection and mapping can be repeated to detect and re-route sequential multiple-bit line errors using additional spare lines (241-243).

Abstract: In a storage device, a bad-sector detecting unit detects a bad sector, and a process determining unit determines whether rescue process is performed for the bad sector. Upon determining to perform the rescue process, the process determining unit controls a damping ratio. A table-updating control unit records various information in an alternating-process control table, and a controller records and reproduces data with respect to a rescue sector based on the alternating-process control table.

Abstract: A memory system includes an error detection circuit having an error counter. When a bit error rate (BER) determined by the error counter exceeds a reference BER, the memory system reduces the BER by adjusting its operating speed or operating voltage, re-performing data training or impedance matching, or by adjusting a data swing width. Accordingly, a method of controlling a bit error rate may be performed, and a system hang is prevented.

Abstract: Controlling an unreliable data transfer in a data channel from a transmitting unit to a receiving unit. A bypass mode or a buffer mode is activated depending on the error rate in the data channel. If bypass mode is selected, data packets are directly transferred in probation from the transmitting unit to the receiving unit by a bypass line. The data packets are error checked after the data transfer. If buffer mode is selected, data is transfer from the transmitting unit to the receiving unit by a buffer line via an error detecting and correcting unit and a buffer unit. The errors are detected and corrected during the data transfer.

Abstract: An apparatus and method for efficiently processing memory faults. A faulty memory is exchanged with a spare memory when the total number of faults in the memories is over a threshold. After the switching, when the number of faults in a single cache line is over a threshold, a memory page corresponding to the single cache line is blocked.

Abstract: A stream of traffic data is generated, where the traffic data has a known characteristic. The stream of traffic data is applied to the network device, where the network device has a specific type. The network device generates an output based on the traffic data. A performance of the network device is monitored while the traffic data is processed by the network device to generate monitoring data for the traffic data applied to the network device having the specific type. The output from the network device is analyzed to identify how the traffic data was handled by the network device to generate performance metrics. The monitoring data and the performance metrics are saved to a knowledge database. The knowledge database can be accessed to enable configuration of other network devices based in part on the monitoring data and performance metrics.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.

Abstract: Embodiments of the invention enable the integrity of data processed by a switch to be guaranteed better than 10?9 undetected erroneous frames per flight hour. To do this, rules for disabling ports are included in the switch management program. These rules include a maximum absolute admissible number of erroneous frames, to a maximum relative rate of admissible erroneous frames and a minimum number of erroneous frames constituting a significance threshold. Random errors are detected at the level of each frame due to the insertion of a CRC. Deterministic or data-dependent errors able to deceive systematically the CRC check are made random by means of a frame index.

Abstract: A memory controller includes a page configure module that communicates with a memory array comprising B memory blocks each including P pages. The page configure module selectively configures memory cells in the P pages of each of the B memory blocks to store from 1 to T bits per cell. The page configure module also generates a memory map based on the configuration. B, P, and T are integers greater than 1. At least one of a write module selectively writes data to the memory array based on the memory map or a read module selectively reads data from the memory array based on the memory map.

Abstract: A communication system includes a transceiver capable of receiving a data burst as part of a paging block and a processing logic capable of comparing at least part of the data burst to a plurality of permutations of the data burst to locate a matching permutation. The processing logic determines a bit error rate (BER) in accordance with a difference between the data burst and the matching permutation. The processing logic uses the BER to operate the communication system.

Abstract: A control channel encoder includes a determiner to determine a current value of K for encoding control signals of a length M, wherein K is a function of a code rate for a data channel. A table generator generates first and second block encoding matrices, each of the first and second block encoding matrices having a variable length, from a fixed block encoding matrix by variably repeating rows from the fixed block encoding matrix to produce a repeated matrix of length K, puncturing the repeated matrix a first time to generate the first block encoding matrix, and puncturing the first block encoding matrix a second time to generate the second block encoding matrix. A block encoder utilizes the block encoding matrix to encode M input control bits as K encoded control bits.

Abstract: A reception device configured to receive a signal of a transmitted bit string transmitted from a transmission device which transmits a bit string includes: a receiving unit arranged to receive a signal from the transmission device and output a received bit string corresponding to the transmitted bit string; a storing unit arranged to store an error rate table wherein said received bit string is correlated with an error rate of post-data which is data of one bit or greater received following the received bit string being in error; and an error correcting unit arranged to perform error correcting of the post-data of the received bit string.

Abstract: In one embodiment, the present invention includes a system having an electromagnetic coupler probe to electromagnetically sample signals from a device under test or a link under test and a receiver, e.g., configured as an integrated circuit that is to receive the sampled electromagnetic signals from the probe and output digital signals corresponding thereto. Other embodiments are described and claimed.

Abstract: Systems and methods are disclosed herein for correcting errors. In one embodiment, among others, a method comprises receiving a plurality of error indications from a plurality of respective receivers. The receivers are configured to receive a data stream of packets transmitted within a multicast channel. Each error indication indicates which ones of a number of the packets were not received. The method further comprises analyzing the error indications to determine a first set of receivers to which forward error correction (FEC) code is transmitted and a second set of receivers to which unicast data is transmitted.

Abstract: A forward error correction (FEC) method is provided including an FEC dynamic central station and a plurality of FEC dynamic remote stations that transmit bearer data and corresponding error correction data therebetween during a plurality of time frames. The error rate of the communication channel is measured and the amount of error correction data transmitted is accordingly and dynamically adjusted, so that the minimum amount of overhead required to effectively transmit the error correction data is used.