Abstract: A method and system for selecting a network to establish a connection to from a set of available network includes a network database providing historical information about each of the networks and sends the database information to end user terminals. The end user terminals monitor real-time performance information about each of the available networks and can send this information to the network database. The end user terminals also include network connection policy information which can be used to make the selection decision. The end user terminal determines a network quality score for each available network as a function of the historical information from the network database, the real-time performance information about each available network and the network connection policy information. The end user terminal can select the available network as a function of the network quality score, for example, selecting the available network with the highest network quality score.

Abstract: Cross-decoding assists decoding of an otherwise uncorrectable error when decoding a desired page of a multi-level-cell technology flash memory. A solid-state disk (SSD) controller adjusts space allocated to redundancy respectively within various pages (e.g. upper, middle, and lower pages) such that the respective pages have respective effective Bit Error Rates (BER)s, optionally including cross-decoding, that approach one another. Alternatively the controller adjusts the allocation to equalize decoding time (or alternatively access time), optionally including decoding time (accessing time) accrued as a result of cross-decoding when there is an otherwise uncorrectable error. The adjusting is via (a) respective ratios between allocation for ECC redundancy and user data space, and/or (b) respective coding rates and/or coding techniques for each of the various pages.

Abstract: A system to convert upstream burst mode data into continuous mode data in a passive optical network (PON) is provided herein. The system includes a burst mode Serializer/Deserializer (SerDes) that recovers a clock and burst mode data from an Optical Network Unit (ONU). The burst mode unit recovers the burst mode data based on a start time of burst mode data transmission by the ONU and a round-trip time between the ONU and an Optical Line Terminal (OLT). The system further includes a continuous mode SerDes that is coupled to the burst mode SerDes. The continuous mode SerDes is configured to receive the recovered clock and recovered burst mode data from the burst mode SerDes and convert the burst mode data into continuous mode data by buffering and padding the burst mode data based on the recovered clock. The continuous mode Serdes is configured to transmit the continuous mode data to the OLT.

Abstract: In a system and method of enhancing data reliability, a reference value associated with error count is obtained, and an error count of data stored in a buffer is obtained whenever an event is triggered. An accumulated value associated with error counts is acquired when the recorded error count is greater than an error threshold value. System slowdown is performed when the accumulated value is greater than a predetermined value.

Abstract: A method of operation of a non-volatile memory system includes: generating a test stimulus for a page in a memory array; measuring a test response from the page in the memory array based on the test stimulus; calculating a measured effective life of the page from the test response; and determining a use plan according to the measured effective life for accessing the page.

Abstract: Rate adaptation is carried out using bit error rate (BER) to enable effective multimedia transmission. The BER can be estimated using signal strength in a MAC layer and modulation information (FIGS. 7-9), and can be compatibly used in different wireless networks by means of message standardization.

Abstract: A technique for radio link detection in a wireless communication system includes estimating a first error rate of an indicator channel. In this case, the indicator channel includes an indication of a number of symbols in a control channel. A second error rate of the control channel is also estimated. The first and second error rates are then combined to provide a performance metric. Based on the performance metric, a determination is made as to whether a radio link problem exists.

Abstract: A method and apparatus for encoding channel quality indicator (CQI) and precoding control information (PCI) bits are disclosed. Each of the input bits, such as CQI bits and/or PCI bits, has a particular significance. The input bits are encoded with a linear block coding. The input bits are provided with an unequal error protection based on the significance of each input bit. The input bits may be duplicated based on the significance of each input bit and equal protection coding may be performed. A generator matrix for the encoding may be generated by elementary operation of conventional basis sequences to provide more protection to a most significant bit (MSB).

Abstract: A method of monitoring signals is disclosed, wherein a plurality of command signals and address signals are consecutively expressed, as a measurement target. The method includes setting a strobe timing that has a predetermined initial value; calculating an error rate by monitoring the plurality of command signals, in accordance with the strobe timing; monitoring the plurality of address signals, and calculating a burst rate from a difference between the consecutive plurality of address signals, in accordance with the strobe timing; identifying timing where the calculated error rate and calculated burst rate are both optimized; and in the event the timing where both the calculated error rate and calculated burst rate are optimized cannot be identified, altering a predetermined value of the set strobe timing, and repeating the calculating, monitoring, and identifying.

Abstract: A method of monitoring signals is disclosed, wherein a plurality of command signals and address signals are consecutively expressed, as a measurement target. The method includes setting a strobe timing that has a predetermined initial value; calculating an error rate by monitoring the plurality of command signals, in accordance with the strobe timing; monitoring the plurality of address signals, and calculating a burst rate from a difference between the consecutive plurality of address signals, in accordance with the strobe timing; identifying timing where the calculated error rate and calculated burst rate are both optimized; and in the event the timing where both the calculated error rate and calculated burst rate are optimized cannot be identified, altering a predetermined value of the set strobe timing, and repeating the calculating, monitoring, and identifying.

Abstract: A variable write back indicator control is provided to control the amount of data to be re-transmitted when a packet error occurs. A hardware controller obtains an indication that an acknowledge rate or an amount of set write back indicators of a data frame is to be adjusted. The indication is based on an error rate of data transmission over a communication bus. Based on obtaining the indication that the amount of set write back indicators is to be adjusted, one or more write back indicators are adjusted.

Abstract: A method for implementing adaptive error correction in a memory, comprising the steps of (A) decoding a page of data read from a memory, (B) selecting one of a plurality of histograms based on a measured code word error rate of the decoded page and (C) applying an error correction code rate based on the selected histogram. The error correction code rate allows the memory to use a minimum number of error correction bits to provide reliable operation of the memory.

Abstract: In a system and method of enhancing data reliability, a reference value associated with error count is obtained, and an error count of data stored in a buffer is obtained whenever an event is triggered. An accumulated value associated with error counts is acquired when the recorded error count is greater than an error threshold value. System slowdown is performed when the accumulated value is greater than a predetermined value.

Abstract: Technologies are generally described for enhancing communication performance. In some examples, a scheduling system may include an error detection unit configured to detect existence of an error in data received from a telecommunication device, an error frequency calculation unit configured to calculate an error frequency based at least in part on the error detected by the error detection unit, and a mode decision unit configured to decide a scheduling mode for the telecommunication device based at least in part on the error frequency calculated by the error frequency calculation unit.

Abstract: Disclosed are mobile communication devices and methods of a mobile communication device that determines that no response has been received within a predetermined period of time from a network to a transmission of an encoded data block in accordance with a commanded MCS. The device then determines an alternative MCS capable of coping better with variations in the radio environment with minimal damage or alteration than the commanded MCS and preemptively transmits the encoded data block in accordance with this more robust alternative MCS. In this way the mobile communication device does not continue failed attempts to transmit data in accordance with the commanded MCS. After the device receives notice of successful transmission of the encoded data block with the alternative MCS, the device will resume the use of the commanded MCS to transmit subsequent encoded data blocks.

Abstract: An adaptive search scheme leads to threshold voltages that have lower bit error rates over initial values. An initial reference voltage is used and data is measured for set steps in voltage about the initial value sufficient to fit a polynomial curve. A minimum is used to determine the lowest bit error rate and corresponding optimum threshold voltage. This voltage is adopted as the new threshold voltage for reading the given data.

Abstract: A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.

Abstract: An apparatus for providing a data integrity field implementation in a data processing system includes a controller operative to interface between a host device and a destination device in the data processing system for transferring at least one data block therebetween. The data processing system further includes an error detection module associated with the controller. The error detection module is operative to determine a probability of an error occurrence based at least in part on a measured current error rate for the data processing system. The controller is operative to implement an error correction methodology which is selectively adaptable as a function of the probability of an error occurrence.

Abstract: Marking memory chips as faulty when a fault is detected in data from the memory chip. Upon detecting that a plurality of memory chips are faulty, determining which of a plurality of memory channels contains the faulty memory chips. Marking one of a plurality of memory channels as failing in response to determining that the number of failing memory chips has exceeded a threshold.

Abstract: Provided are techniques for receiving a packet transmitted in conjunction with a security association associated with Internet Protocol Security (IPSec); determining, based upon the security Association that the packet is faulty; incrementing a count corresponding to previous faulty packets received; determining that the count exceeds a threshold; and disabling IPSec accelerator hardware in response to the determining that the count exceeds the threshold.

Abstract: Embodiments relate to a method including detecting a first error when reading a first cache line, recording a first address of the first error, detecting a second error when reading a second cache line and recording a second address of the second error. Embodiments also include comparing the first and second bitline address, comparing the first and second wordline address, activating a bitline delete mode based on matching first and second bitline addresses and not matching the first and second wordline addresses, detecting a third error when reading a third cache line, recording a third bitline address of the third error, comparing the second bitline address to a third bitline address and deleting a location corresponding to the third cache line from available cache locations based on the activated bitline delete mode and the third bitline address matching the second bitline address.

Abstract: A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.

Abstract: One embodiment of the present invention provides a system that facilitates transmission buffer under-run protection. During operation, the system stores bits of a data frame in a transmission buffer associated with an output port. The system also monitors the state of the transmission buffer and commences transmission of the data frame to the output port prior to complete reception of the data frame in the transmission buffer. The system further determines that the amount of data stored in the transmission buffer is below a predetermined threshold and inserts a number of predetermined unique bit sequences after the partially transmitted data frame, thereby allowing a receiving device to temporarily suspend reception of the data frame and resume reception at a later time without dropping the data frame.

Abstract: A method of processing signal data comprises receiving signal data, calculating a first k-th moment from the signal data based on a first number of samples N1, calculating a second k-th moment from the signal data based on a second number of samples N2, the first number N1 being different than the second number N2, calculating a combined error, the combined error being a function of the first and second k-th moments, classifying a data region of the signal data as flat if the combined error is below or equal to a threshold curve in the data region, and classifying a data region of the signal data as non-flat if the combined error is higher than the threshold curve in the data region.

Abstract: Marking memory chips as faulty when a fault is detected in data from the memory chip. Upon detecting that a plurality of memory chips are faulty, determining which of a plurality of memory channels contains the faulty memory chips. Marking one of a plurality of memory channels as failing in response to determining that the number of failing memory chips has exceeded a threshold.

Abstract: A controller system in which a plurality different main functions are integrated includes a plurality of microcontrollers. Each of the microcontrollers is associated with one of the main functions. At least one monitoring unit is implemented for the plurality of the main functions, for example a brake monitor and a comfort monitor. When the at least one monitoring unit detects a defect of a main function in the controller, only the defective main function is deactivated.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes: a data detector circuit, and a reliability monitor circuit. The data detector circuit is operable to apply a data detection algorithm to a data set to yield a detected output that includes soft data. The reliability monitor circuit is operable to determine a proxy error count based at least in part on the soft data, and to modify a parameter governing an operation of the data processing system based at least in part on the proxy error count.

Abstract: Provided are techniques for receiving a packet transmitted in conjunction with a security association associated with Internet Protocol Security (IPSec); determining, based upon the security Association that the packet is faulty; incrementing a count corresponding to previous faulty packets received; determining that the count exceeds a threshold; and disabling IPSec accelerator hardware in response to the determining that the count exceeds the threshold.

Abstract: A method is provided for determining with a first device, staleness of attestation measurements at a second device. The method includes booting up the second device at a first time, the second device having a communication portion, a security portion, a basic input/output system and a trusted protection module. Further, the method includes generating an initial counter based on the booting up of the second device at the first time. A current counter is then generated based on a second time after the first time. The method additionally includes providing a request to the second device from the first device, the request requesting booting information and current information, the booting information being based on the initial counter, the current information being based on the current counter. Still further, the method includes providing a response to the first device from the second device, the response including the booting information and the current information.

Abstract: An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to (i) generate a reference voltage used by a memory circuit in a first read of a set of data and (ii) adjust the reference voltage based on a plurality of parameters to lower an error rate in a second read of the set from the memory circuit. The second circuit may be configured to update the parameters in response to an error correction applied to the set after the first read from the memory circuit. The memory circuit is generally configured to store the data in a nonvolatile condition by adjusting a plurality of threshold voltages.

Abstract: A data processing system and method for regulating a voltage supply to functional circuitry configured to operate from a variable voltage supply, the functional circuitry having at least one error correction circuit configured to detect and repair errors in operation of the functional circuitry. Voltage regulator circuitry provides the voltage supply to the functional circuitry, and modifies the voltage level of the voltage supply based on a feedback control signal. Error rate history circuitry receives error indications from the error correction circuit during operation of the functional circuitry and generates error rate history information therefrom. An adaptive controller then generates the feedback control signal in dependence on the error rate history information such that the adaptive controller adjusts the feedback control signal over time having regard to the error rate history information in order to obtain a predetermined target non-zero error rate within the functional circuitry.

Abstract: Embodiments relate to a method for bitline deletion include, based on detecting a high bitline error rate condition in the cache at a selected bitline address, wherein the high bitline error rate condition indicates a high rate of errors at the selected bitline address, activating the programmable switch in the cache. The method also includes, based on the programmable switch being activated and encountering an error associated with the selected bitline address, automatically deleting, by the computer system, one or more cache lines associated with subsequent errors in the cache regardless of an address of the subsequent errors based on the activated programmable switch, wherein the automatic line deletion indicates a line is unavailable.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.

Abstract: Embodiments relate to a method for bitline deletion include, based on detecting a high bitline error rate condition in the cache at a selected bitline address, wherein the high bitline error rate condition indicates a high rate of errors at the selected bitline address, activating the programmable switch in the cache. The method also includes, based on the programmable switch being activated and encountering an error associated with the selected bitline address, automatically deleting, by the computer system, one or more cache lines associated with subsequent errors in the cache regardless of an address of the subsequent errors based on the activated programmable switch, wherein the automatic line deletion indicates a line is unavailable.

Abstract: Embodiments of the invention describe methods, systems and apparatuses to improve solid state device (SSD) write speed by efficiently utilizing error correction code executed for the device. SSDs may be comprised of several NAND memory devices. It is understood that such devices tend to have a raw bit error rate (RBER) that is related to the program/erase cycle count for the device. Embodiments of the invention efficiently use system ECC by changing the operating conditions of the SSD to better utilize the robustness of the implemented ECC algorithm. For example, embodiments of the invention may alter the programming voltage supplied to an SSD to increase write speed; such an increase may increase the RBER of the device, but will not affect the accuracy of such operations due to the ECC that is provisioned for end of life storage fidelity (i.e., the RBER that will occur at the end of life).

Abstract: A system involves a first SerDes link from a first integrated circuit (IC) to a second IC and a second link from the second IC to the first IC. Power consumption settings in circuitry of the first link are adjusted to control power consumption such that the bit error rate of the first link is maintained in a range, where the lower bound of the range is substantially greater than zero. Power consumption settings in circuitry for the second link are adjusted to control power consumption such that the bit error rate of the second link is maintained in range, where the lower bound of the range is substantially greater than zero. In one example, circuitry in the second IC detects errors in the first link and reports back via the second link. The first IC uses the reported information to determine a bit error rate for the first link.

Abstract: Method for transmitting data in a transmission system, the data being transmitted in the form of packets including a compressed header field and a data field and according to a format suited to the transmission system comprising the following steps: recovering the data packet to be transmitted including a compressed header and useful data, identifying the header part from the useful-data part, applying a corrector coding which is selected at the level of the header, and providing the resulting new packet to the link layer, while also communicating the protection mode used, generating the link header according to the transmission format of the relevant transmission system integrating the mode of protection used, and the adaptation of the CRC checksum of the link layer, on reception, performing the error corrector decoding in two steps.

Abstract: A decoding device includes a decoding unit that decodes control data to generate decode data, the control data indicating a state of a radio propagation channel; a reliability calculating unit that calculates a reliability indicator indicating a reliability of the decode data; and an outputting unit that outputs decode data whose reliability indicator is larger than a specified threshold; wherein the reliability calculating unit calculates the reliability indicator of decode data to be decoded, based on a similarity indicator indicating a similarity between the decode data to be decoded and previous decode data whose reliability indicator is larger than the threshold.

Abstract: A method for initiating a storage window of a receiving end in a wireless communications system, which periodically retransmits previously transmitted data packets in an unacknowledged mode, includes receiving a first PDU after a receiving entity of the receiving end is established, re-established, or after a timer expires, and initiating a state variable, which is defined to be a sequence number of the highest numbered packet that has been received, according to a sequence number of the first received packet. An example of the wireless communications system is the Universal Mobile Telecommunications System (UMTS) with a multimedia broadcast/multicast service (MBMS) application.

Abstract: An apparatus for providing a data integrity field implementation in a data processing system includes a controller operative to interface between a host device and a destination device in the data processing system for transferring at least one data block therebetween. The data processing system further includes an error detection module associated with the controller. The error detection module is operative to determine a probability of an error occurrence based at least in part on a measured current error rate for the data processing system. The controller is operative to implement an error correction methodology which is selectively adaptable as a function of the probability of an error occurrence.

Abstract: A mobile station downloading an object over a broadcast channel uses a repair service to obtain data that was received in error during the original broadcast. The mobile station sets a repair threshold for the download object and invokes repair if the amount of errors is less than the repair threshold. If the amount of errors exceeds the repair threshold, the mobile station treats the download attempt as having failed and may send a new request if download is still desired.

Abstract: A method to increase spectral efficiency in a communication system is described herein. The communication system includes at least one mobile station and is capable of transmitting messages encoded according to a plurality of available modulation coding schemes (“MCSs”). Each available MCS includes a modulation scheme and an effective coding rate. The MCSs are indexed according to increasing complexity. A signal-to-interference ratio (“SINR”) is determined which is sufficient to satisfy a predetermined frame error rate (“FER”). A first MCS and a corresponding amount of transmissions needed to satisfy the predetermined FER at the SINR using the first MCS are determined. The first MCS has a higher effective coding rate than a second MCS. The second MCS sufficiently satisfies the predetermined FER at the SINR in a single transmission. A message encoded according to the first MCS is transmitted through the communication system using hybrid automatic repeat request (“HARQ”).

Abstract: The instant disclosure relates to a raw data compression method for the fabrication process. The method includes the steps of: inputting into a signal converter a collection of raw data points representing operational parameter of a semiconductor equipment within a predetermined time period; obtaining an approximation of the raw data points with a Fourier series; computing the Fourier coefficients and the residuals between the raw data points and the corresponding predicted values predicted by the Fourier series; determining if the residuals exceed an error threshold; recording and storing the Fourier coefficients as the compressed data if none of the residuals exceeds the error threshold; and recording the raw data point as abnormal data point if the corresponding residual exceeds the error threshold before recording and storing the Fourier coefficients and the abnormal data point as the compressed data.

Abstract: In one embodiment, a method for testing adjustment and configuration is disclosed. The method can include accessing source code of a test framework that is configured for testing a module, creating a configuration folder having a property override for a test suite for the module testing, determining a source root folder for the test suite, starting the test framework by passing in an identifier for the test suite, and adding a custom test to the source root folder using the configuration folder to customize the test suite. The method can further include compiling the test framework with each of the plurality of test folders enabled. The method also may use a refactoring tool to make changes in a file within the test framework.

Abstract: A memory system includes an error detection circuit having an error counter. When a bit error rate (BER) determined by the error counter exceeds a reference BER, the memory system reduces the BER by adjusting its operating speed or operating voltage, re-performing data training or impedance matching, or by adjusting a data swing width. Accordingly, a method of controlling a bit error rate may be performed, and a system hang is prevented.

Abstract: The subject disclosure describes a method for reducing a sector error rate in a flash memory device, the method comprising, identifying a first program verify level having a first value, selecting an adjustment value for the first program verify level and programming the adjustment value to the first program verify level to replace the first value and to shift a first programming distribution associated with the first program verify level, wherein the shift in the first programming distribution is associated with a decrease in a sector error rate, wherein the shift in the first programming distribution is associated with an increase in a bit error rate. A flash storage device and computer-readable media are also provided.

Abstract: Apparatus and methods are disclosed, including a method of programming involving determining an error rate for the memory cells, and programming the memory cells using a charge state level for a charge state that is based at least in part on the determined error rate.

Abstract: Subject matter disclosed herein relates to a memory device, and more particularly to read performance of phase change memory.

Abstract: Embodiments herein provide data recovery techniques and configurations for solid state memory devices. For example, a method includes identifying a hard error associated with a cell of a solid state memory device, providing a location of the cell having the identified hard error to a decoder to recover data originally programmed to the cell, and recovering the data originally programmed to the cell using the decoder. Other embodiments may be described and/or claimed.

Abstract: Technologies are generally described for enhancing communication performance. In some examples, a scheduling system may include an error detection unit configured to detect existence of an error in data received from a telecommunication device, an error frequency calculation unit configured to calculate an error frequency based at least in part on the error detected by the error detection unit, and a mode decision unit configured to decide a scheduling mode for the telecommunication device based at least in part on the error frequency calculated by the error frequency calculation unit.