Loop-back Patents (Class 714/716)
  • Patent number: 10372649
    Abstract: An approach is provided in which an information handling system suspends operation of one or more components corresponding to a PCIe link that is operating at a reduced capacity. The information handling system then trains the PCIe link to an increased capacity while the one or more components are suspended in operation. In turn, the information handling system resumes operation of the one or more components and restores the PCIe link to the increased capacity.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: August 6, 2019
    Assignee: International Business Machines Corporation
    Inventors: Curtis S. Eide, Christopher J. Engel, Aditya Saripalli
  • Patent number: 10313222
    Abstract: An adapter is configured to connect to a network. The adapter including a controller configured to receive a stream of network communication from a computer system physically connected to the adapter. The controller is further configured to detect a first identifier. The first identifier is related to a first communication unit of the stream of network communication. In response to detecting the first identifier, the controller is further configured to direct the first communication unit away from the network and back toward the controller through a loopback pathway. The controller is further configured to direct the stream of network communication away from the computer system and to the network.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: June 4, 2019
    Assignee: International Business Machines Corporation
    Inventor: Mehulkumar J. Patel
  • Patent number: 10116399
    Abstract: A circuit arrangement includes a transceiver unit, a switching device coupled to the transceiver unit with a terminal and a control device coupled to the switching device. The control device is configured to operate in a first and in a second mode of operation. In the first mode of operation, the switching device is configured by the control device such that a first signal is routed from the transceiver unit via the switching device back to the transceiver unit in a feedback loop. In the second mode of operation, the switching device is configured by the control device such that a second signal is routed from the transceiver unit via the switching device to the terminal or the second signal is routed from the terminal via the switching device to the transceiver unit.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: October 30, 2018
    Assignee: SnapTrack, Inc.
    Inventors: Pasi Lehtonen, Harri Pellikka, Marko Alanen, Pasi Tikka, Sami Kalajo, Pekka Ikonen
  • Patent number: 9852036
    Abstract: A novel diagnostics and verifiable input/output (DVIO) channel may reduce fixed diagnostic circuitry and allow standard input/output channels to be repurposed as diagnostics for specific deployments. The DVIO channel may include a digital input sub-channel and a digital output sub-channel, with each sub-channel including basic protection and diagnostic circuitry for performing basic diagnostics. The two sub-channels may be used independently of each other, and they may also be coupled together to create an enhanced digital input or digital output channel, which is capable of performing more advanced diagnostics such as output readback or test pulse generation, for example. Multiple DVIO channels may be coupled together to create a multiple-channel digital input or digital output with redundant signal paths. In this way the input/output resources may be configured to meet the specific needs of a given application, and minimize the test and diagnostic circuitry required in traditional implementations.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: December 26, 2017
    Assignee: NATIONAL INSTRUMENTS CORPORATION
    Inventor: Joseph E. Peck
  • Patent number: 9401760
    Abstract: A diagnostic testing utility is used to perform single link diagnostics tests including an electrical loopback test, an optical loopback test, a link traffic test, and a link distance measurement test. To perform the diagnostic tests, two ports at each end of a link are identified and then statically configured by a user. The ports will be configured as D_Ports and as such will be isolated from the fabric with no data traffic flowing through them. The ports will then be used to send test frames to perform the diagnostic tests.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: July 26, 2016
    Assignee: Brocade Communications Systems, Inc.
    Inventors: David Aaron Skirmont, Saumitra Buragohain, Balakrishna Wusirika, Badrinath Kollu, Kyuh Kim
  • Patent number: 9356743
    Abstract: A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: May 31, 2016
    Assignee: Rambus Inc.
    Inventors: Jared Zerbe, Pak Shing Chau, William Franklin Stonecypher
  • Patent number: 9324397
    Abstract: A configurable die including a logic element configured to communicate a control and address (CA) signal and a data (DQ) signal, and a first generic physical interface (PHY) and a second generic PHY in communication with the logic element, wherein each of the first generic PHY and the second generic PHY is configurable as a CA PHY and as a DQ PHY, and wherein the logic element is configurable to communicate the CA signal and the DQ signal to different ones of the first and second generic PHYs.
    Type: Grant
    Filed: January 16, 2015
    Date of Patent: April 26, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Kunal Mukesh Desai, Piyush Gupta, Bernie Jord Yang, Umesh Madhusudan Rao
  • Patent number: 8996953
    Abstract: Exemplary embodiments of the present invention disclose a method and system for monitoring a first Error Correcting Code (ECC) device for failure and replacing the first ECC device with a second ECC device if the first ECC device begins to fail or fails. In a step, an exemplary embodiment detects that a specified number of correctable errors is exceeded. In another step, an exemplary embodiment detects the occurrence of an uncorrectable error. In another step, an exemplary embodiment performs a loopback test on an ECC device if a specified number of correctable errors is exceeded or if an uncorrectable error occurs. In another step, an exemplary embodiment replaces an ECC device that fails the loopback test with an ECC device that passes a loopback test.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: March 31, 2015
    Assignee: International Business Machines Corporation
    Inventors: Edgar R. Cordero, Timothy J. Dell, Joab D. Henderson, Jeffrey A. Sabrowski, Anuwat Saetow, Saravanan Sethuraman
  • Patent number: 8996256
    Abstract: In each sensor unit, when a sensor control unit cannot detect current flowing to an output side, its address is set to the same address as a sensor unit of the last stage. In an ECU, if the set address and characteristic information of each sensor unit are not stored in a memory unit when the set addresses and the characteristic information of all the sensor units are received by an ECU control unit, the received set addresses and the characteristic information are stored. A failure check unit checks received characteristic information received by the ECU control unit with characteristic information stored in the memory unit. If one characteristic information is in disagreement, a sensor unit having such characteristic information is determined to be failing. If plural characteristic information are in disagreement, a sensor unit having characteristic information and closest to the ECU is determined to be failing.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: March 31, 2015
    Assignee: Denso Corporation
    Inventor: Takashi Inamoto
  • Patent number: 8904248
    Abstract: A self-test loopback apparatus for an interface is disclosed. In one embodiment, a bidirectional interface of an integrated circuit includes a transmitter coupled to an external pin, a first receiver coupled to the external pin, and a second receiver coupled to the external pin. During operation in a test mode, the first receiver may be disabled. The transmitter may transmit test patterns generated by a built-in self-test (BIST) circuit, and compare those test patterns to patterns received by the second receiver. The second receiver may be implemented as a Schmitt trigger (wherein the first receiver may be a standard single-bit comparator). When operating in functional mode, the second receiver may be disabled.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: December 2, 2014
    Assignee: Apple Inc.
    Inventors: Brian S. Park, Gregory S. Scott, Anh T. Hoang
  • Patent number: 8843794
    Abstract: Techniques and mechanisms for evaluating I/O buffer circuits. In an embodiment, test rounds are performed for a device including the I/O buffer circuits, each of the test rounds comprising a respective loop-back test for each of the I/O buffer circuits. Each of the test rounds corresponds to a different respective delay between a transmit clock signal and a receive clock signal. In another embodiment, a first test round indicates a failure condition for at least one I/O buffer circuit and a second test round indicates the failure condition for each of the I/O buffer circuits. Evaluation of the I/O buffer circuits determines whether the device satisfies a test condition, where the determining is based on a difference between the delay corresponding to the first test round and the delay corresponding to the second test round.
    Type: Grant
    Filed: September 24, 2012
    Date of Patent: September 23, 2014
    Assignee: Intel Corporation
    Inventors: Christopher J. Nelson, Tak M. Mak, David J. Zimmerman, Pete D. Vogt
  • Patent number: 8817635
    Abstract: A method for verifying compliance of a communication device with one or more requirement specifications is disclosed.
    Type: Grant
    Filed: May 6, 2009
    Date of Patent: August 26, 2014
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Leif Mattisson, Béla Rathonyi
  • Patent number: 8812918
    Abstract: A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: August 19, 2014
    Assignee: Rambus Inc.
    Inventors: Jared Zerbe, Pak Shing Chau, William Franklin Stonecypher
  • Patent number: 8782477
    Abstract: A loopback card includes a connector configured to connect to an IO interface and emulate a storage device interface. The connector includes a port configured to receive a set of signals from the IO interface and transmit them to a redriver. The connector is configured to receive the set of signals from the redriver and transmit them from the redriver to the IO interface. The connector includes control signal inputs configured to receive control signals from the IO interface. The connector further includes one or more logic gates configured to receive the control signals. The one or more logic gates apply a logic operation on the control signals to generate an output and route the output to the IO interface through the connector. The redriver is operably connected to the port and configured to receive the set of signals from the port and transmit them back to the port.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: July 15, 2014
    Assignee: Jabil Circuit, Inc.
    Inventors: Craig Anthony Klein, Aleksander Jaworski, John Roy Gaudet, Steven Scott Burroughs
  • Patent number: 8767801
    Abstract: The ability of clock and data recovery (“CDR”) circuitry on an integrated circuit (“IC”) to handle jitter in a serial data input signal can be tested by using transmitter circuitry on the IC to produce a serial data output signal whose time base has been subjected to modulation. Loop-back circuitry on the IC may be used to apply the serial data output signal to the CDR circuitry as the serial data input signal of the CDR circuitry. Modulation circuitry on the IC may be used to cause the above modulation of the time base of the serial data output signal.
    Type: Grant
    Filed: March 23, 2010
    Date of Patent: July 1, 2014
    Assignee: Altera Corporation
    Inventors: Allen Chan, Wilson Wong
  • Patent number: 8756469
    Abstract: A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: June 17, 2014
    Assignee: Rambus Inc.
    Inventors: Jared Zerbe, Pak Shing Chau, William Franklin Stonecypher
  • Patent number: 8644434
    Abstract: An apparatus for performing sequence detection on a stream of incoming bits comprises a memory and circuitry coupled to the memory. The circuitry is operative, for each bit of the stream of incoming bits, to overwrite a first binary number presently stored in the memory with a second binary number, and to provide an output indicative of when the second binary number is equal to a predetermined value. The output indicative of when the second binary number is equal to the predetermined value is, in turn, indicative of when a binary number constructed by the stream of incoming bits is divisible by a prescribed integer.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: February 4, 2014
    Assignee: LSI Corporation
    Inventor: Sanjib Paul
  • Patent number: 8638851
    Abstract: A video coding system and method for increasing a transmitted output bit rate of a video encoding system by altering the content of the bit stream. A video encoder may receive a coding mode signal from a computer application for coding source video data, the coding mode signal indicating a target bit rate having a risk factor related to transmission error associated to the target bit rate. The coded bitstream may be modified based on the risk factor indicated in the coding mode signal. A modified coded bitstream may be outputted at the target bit rate and at a reduced coding efficiency, and the channel may be tested for transmission errors. Based on the test results, a revised coding mode signal indicating the same target bit rate, but a revised risk factor may be provided. The coded bitstream may be revised by removing the modifications previously made to the coded bitstream and a revised coded bitstream having greater coding efficiency may be output at the target bit rate.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: January 28, 2014
    Assignee: Apple Inc.
    Inventors: Hyeonkuk Jeong, Xiaosong Zhou, Joe Abuan, Xiaojin Shi, Hsi-Jung Wu, James Oliver Normile
  • Patent number: 8619599
    Abstract: Methods and systems for implementing self-testing of packet processing devices are disclosed. For example, a packet-processing device can include a plurality of ports having a receive media access controller (RX MAC) and a transmit media access controller (TX MAC). The TX MAC of a first port is selectably configurable to loop back packets to its respective RX MAC during the self-testing. The packet-processing device can further include a switching engine configured to provide a test packet received from a packet generator to the TX MAC of the first port, and route to the TX MAC of one or more second ports at least the test packet received from the RX MAC of the first port, or a copy of the received test packet, after the received test packet or its copy has been looped-back one or more times between the TX MAC and the RX MAC of the first port.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: December 31, 2013
    Assignee: Marvell International Ltd.
    Inventor: Vladimir Even
  • Patent number: 8607104
    Abstract: A memory loopback system and method including an address/command transmit source configured to transmit a command and associated address through an address/command path. A transmit data source is configured to transmit write data associated with the command through a write path. Test control logic is configured to generate gaps between successive commands. A loopback connection is configured to route the write data from the write path to a read path. A data comparator is configured to compare the data received via the read path to a receive data source and generate a data loopback status output. Pattern generation logic can be configured to generate a loopback strobe, the loopback strobe being coupled to the read path. The pattern generation logic may be configured to synthesize a read strobe based on the test control logic and to use the synthesized read strobe as the loopback strobe.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: December 10, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Hanwoo Cho, Tahsin Askar, Philip E. Madrid, Guhan Krishnan, Brian W. Amick, Shawn Searles, Ryan J. Hensley
  • Patent number: 8553565
    Abstract: A switch apparatus providing with a loop detection function sets a port identification to a port which activates the loop detection function, only receives the loop detection frame by a high-order port in the switch apparatus connected with a backbone network or a high-order switch apparatus on the basis of the port identification set previously, and controls an inactivation of a sending source low-order port that sent the loop detection frame, when the loop detection frame is received by the high-order port.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: October 8, 2013
    Assignee: Alaxala Networks Corporation
    Inventors: Kazunori Kamachi, Hiroyuki Dei
  • Patent number: 8543873
    Abstract: A method and apparatus for multi-site testing of computer memory devices. An embodiment of a method of testing computer memory devices includes coupling multiple memory devices, each memory device having a serializer output and a deserializer input, wherein the serializer output of a first memory device is coupled with a deserializer input of one or more of the memory devices of the plurality of memory devices. The method further includes producing test signal patterns using a test generator of each memory device, serializing the test signal pattern at each memory device, and transmitting the serialized test pattern for testing of the memory devices, wherein testing of the memory devices includes a first test mode and a second test mode.
    Type: Grant
    Filed: January 6, 2010
    Date of Patent: September 24, 2013
    Assignee: Silicon Image, Inc.
    Inventor: Chinsong Sul
  • Patent number: 8533543
    Abstract: In accordance with an aspect of the application, there is provided a system for testing, including a first chip, a second chip, and first and second connections. The first connection is configured to couple a first pin of the first chip to a first pin of the second chip, and to transmit an initial signal from the first chip to the second chip. The second connection is configured to couple a second pin of the first chip to a second pin of the second chip to return the signal as a returned signal to the first chip. The first chip comprises comparison circuitry configured to compare the returned signal with the initial signal.
    Type: Grant
    Filed: March 30, 2009
    Date of Patent: September 10, 2013
    Assignee: Infineon Technologies AG
    Inventors: Jens Barrenscheen, Harry Siebert
  • Patent number: 8516238
    Abstract: Circuits, methods, and apparatus that allow signals that are compliant with multiple standards to share a common connector on an electronic device. An exemplary embodiment of the present invention provides a connector that provides signals compatible with a legacy standard in one mode and a newer standard in another mode.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: August 20, 2013
    Assignee: Apple Inc.
    Inventors: William P. Cornelius, William O. Ferry, James E. Orr
  • Patent number: 8471599
    Abstract: In an adjustable voltage examining module, while a logic tester issues an input signal to an audio module under test, upper/low-threshold reference signals are simultaneously issued to an adjustable voltage comparing circuit. While the adjustable voltage comparing circuit receives a signal under test returned by the to-be-examined audio module after a while, the adjustable voltage comparing circuit loads both an high-threshold reference voltage and a low-threshold reference voltage respectively indicated by the reference upper/low-threshold signal so as to compare both the upper and low-threshold reference voltages with the signal under test. Therefore, while the signal under test is examined to acquire a voltage level between voltage levels of the upper and low-threshold reference signals, precise operations of the audio module under test are assured, and time wasted by continuously-issued interrupt is saved.
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: June 25, 2013
    Assignee: Princeton Technology Corporation
    Inventors: Yang-Han Lee, Yung-Yu Wu
  • Patent number: 8384569
    Abstract: A stochastic signal generation circuit includes a signal output circuit and a signal processing circuit connected with the signal output circuit. The signal output circuit includes two matching semiconductor components, wherein the signal output circuit detects a slight mismatch between the two matching semiconductor components, converts the detected slight mismatch into a corresponding electric signal, amplifies the electric signal, and outputs an analog voltage signal. The signal processing circuit converts the analog voltage signal into a stochastic digital signal. Also, a method for generating a stochastic signal is provided. The present invention decreases the cost of the integrated circuit, and better ensures the information security of the electronic products.
    Type: Grant
    Filed: April 20, 2011
    Date of Patent: February 26, 2013
    Assignee: IPGoal Microelectronics (SiChuan) Co., Ltd
    Inventor: Guojun Zhu
  • Patent number: 8363706
    Abstract: A system and method for communication provides an adaptation value for at least one communication parameter, the adaptation value describes a variation of the communication parameter to be enabled during that data communication. The communication parameter is determined such that the variation indicated by the adaptation value is possible during data communication without violating a limit for the communication parameter.
    Type: Grant
    Filed: May 10, 2007
    Date of Patent: January 29, 2013
    Assignee: Infineon Technologies AG
    Inventor: Dietmar Schoppmeier
  • Patent number: 8301941
    Abstract: An apparatus may include an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller may be programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller may be configured to receive a first write operation from the processor over the interconnect. The memory controller may be configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller may be further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect.
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: October 30, 2012
    Assignee: Apple Inc.
    Inventors: Luka Bodrozic, Sukalpa Biswas, Hao Chen, Sridhar P. Subramanian, James B. Keller
  • Patent number: 8286197
    Abstract: Methods and systems for comprehensive socket API loopback processing on a computing device. In an exemplary method and system, a socket API processes loopback calls without resort to a TCP/IP protocol stock or lower level systems (e.g. network drivers), reducing overhead requirements and processing burdens imposed on the TCP/IP stack and lower level systems and improving overall computing device performance.
    Type: Grant
    Filed: July 17, 2008
    Date of Patent: October 9, 2012
    Assignee: Sharp Laboratories of America, Inc.
    Inventor: Swee Huat Sng
  • Patent number: 8286039
    Abstract: Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: October 9, 2012
    Assignee: Intel Corporation
    Inventors: Pete D. Vogt, Dennis W. Brzezinski, Warren R. Morrow
  • Patent number: 8279759
    Abstract: In one embodiment, a system includes a first network device configured to communicate on a first communication layer, and a second network device configured to communicate on a second communication layer. The system further includes a router communicatively coupled to the first and second network devices through at least one network path. The at least one router includes a ping inter-working unit configured to support the transmission of a message between the first and second network devices through the at least one network path.
    Type: Grant
    Filed: March 7, 2006
    Date of Patent: October 2, 2012
    Assignee: Verizon Services Corp.
    Inventor: Lawrence W. Jones
  • Patent number: 8266482
    Abstract: An integrated circuit includes a signal source and a signal destination linked by a signal path. Error correction codes (e.g. Hamming codes) are applied to the signals to be transmitted. Errors detected in the signal transmission are used to control an operating parameter of the signal path, such as signal voltage level, body bias voltage, clock frequency and/or temperature. The control applied is closed-loop feedback control seeking to maintain a finite non-zero predetermined error rate. The technique can also be used between a memory accessing integrated circuit and a separate memory integrated circuit. Furthermore, the technique can be used to provide fixed, but differing operating parameters for signal lines within a signal path.
    Type: Grant
    Filed: January 31, 2006
    Date of Patent: September 11, 2012
    Assignee: ARM Limited
    Inventors: Andrew David Tune, Alistair Crone Bruce, Simon Crossley, Robin Hotchkiss
  • Patent number: 8250416
    Abstract: Redundant acknowledgment between agents performing a loopback test over bidirectional communications bus is described. In one example, in a processor including a communications agent coupled to a bidirectional communications bus, the communications agent initiates loopback communications to a second agent, sends a packet including a redundant acknowledgment sequence to the second agent, receives the packet including the redundant acknowledgement sequence looped back from the second agent, determines whether the received redundant acknowledgment sequence is valid, sends a test sequence to the second agent, receives the test sequence looped back, and if the received redundant acknowledgment sequence is determined to be valid, then checks the received test sequence.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: August 21, 2012
    Assignee: Intel Corporation
    Inventors: Tim Frodsham, Zale Schoenborn, Sanjay Dabral, Muraleedhara Navada
  • Patent number: 8234530
    Abstract: A built-in self test circuit includes a pattern generator, an elastic buffer, a symbol detector, and a comparison unit. A pattern generator generates a first test pattern to test a port under test and then a result pattern is gotten and stored in the elastic buffer. The symbol detector detects if a starting symbol exists in the test result pattern. If it exists, a second test pattern is generated to be compared with the test result pattern. As a result, a reliability of data transmission of the port under test is determined.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: July 31, 2012
    Assignee: Via Technologies Inc.
    Inventor: Wayne Tseng
  • Patent number: 8214706
    Abstract: A semiconductor device including an electronic circuit, a memory, and an error detecting module. The electronic circuit is configured to receive an input signal having been generated by a test module, and generate an output signal based on the input signal. The memory is configured to store a predetermined output value that is expected to be output from the electronic circuit based on the electronic receiving the input signal, wherein the predetermined output value is stored in the memory prior to the input signal being generated by the test module. The error detecting module is configured to (i) generate a sample value of the output signal, (ii) compare the sample value of the output signal to the predetermined output value stored in the memory, and (iii) generate a result signal that indicates whether the sample value of the output signal matches the predetermined output value.
    Type: Grant
    Filed: March 1, 2010
    Date of Patent: July 3, 2012
    Assignee: Marvell International Ltd.
    Inventors: Masayuki Urabe, Akio Goto
  • Patent number: 8199858
    Abstract: The present invention provides an OOB detection circuit capable of making accurate signal determination even in the case where a characteristic fluctuation occurs in an analog circuit, thereby preventing deterioration in the yield of a product. To an amplitude determining circuit, a characteristic adjustment register for changing setting of an amplitude threshold adjustment mechanism for distinguishing a burst and a squelch from each other provided for the amplitude determining circuit is coupled. The characteristic adjustment register is controlled by a self determination circuit. An output of the amplitude determination circuit is supplied to a time determining circuit and also to the self determination circuit. On the basis of the output of the amplitude determining circuit, the self determination circuit controls the characteristic adjustment register.
    Type: Grant
    Filed: December 6, 2008
    Date of Patent: June 12, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuaki Kurooka, Kenichi Shimizu
  • Patent number: 8184542
    Abstract: Verifying a customer premises connection to a communication system having a plurality of ports, each of which serves a corresponding customer premises. A known quantity of data is transmitted to an address corresponding to a specific customer premises. A quantity of data received at a first trial port of the plurality of ports is monitored. If the known quantity of data matches the monitored quantity of data received at the first trial port, then the customer premises connection to the first trial port is thereby verified. If the known quantity of data does not match the monitored quantity of data received at the first trial port, then quantity of data received at a second trial port of the plurality of ports is monitored and, if the known quantity of data matches the monitored quantity of data received at the second trial port, then the customer premises connection to the second trial port is thereby verified.
    Type: Grant
    Filed: December 8, 2005
    Date of Patent: May 22, 2012
    Assignee: AT&T Intellectual Property I, L.P.
    Inventor: Jie Su
  • Patent number: 8169924
    Abstract: A provider edge (PE) node of a network operates to send a trace path message over the network to a receiver PE node, the trace path message recording a list of intermediate nodes of a unicast path from the PE node to the receiver PE node; and receive a join message initiated from the receiver PE node, the join message using the list to propagate to the source PE node through the intermediate nodes such that a branch of a multicast tree is aligned with the unicast path. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b).
    Type: Grant
    Filed: December 7, 2005
    Date of Patent: May 1, 2012
    Assignee: Cisco Technology, Inc.
    Inventors: Ali Sajassi, Dino Farinacci, John M. Zwiebel, Daniel Alvarez
  • Publication number: 20120072787
    Abstract: In one embodiment, an apparatus comprises an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller is programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller is configured to receive a first write operation from the processor over the interconnect. The memory controller is configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller is further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect.
    Type: Application
    Filed: November 28, 2011
    Publication date: March 22, 2012
    Inventors: Luka Bodrozic, Sukalpa Biswas, Hao Chen, Sridhar P. Subramanian, James B. Keller
  • Patent number: 8135999
    Abstract: Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: March 13, 2012
    Assignee: Intel Corporation
    Inventors: Warren Morrow, Pete Vogt, Dennis Brzezinski
  • Patent number: 8135872
    Abstract: A USB controller and a testing method of the USB controller are disclosed. The USB controller includes a sequence control unit for outputting a transmitting enable signal and a receiving enable signal, and for controlling a sequence of transmission and reception of data based on the transmitting enable signal and the receiving enable signal; a driver unit for transmitting data; a receiver unit for receiving data; a register for setting up a test mode wherein a loop-back test of the USB controller is performed; and a switching unit for providing one of the transmitting enable signal to the receiver unit and the receiving enable signal to the driver unit, if the test mode is set up in the register; wherein the loop-back test is performed if the test mode is set up in the register.
    Type: Grant
    Filed: February 13, 2008
    Date of Patent: March 13, 2012
    Assignee: Ricoh Company, Ltd.
    Inventor: Shinji Sakaguchi
  • Patent number: 8122305
    Abstract: A system for operating a data storage device having a plurality of sectors and at least one port, each port having a transmitter and a receiver, is disclosed. In one embodiment the system includes coupling at least one of the transmitters to at least one of the receivers, providing power to the data storage device, detecting that the transmitter is coupled to the receiver, and executing code for exercising the data storage device.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: February 21, 2012
    Assignee: Dell Products L.P.
    Inventors: Charles Jarboe, Robert Clausen, Jeffrey C. Hailey, Mark Lindholm, Raymond McCormick, Kevin Marks
  • Patent number: 8098766
    Abstract: A transceiver includes a receiver unit including a clock and data recovery unit. The transceiver includes a transmitter unit and a digital core coupled to the receiver unit and the transmitter unit. A switch circuit is positioned after the clock and data recovery unit, and is configured to route data from the receiver unit to the transmitter unit in a test mode of the transceiver.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: January 17, 2012
    Assignee: Infineon Technologies AG
    Inventor: Holger Wenske
  • Patent number: 8091001
    Abstract: Testing of combinatorial logic in a programmable device is provided by routing input and/or output test values as signals from and back to dedicated logic through programming circuitry in programmable logic. Some embodiments of the present invention provide for a method for testing functional logic block of an application-specific standard product (ASSP) in a programmable logic device, the method comprising: storing an input value into a register; passing the input value from the register to combinatorial logic; producing an output value from the combinatorial logic; passing the output value from the combinatorial logic to the register; saving the output value in the register; and reading the output value out of the register.
    Type: Grant
    Filed: November 30, 2006
    Date of Patent: January 3, 2012
    Assignee: QuickLogic Corporation
    Inventors: Stephen U. Yao, Darwin D. Q. Samson, Ket-Chong Yap
  • Patent number: 8086915
    Abstract: In one embodiment, an apparatus comprises an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller is programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller is configured to receive a first write operation from the processor over the interconnect. The memory controller is configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller is further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect.
    Type: Grant
    Filed: October 21, 2010
    Date of Patent: December 27, 2011
    Assignee: Apple Inc.
    Inventors: Luka Bodrozic, Sukalpa Biswas, Hao Chen, Sridhar P. Subramanian, James B. Keller
  • Patent number: 8074129
    Abstract: A memory apparatus is disclosed, comprising a memory device under test, a reduced-pin-count device and a built-in self test device. The reduced-pin-count device is used to find a faulty cell address in the memory device under test during a pre-fuse stage. The built-in self test device is used to detect whether the memory device under test has any error during a post-fuse stage. The memory apparatus is capable of promptly finding the address of a defect cell in the memory device under test such that repairs can be performed during a fuse stage. Furthermore, the invention reduces the pin count required during testing the memory device under test. Thus, the cost of testing equipment is reduced and the performance of memory testing is enhanced.
    Type: Grant
    Filed: June 11, 2007
    Date of Patent: December 6, 2011
    Assignee: Winbond Electronics Corp.
    Inventor: Fan-Sheng Kung
  • Patent number: 8069378
    Abstract: A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.
    Type: Grant
    Filed: June 14, 2010
    Date of Patent: November 29, 2011
    Assignee: Rambus Inc.
    Inventors: Jared Zerbe, Pak Shing Chau, William Franklin Stonecypher
  • Patent number: 8051350
    Abstract: A built-in self test circuit includes a pattern generator, an elastic buffer, a symbol detector, and a comparison unit. A pattern generator generates a first test pattern to test a port under test and then a result pattern is gotten and stored in the elastic buffer. The symbol detector detects if a starting symbol exists in the test result pattern. If it exists, a second test pattern is generated to be compared with the test result pattern. As a result, a reliability of data transmission of the port under test is determined.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: November 1, 2011
    Assignee: Via Technologies Inc.
    Inventor: Wayne Tseng
  • Patent number: 8037356
    Abstract: A system for validating communications between a plurality of processors is disclosed. The system includes a plurality of loop back paths, and each of the loop back paths is coupled to a corresponding one of the plurality of processors. In addition, each loop back path is configured to attenuate one of a plurality of signals transmitted from each of the corresponding ones of the plurality of processors so as to generate a plurality of loop back signals. A plurality of signal transmission paths are configured to carry a corresponding one of the plurality of signals from one of the plurality of processors to another of the plurality of processors, and a plurality of comparators compare the plurality of loop back signals to the plurality of transmission signals so as to enable the validity of each of the plurality of signals to be assessed.
    Type: Grant
    Filed: October 24, 2007
    Date of Patent: October 11, 2011
    Inventors: David C. Rasmussen, John G. Gabler
  • Patent number: 8028210
    Abstract: An object of the present invention is to provide a semiconductor device capable of recognizing circuit malfunction in an actual operation and of specifying a point of the circuit malfunction, and the semiconductor device, which does not induce the malfunction in the circuit of a subsequent stage when restoring the malfunction. The present invention is the semiconductor device provided with a plurality of logic circuits and a plurality of judging circuits for judging malfunction based on data from the logic circuits, wherein each of the judging circuits is provided with a first register, delay unit, a second register, a comparator and scanning unit, which makes the second register a shift register to allow to transmit an error signal held in the second register to the subsequent stage, while allowing the comparator to hold a comparison result.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: September 27, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Masanori Kurimoto