Abstract: A testing method includes selecting a low-pass filter by simulation, generating testing signals with the low-pass filter receiving output signals of an under-test circuit, and outputting the testing signals to an input of the under-test circuit for predetermined measurements. A testing circuit and testing method achieve the same jitter injection as conventional high-speed testing instruments, but save testing cost.

Abstract: A signature circuit in a semiconductor chip includes a signature program circuit configured to be programmed with signature information and to output a signature signal in response to the signature information; a signature output circuit configured to block the signature signal output by the signature program circuit during operation in a normal mode, and configured to pass the signature signal during operation in a test mode; and a pad-driving transistor directly coupled to the pad, configured to drive the pad during operation in the normal mode in response to an operation command, and configured to drive the pad during operation in the test mode in response to the signature signal output by the signature output circuit. The signature circuit outputs the signature information through a transistor for adjusting impedance to reduce a chip size by omitting an additional logic circuit for the signature circuit.

Abstract: A system for phase tracking and equalization across a byte group for asymmetric control of high-speed bidirectional signaling includes a slave device and a master device that is coupled to the slave device via a plurality of bidirectional data paths. The master device may adaptively modify transmit characteristics based upon data eye information sent via one or more unidirectional data paths by the slave device. The data eye information may correspond to an edge position of data signal transitions received by the slave device on each data path of the plurality of bidirectional data paths. In addition, the master device may modify data path equalization coefficients within the master device for a grouping of the bidirectional data paths such as a byte group, for example, dependent upon the data eye information.

Abstract: A data transmission apparatus comprises an estimation device to estimate a transmission condition of the transmission channel in the transmitter based on at least Jitter information or a packet loss rate obtained from the receiver, and a controller to change at least one of a bit rate of transmission data and a error resilience level according to the estimated transmission condition.

Abstract: A data transmission apparatus comprises an estimation device to estimate a transmission condition of the transmission channel in the transmitter based on at least Jitter information or a packet loss rate obtained from the receiver, and a controller to change at least one of a bit rate of transmission data and a error resilience level according to the estimated transmission condition.

Abstract: A data transmission apparatus comprises an estimation device to estimate a transmission condition of the transmission channel in the transmitter based on at least Jitter information or a packet loss rate obtained from the receiver, and a controller to change at least one of a bit rate of transmission data and a error resilience level according to the estimated transmission condition.

Abstract: A method and apparatus are disclosed for generating a second clock signal, having a second effective clock frequency, from a first clock signal, having a first effective clock frequency. Clock pulses of the first clock signal are counted to generate a count value. When the count value reaches a predetermined blanking value, a blanking signal is generated. The blanking signal blanks at least one clock pulse of the first clock signal. The process is repeated multiple times at a predetermined rate corresponding to the predetermined blanking value to generate the second clock signal.

Abstract: An amplifier (1) adapted to receive an input signal and to generate an output signal at an amplifier output (7) according to the input signal, the amplifier (1) comprising: a feedback circuit arranged to provide a feedback signal indicative of the output signal; an error signal generating circuit (12, 44) arranged to receive the feedback signal and generate a digital error signal according to the feedback signal; and an output signal generating circuit arranged to generate the output signal and to receive the digital error signal and to adjust the output signal according to the digital error signal; the amplifier (1) further comprising: a fault detection circuit (50) arranged to receive the digital error signal and to determine the presence or absence of a fault condition at the amplifier output (7) according to the digital error signal and to provide a signal (54) indicative of the presence or absence of the fault condition.

Abstract: An analog base-band (ABB) chipset of a mobile communication system comprises a memory configured to store a test pattern, a test control unit configured to generate a control signal during a test mode, an ABB unit configured to perform a test operation by receiving the test pattern from the memory in response to the test control signal and to output data of the test pattern to the memory in response to the test control signal, and a path selection circuit configured to form a flow path of the test pattern in the ABB unit in response to the test control signal.

Abstract: An apparatus, system, and method are provided for facilitating port testing of a multi-port host adapter. The present invention includes a scheduler that schedules execution of a plurality of threads to test a first port and a plurality of threads to test a second port of a multi-port adapter. The port test routine is divided into threads such that execution time and switching overhead is minimized. A multithreading module provides multithreaded execution of the plurality of threads such that the port test of the first port and the port test of the second port are performed in parallel. The apparatus further includes a communication module that takes the first port and the second port off-line. A third port remains on-line for Input/Output (I/O) communications that are multithreaded with the plurality of threads involving the first port and the second port.

Abstract: A test system for testing a backplane comprising an adapter assembly and a generic boundary-scan test unit. The adapter assembly includes an application-specific mating connector to communicatively couple the adapter assembly to an application-specific port of a backplane and an adapter generic connector. The generic boundary-scan test unit includes a test card generic connector to communicatively couple the generic boundary-scan test unit to the adapter generic connector of the adapter assembly and boundary-scan functionality to transmit at least one output test signal. The backplane is tested by communicating the output test signal from the generic boundary-scan test unit to the application-specific mating connector for testing the backplane and communicating at least one input test signal received from the backplane via the application-specific mating connector to the boundary-scan functionality of the generic boundary-scan test unit.

Abstract: A Multiple Input Shift Register (MISR) is used to generate signatures, based on data from a device under test, in order to validate the proper sequence and content of the data over a defined period of time. The MISR described herein includes the ability to “tag” the signatures for each time period using an incrementing value, and make that tag and the signature readable by a test controller. The MISR has the flexibility to be reset to a known initial state (or otherwise load a seed value) at the beginning of each time period or to continue accumulating signatures without being reset (or using the seed value). Accumulation of signatures over an extended period of time allows a test controller to validate that no errors occurred during a long term test without having to closely monitor the intermediate results.

Abstract: Memory apparatus and methods selectively map first lanes to second lanes. A memory agent may transfer training and return sequences using different lane mappings. The return sequences may be analyzed to identify failed lanes. Other embodiments are described and claimed.

Abstract: A serial point to point link that communicatively couples an integrated circuit (IC) device to another IC device is initialized by transferring a training sequence of symbols over the link. Registers of the IC device are programmed, to set a symbol data pattern and configure a lane transmitter for the link. A start bit in a register of the IC device is programmed, to request that the link be placed in a measurement mode. In this mode, the IC device instructs the other IC device to enter a loopback mode for the link. The IC device transmits a sequence of test symbols over the link and evaluates a loopback version of the sequence for errors. The sequence of test symbols have a data pattern, and are transmitted, as configured by the registers. Other embodiments are also described and claimed.

Abstract: A data transmission apparatus comprises an estimation device to estimate a transmission condition of the transmission channel in the transmitter based on at least Jitter information or a packet loss rate obtained from the receiver, and a controller to change at least one of a bit rate of transmission data and a error resilience level according to the estimated transmission condition.

Abstract: Application Specific Integrated Circuit (“ASIC”) devices, such as Field Programmable Gate Arrays (“FPGAs”), may be interconnected using serial I/O connections, such as high speed multi-gigabit serial transceiver (“MGT”) connections. For example, serial I/O connections may be employed to interconnect a pair of ASICs to create a high bandwidth, low signal count connection, and in a manner so that any given pair of multiple ASIC devices on a single circuit card may communicate with each other through no more than one serial data communication link connection step. A reconfigurable hardware architecture (“RHA”) may be configured to include a communications infrastructure that uses a high-bandwidth packet router to establish standard communications protocols between multiple interfaces and/or multiple devices that may be present on a single circuit card. Additionally, a communications infrastructure may be established across multiple circuit cards.

Abstract: A latch is provided for rapidly stabilizing a latching operation. The latch comprises a first latch circuit for latching a first signal in response to a first portion of a second signal to generate a first latch signal, and a latch error compensator for compensating a latch error in the first latch signal generated by the first latch circuit to generate a compensated latch signal.

Abstract: A self-synchronising data bus analyser comprising a generator LFSR, a receiver LFSR and a comparator wherein the generator LFSR generates a first data set which is transmitted through a data bus to the comparator; and wherein the comparator compares the first data set with a second data set generated by the receiver LFSR and adjusts the receiver LFSR until the second data set is substantially the same as the first data set.

Abstract: A circuit includes a universal serial bus physical layer interface (USB PHY), programmable storage elements in communication with control inputs of the USB PHY, and a processor to set the programmable storage elements. The processor initiates the loopback mode of the USB PHY by sending the appropriate control signal sequence to the programmable storage elements. The processor may also enable the generation of hardware generated or programmed test data.

Abstract: A programmable bit error rate monitor includes an error counter, a monitoring period counter with a programmable upper bound to set the monitoring period, and an error flag generator that compares the actual error count to a programmable threshold. The error flag generator may generate flags at different sensitivity levels, and the user may programmably select one of those flags. The three flags can be generated by independent comparators, or they can be extrapolated from the base error flag—e.g., by comparing only certain bits of the error count to corresponding bits of the threshold.

Abstract: A multi-device system having a daisy chain system bus structure and related method of operation are disclosed. A reference signal having a defined oscillation period is communicated around the daisy chain bus structure. Total signal transmission time around the daisy chain bus structure as well as signal transmission time to each one of a plurality of client devices connected to a host device by the daisy chain bus structure may be readily determined.

Abstract: Provided is a CAN system that can generate an error signal without requiring hardware for generating an error signal to be connected to a bus. A protocol processing part within a CAN controller incorporates error data into receive data or send data, based on error data information stored in a register.

Abstract: A loopback test to test a communication link for a layered interface where in a master agent programs the electrical parameters for the slave agent, such as, the offset, timing, and current compensation with a loopback control register. The slave and master agent to support an entry into the loopback test based on detection of a header within a packet. The slave and master agent to support exit out of the loopback test based on whether the loop count is finite.

Abstract: An integrated circuit device having a test sequence generator, first and second transceivers and a test sequence analyzer. The test sequence generator generates a test data sequence in response to a test mode selection. The first transceiver receives the test data sequence from the test sequence generator and is configured in a loopback mode to transmit and receive the test data sequence. The second transceiver receives the test data sequence received by the first transceiver and is configured in a loopback mode to transmit and receive the test data sequence. The test sequence analyzer determines whether the test data sequence received by the second transceiver matches the test data sequence generated by the test sequence generator.

Abstract: A system and method for economically yet thoroughly testing serial ports of electronic devices includes a receiver and a transmitter. The receiver is coupled to a TX line of a device under test for receiving an input serial bit stream from the device under test. The transmitter is coupled to a RX line of the device under test for providing an output serial bit stream to the device under test. The receiver is coupled to the transmitter for establishing a loopback connection. A time distortion circuit is interposed between the receiver and the transmitter, for adding predetermined amounts of timing distortion to the output serial bit stream. In addition, a selector is interposed between the receiver and the transmitter, for selecting between the receiver and a direct input. The direct input provides an algorithmic test signal that differs from the input serial bit stream received by the receiver.

Abstract: A system to test integrated circuits on a wafer may include a transceiver formed on the wafer. The system may also include an antenna system couplable to the transceiver. The transceiver may be formed in one of a scribe line on the wafer, a chip on the wafer or on an otherwise unusable portion of the wafer. The antenna system maybe formed in at least one of the same scribe line as the transceiver or in at least one other scribe line formed in the wafer. Alternatively, the antenna system may include an antenna external to the wafer.

Abstract: A macro block MB2 including a physical-layer circuit PHY for communications performs transmission and reception processing to and from a macro block MB1 at a clock frequency CF1. A test circuit TC includes a test transmission buffer TXB that stores a transmission data signal from a test input terminal TPI at a frequency CF2 that is lower than the frequency CF1, and a test reception buffer RXB that outputs a reception data signal to a test output terminal TPO at a frequency CF3 that is lower than the frequency CF1. After the transmission buffer TXB has stored the transmission data signal from the terminal TPI at the frequency CF2, it outputs the stored transmission data signal to the MB2 at the frequency CF1. After the reception buffer RXB has stored the reception data signal from the MB2 at the frequency CF1, it outputs the stored reception data signal to the terminal TPO at the frequency CF3.

Abstract: A data transmission apparatus comprises an estimation device to estimate a transmission condition of the transmission channel in the transmitter based on at least Jitter information or a packet loss rate obtained from the receiver, and a controller to change at least one of a bit rate of transmission data and a error resilience level according to the estimated transmission condition.

Abstract: A disk drive is disclosed for connecting to a host, the host comprising loopback circuitry operable to loop a pattern received from the disk drive back to the disk drive. The disk drive comprises interface circuitry including a transmitter driver operable to transmit transmission signals at a transmission amplitude, and a receiver driver operable to receive reception signals. The transmitter driver is configured to transmit at an initial transmission amplitude, and a calibration pattern is transmitted to the host through the transmitter driver. The reception signals received by the receiver driver are monitored to detect a loopback pattern representing a loopback of the calibration pattern. The loopback pattern is processed to detect an error, and the transmission amplitude is adjusted in response to the error.

Abstract: A built-in self-test circuit for use in testing a serializer/deserializer circuit includes a programmable transmit register that transmits data to the serializer/deserializer circuit having programmably varying characteristics. The built-in self-test circuit includes the transmit register that transmits data to the serializer/deserializer for processing into processed data, a receive register that receives the processed data from the serializer/deserializer, and an error detector that detects errors in the processed data.

Abstract: Communications equipment can be tested using a test pattern that is modified compared to, and more exploitive than, a standard test pattern. Test patterns can be employed that have lengthened or shortened consecutive identical digit (CID) portions, or that have lengthened or shortened pseudo random bit sequence (PRBS) portions. In some cases, PRBS polynomials are not re-seeded after each CID. Further, different order polynomials can be employed for different applications. Exemplary applications can include test equipment and built-in self-test capability for integrated circuits.

Abstract: The present invention provides a fast testing system and method for optical transceiver, which integrates multiple testing machines in the testing environment for the optical transceiver, so that the user can employ the testing system for optical transceiver for rapid and simultaneous measurement of multiple products, and further improving the production efficiency. Moreover, with a combination of optical channel selector with a set of digital communication analyzer and spectrum analyzer, a plurality of products to be tested can be switched for parametric inspection, and by combining a tree coupler to synchronously transmit the measurement signals of the standard sample to the product to be tested in a multi-port transmission to further measure the bit error ratio. Thus, the product analysis report for the user is in real-time, so as to effectively improve the competitiveness of the industry.

Abstract: A semiconductor integrated circuit includes a first delay circuit generating a first delay clock; a second delay circuit generating a second delay clock; a first register registering a value of a first delay of the first delay clock; a second register registering a value of a second delay of the second delay clock; a clock supplying circuit supplying a clock signal to the first and second delay circuits; a phase comparator detecting a phase difference between the first and second delay clocks; and a built-in test circuit configured to control the first and second registers so that the value of the first delay can be registered in the first register and the value of the second delay can be registered in the second register.

Abstract: An bit error rate tester for use in connection with a high speed networks. The bit error rate tester includes transmit and receive ports, as well as a sequence generator, memory, synchronizer, sequence start detect module, and comparator. The sequence generator generates a bit sequence for transmission through a network path. The bit sequence returns to the bit error rate tester by way of the receive port. The synchronizer then bit-aligns the received bit sequence to compensate for idles/fill words added/dropped as the bit sequence transited the network. The synchronized bit sequence is passed to the start word detector which detects start and end words in the bit sequence and instructs the comparator to compare only data between the start and end words. The comparator compares the received bit sequence with a copy of the transmitted bit sequence regenerated from the memory, and calculates a bit error rate.

Abstract: A signal transmit-receive device of the invention reduces the number of high-speed signal lines required for connecting a transmitting circuit group and a receiving circuit group, and for running a loopback test on a signal transmit-receive device. The loopback test circuit uses an error detecting circuit, a test signal producing circuit, and a wiring for transmitting error information. The error detecting circuit compares a test signal pattern defined in advance by a first communication device and a received signal pattern. The test signal producing circuit produces the test signal pattern based on error information. If an error is detected, the error signal is transmitted to the test signal producing circuit through the wiring. The test signal producing circuit produces a predetermined test signal pattern if the error signal DE has an L level; upon receiving H level, it sends back the predetermined test signal pattern to the first communication device.

Abstract: An automated test system (20) for testing a high-speed communications integrated circuit (10), such as a serializer/deserializer, is disclosed. The system (20) is able to test the parameters of receiver jitter tolerance and receiver sensitivity in a loopback connection arrangement, in which serial output terminals (SERTX) of the integrated circuit (10) are connected to serial input terminals (SERRX) of the integrated circuit (10). An attenuator (26), which in the disclosed embodiment includes programmable attenuators (30P, 30N) and a fixed attenuator (32), one of which is selected, is disposed in the loopback path. A deterministic jitter injector (28) is also in the loopback path, and may be implemented by way of variable length trace blocks (35P, 35N) on the test board (30).

Abstract: A software self test engine is executed from a cache of a processor. The software self test engine is executed using an execution engine of the processor to perform a physical layer self test. The physical layer self test is performed by transmitting a test vector from the execution engine under control of the self test engine to an input/output (“I/O”) unit of the processor along a datapath coupling the execution engine to the I/O unit. The test vector is transmitted along a loop back path including the I/O unit and the datapath to test a hardware device along the loop back path.

Abstract: A testing circuit for testing a series of at least three alternating transmitter and receiver links. The testing circuit including a built-in-self-test (BIST.) macro for generating test data and transmitting the test data to a first link of the series of transmitter and receiver links, and for receiving processed test data from a last link of the series of transmitter receiver links; and at least one test transmission line for transmitting test data received by a link of the series of transmitter and receiver links to a next link of the series of transmitter and receiver links, wherein the at least one test transmission line connects the at least three transmitter and receiver links.

Abstract: A test system and method for testing a serializer/de-serializer system. The system includes a pair of serializer/de-serializers each having a serial data receive port and a serial data transmit port. The serializer/de-serializers are adapted to be placed in a loop-back mode in response to a loop-back signal to pass data fed to the serial data receive port to the serial data transmit port. A backplane connects the serial data transmit port of one serializer/de-serializer to the serial data receive port of a second one of the serializer/de-serializers. A tester passes data to the first serial data receive port and receives data from the data transmit port of the second one of the serializer/de-serializers with both serializer/de-serializes placed in the loop-back mode.

Abstract: A method for determining whether a physical layer device under test is defective may include establishing a closed communication path between a verified physical layer device and the physical layer device under test via an optical interface of the verified physical layer device and an optical interface of the physical layer device under test. Alternately, the electrical interface may also be used for testing. A packet generator may transmit test packets over the established closed communication path and at least a portion of the test packets from the physical layer device under test may be received by the verified physical layer device. Subsequently, the verified physical layer device may compare at least a portion of the received test packets with at least a portion of the generated test packets in order to determine whether the physical layer device is defective or operational.

Abstract: A flash memory erase check circuit is disclosed. One embodiment includes an on-chip circuit that quickly and reliably checks that the flash memory chip is actually erased even after data gain that has resulted, for example, from a long period of storage.

Abstract: A method and system are disclosed for providing standalone built-in self-testing of a transceiver chip. The transceiver chip includes packet generators for generating test packets and packet checkers for comparing received packets with expected packets. The transceiver chip may be configured for testing through at least two wraparound test paths—a first test path that includes an elastic FIFO of a transmit path of the transceiver chip, and a second test path that includes an elastic FIFO of a receive path of the transceiver chip. During testing, the test packets are generated by packet generators within the transceiver chip and routed through the at least two wraparound test paths to packet checkers within the same transceiver chip. The packet checkers compare the returned packets to the expected packets. If the returned packets are inconsistent with the expected packets, the transceiver chip is defective.

Abstract: A test packet generator (225a) within a physical layer device (230) may generate test packets to be communicated over a closed communication path established within the physical layer device (230). The test packets may include a pseudo-random bit sequence. A receiver within the physical layer device (230) may receive at least a portion of the generated test packet. A test packet checker (225b) within the physical layer device may compare at least a portion of the received test packets with at least a portion of the generated test packets in order to determine the bit error rate for the physical layer device. A window counter (225c) within the physical layer device (230) may count at least a portion of a number of bits received within the generated test packets and a number of bits that are in error in at least a portion of the number of bits received.

Abstract: A high speed, two-way serial interface with a scrambler and de-scrambler may be tested by sending a single word repeatedly through the scrambler to create a pseudo-random sequence. The pseudo-random sequence is then passed through the transmitter and looped back through the receiver of the serial interface. The pseudo-random sequence is then descrambled and compared to the input word. Since the input sequence is only a single word rather than a series of words, the comparison is very simple and capable of being performed within the serial interface itself without the need for external test equipment.

Abstract: Techniques for performing a continuity check operation include sending a pattern of bits over a packet network connection through a first interface on a packet network to a second interface on the packet network. The first interface is monitored for return of the pattern of bits over the packet network connection. A decision whether the continuity check is successful is based on whether the pattern of bits is detected at the first interface during the monitoring. The techniques can be used for both narrowband as well as broadband calls over the packet network.

Abstract: A method and mechanism for testing communication links. A transmitter contact, or transmission point, is assigned a unique identifier. During a given test, the transmitter conveys a test pattern to a receiver via a link. Following this test pattern, the transmitter transmits a bit of its unique identifier to the receiver. The receiver receives both the test pattern and the identifier bit, and determines whether the received test pattern matches an expected value. If the test pattern was correctly received by the receiver, the receiver transmits the received identifier bit back to the transmitter. However, if the received test pattern is not correct, the receiver complements the received identifier bit and transmits the complemented bit back to the transmitter. The transmitter receives the identifier bit from the receiver and determines whether it matches the identifier bit which was originally transmitted by the transmitter.

Abstract: The present invention provides system and method of identifying a failure location in any datapath in a set of datapaths in a communication element, each datapath of the set of datapaths traversing from an ingress point through at least a first component to an egress point. In an embodiment, the method comprises: providing a diagnostic cell adapted to be inserted at a starting point upstream of the first component in the any datapath; providing at least a first diagnostic cell counter module adapted to be associated with a first location in the first component, the first diagnostic cell counter module adapted to recognize when the diagnostic cell passes the first location and adapted to track passage of the diagnostic cell past the first location; inserting the diagnostic cell into the any datapath at the starting point; and analyzing the diagnostic cell counter module to identify the failure location in the any datapath.

Abstract: Arrangements (circuits, methods, systems) having self-measurement of input/output (I/O) specifications (e.g., input trip-point, output drive-level and pin leakage).

Abstract: The present invention is a bit error rate tester that may operate on network paths having devices that add or drop idles within a transmitted bit sequence. In particular, the bit sequence determines whether a received bit sequence is synchronized. If the received sequence is not synchronized or if a certain event/threshold is reached, then the bit error rate tester re-synchronizes the sequence prior to analysis. Also, the bit error rate detector is able to operate on high-speed networks and provide bit granularity measurements.

Abstract: The present invention provides a method and apparatus to determine the state of a communications link between two nodes in a network. Typically, each node will have an RTT-based value to use, a packets sent counter, and a threshold number to use against the packet sent counter to determine if there is a problem with their communications link. Using the RTT value makes the failure detection sensitive to the actual state of the communications link at any particular time; it also allows the failure detection algorithm to take into account the bursty nature of nodes in a packetized network connection. For each packet received from a non-local node, the local node sets the counter to 0 and starts a new RTT-based time interval. The local node then increments the counter only once, regardless of how many packets it sends to the non-local node, during the RTT-based time interval. Once the time interval is up, the counter is incremented for each packet sent.