Abstract: A method of testing an electronic device including first and second semiconductor devices connected to each other with a plurality of bus lines. First, the first semiconductor device supplies a selected one of the bus lines with a first logical output signal. Then, the second semiconductor device acquires a first bus line signal from the selected bus line. The second semiconductor device inverts the first bus line signal to generate a second logical output signal. The second semiconductor device transmits the second logical output signal to the first semiconductor device. The first semiconductor device receives a second bus line signal from the selected bus line. The first semiconductor device compares the first logical output signal and the second bus line signal to detect a connection between the first semiconductor device and the second semiconductor device.

Abstract: A system and method for economically yet thoroughly testing serial ports of electronic devices includes a receiver and a transmitter. The receiver is coupled to a TX line of a device under test for receiving an input serial bit stream from the device under test. The transmitter is coupled to a RX line of the device under test for providing an output serial bit stream to the device under test. The receiver is coupled to the transmitter for establishing a loopback connection. A time distortion circuit is interposed between the receiver and the transmitter, for adding predetermined amounts of timing distortion to the output serial bit stream. In addition, a selector is interposed between the receiver and the transmitter, for selecting between the receiver and a direct input. The direct input provides an algorithmic test signal that differs from the input serial bit stream received by the receiver.

Abstract: The present invention is an apparatus for multi-level loopback test in a community network system and method therefor, in which a loopback test device is installed between an Ethernet switch in a community and a central office so that the loopback test device can be utilized by network management system in central office to perform a three-level loopback test on the community network system to easily obtain the information of whether there is a fault between central office and loopback test device, whether the connection of Ethernet switch is good, and whether loopback test device operates normally.

Abstract: A method for testing the upstream channel of a cable modem system, using a tester, which generates and transmits a known test pattern to the Cable Modem Termination System (CMTS). If there are errors in the packet resulting from the upstream channel, the CMTS discards the packet based on standard Internet Protocol. If there are no errors the packet is returned on the downstream channel to the tester. The tester counts all returned test packets received including test packets with errors resulting in the downstream. Packets with errors are not discarded, but are checked for a portion of the repeating test pattern and checked for the correct number of bits of a test packet. All packets determined to be test packets, including those with errors, are counted over a period of time and compared to the number of packets originally sent.

Abstract: A method and apparatus for testing the transmitter and receiver links of an I/O node. A test mode in an I/O node is initiated by a test signal driven from a test system to the I/O node via a loadboard. The I/O node may then receive test data through a peripheral bus interface. The inputting may be performed synchronously to a first clock signal. The I/O node may then transmit the test data to a receiver via a loopback mechanism on the loadboard. The transmission and reception of test data between transmitter and receiver is synchronous to a second clock signal, which has a frequency equal to the operational frequency of the transmitter and receiver. The receiver may forward the test data to the peripheral bus interface, which may in turn output the test data to the test system. The test system may then determine the results of the test.

Abstract: An analogue/digital interface circuit is disclosed in which an integral bistable circuit has its state changed by the arrival of an incoming analogue signal, however transient, and irrespective of when it arrives relative to the clock signal driving the digital circuit. The use of a bistable (flip-flop) circuit enables each parth of the interface circuit to be traversed when scan test signals are applied to it. Concurrently with the application of such signals, an inhibition signal is applied to the analogue signal inlet to prevent the arrival of any subsequency analogue signals from changing the state of the signal-storage element.

Abstract: A data transmission apparatus comprises an estimation device to estimate a transmission condition of the transmission channel in the transmitter based on at least Jitter information or a packet loss rate obtained from the receiver, and a controller to change at least one of a bit rate of transmission data and a error resilience level according to the estimated transmission condition.

Abstract: A method for establishing communication in an ADSL subscriber loop, the method comprising the steps of determining that showtime cannot be entered during initialization of communication between the modems; requesting entry into a diagnostic mode by one of the modems upon the determining; diagnosing line conditions as being unable to support communication at a predetermined standard; and establishing communication at a standard lower than the predetermined standard.

Abstract: A clock data recovery system is provided for resampling a clock signal according to an incoming data signal stream. It comprises a clock generator for generating said clock signal wherein one of the frequency and phase of that clock signal is dependent upon a control signal. It is further provided a phase detector operable to detect the phase difference between said clock signal and said incoming data signal stream and is operable to generate a phase difference signal. A loop controller has a variable-gain and is operable to control said clock generator by generating said control signal. That control signal is dependent in said phase difference signal and that variable-gain. The variable-gain is dependent upon a transition rate of the incoming data signal stream. The loop controller can comprise a low-pass filter to generate from the phase difference signal a low-pass filered phase signal and to adjust the bandwidth of the clock data recovery system.

Abstract: A device apparatus and method are detailed that allow for improved bit error rate (BER) testing, configuration, and operation of a communication device and associated physical communication link, in particular on a HDSL communication device and link. The improved communication device apparatus and method additionally allow for the communication device to utilize an embedded BER tester (BERT) to run commonly utilized BER tests on high speed communication channels (downstream and upstream) associated with the communication device. The device apparatus and method also allow for a BER test to be configured and initiated remotely, with loopback at a remote device and masking of alarm states at the remote device or local device until the BER test is complete.

Abstract: A method for self-testing of an electronic system that includes a main module and subsidiary modules, which are connected to the main module by data lines, at least some of which may be idle. One of the idle lines is selected to serve as an aid line, and the subsidiary module to which the aid line is connected is instructed to loop back traffic reaching the subsidiary module via the aid line. Another idle line is selected for testing, and a switch in the main module is configured to link the aid line and the line under test. The subsidiary module to which the line under test is connected transmits test traffic over the idle line to the main module. If the test traffic does not return to the subsidiary module within a predetermined period of time, a failure is reported.

Abstract: A system and method for conducting diagnostic tests on a network card disposed in a telecommunications node. A diagnostic application automaton is launched at predetermined intervals by a base level diagnostics automata under the control of an executive scheduler running on the network card, wherein the network card is initially in a provisioned configuration mode operable to transmit and receive communication traffic therethrough. Upon determining by the base level diagnostics automata to install the diagnostic application, the network card is reconfigured into a loopback configuration mode involving a predefined loopback path in the telecommunications node. Operations relating to the telecommunications traffic are suspended in the loopback mode, whereby one or more diagnostic tests may be performed by the installed diagnostic application by injecting appropriate test patterns at specific locations in the path.

Abstract: In ATM networks, digital data in ATM cells are sent to a destination node over more than one transmission link in round robin fashion. This is called inverse multiplexing. At connection start-up, the source node informs the destination node of the specific round robin fashion of the transmission links so that the ATM cells are reassembled in a proper sequential order. Inverse multiplexing control cells are used to communicate between the source node and destination node for connectivity testing of transmission links. Cell stuffing is also provided in one embodiment to accommodate non-synchronized links among transmission links. In a particular embodiment, two consecutive control cells indicate a stuffing cell. A start-up procedure is described when not all the transmission links are usable.

Abstract: A system is provided for testing a physical layer device, or various network portions connected to that physical layer device. The test system includes a random bit generator that, during use, produces a random pattern of bits clocked in parallel onto the transmit portion of the physical device. The parallel-fed information can then be serialized and selectably fed back to the receive input of the same physical device. The receive portion of the physical device can then deserialize the random pattern of bits, and present those bits to logic within the test system. The test system can, therefore, compare each of the random pattern of bits presented to the physical device with corresponding bits derived from the deserializer. If each bit within the random pattern of m bits forwarded to the serializer does not compare with each corresponding m bits forwarded from the deserializer, then the physical device is known to be a failure.

Abstract: An in-band communication scheme reports the results of loop performance measurements from a remote site to a test site, by deliberately injecting, into a loopback sequence of a repeated code word, a selected one of different numbers of errors. The number of errors is selectable from among a plurality of different quantification values, based upon in which of a plurality of respective ranges of loop performance parameters, measured parameter values fall. The error data is thus effectively a gray-scale type of quantification of loop performance measurement data.

Abstract: A connection integrity monitor is provided wherein, for large switch fabrics (connection circuits), gate usage and power requirements are reduced by a value approaching 50% when compared to a previously disclosed connection integrity monitor. Rather than simultaneously monitoring the connectivity of all outputs of the switch fabric, thus completely duplicating the switch fabric, the connection integrity monitor monitors only one connection at a time. Therefore, redundancy is reduced from M to 1. The connection integrity monitor can be provisioned statically to monitor any one of the output connections or arranged so that all connections can be monitored, although not simultaneously.

Abstract: A data transfer method includes a connection establishment step of detecting connection with a remote device and setting parameters for data transfer, and a transfer execution step of starting data transfer after completion of the connection establishment step and continuing data transfer until a transfer error is recognized to have occurred. In the transfer execution step, the frequency of errors in received data is monitored and, when the frequency reaches a predetermined value, a transfer error is recognized to have occurred.

Abstract: A system and method for performing non-intrusive loopback testing in a communication device. When a loopback mode of testing is requested for the communication device (e.g., from a diagnostic application), and one or more communication streams are active or bound to the device, the streams are suspended instead of terminated. In a list of the active streams, maintained in the device's information data structure, a device driver or the application modifies each of the streams (e.g., by setting a flag). While a stream is suspended, any traffic for the stream is dropped. After the loopback testing is completed, the streams are reactivated.

Abstract: A method and apparatus for determining a communication device's loopback capabilities by querying a device driver of the device. The device's loopback capabilities identify locations (e.g., internal modules, protocol layers) in the device, and/or data rates, at which loopback testing may be performed. Instead of embedding those capabilities in a diagnostic application and modifying the application every time a device changes or is upgraded, the application queries the device driver. The device driver sends the application a data structure or message identifying the capabilities, including identifiers. The application specifies a loopback capability to be exercised by returning a corresponding identifier to the driver.

Abstract: The present invention relates to a node connection test method and a recording medium by which a test can be carried out in a system having a plurality of nodes (network connecting devices such as personal computers and workstations) connected to a network such as a LAN (Local Area Network) or WAN (Wide Area Network). A testing program used in the method of the present invention includes two independent programs, a transmission program and a reception program. A loopback test is performed between the transmission program and the reception program, thereby confirming normality of the network.

Abstract: A method for locating a failure of a communication line according to self-adjusted priorities of the test points in the order of high failure probability in a communication line management system, includes the steps of organizing the test points, information on the test history of the test points, and test point search priorities (TSPs) representing the priorities of the test points in the order of high failure probability into a test database, searching the test database to determine the testing order of the test points according to the TSPs, testing the test points in the testing order to locate the failure, and revising the values of the data fields of the TSPs according to the test results and the location of the failure.

Abstract: A method and system are disclosed for providing standalone built-in self-testing of a transceiver chip. The transceiver chip includes packet generators for generating test packets and packet checkers for comparing received packets with expected packets. The transceiver chip may be configured for testing through at least two wraparound test paths—a first test path that includes an elastic FIFO of a transmit path of the transceiver chip, and a second test path that includes an elastic FIFO of a receive path of the transceiver chip. During testing, the test packets are generated by packet generators within the transceiver chip and routed through the at least two wraparound test paths to packet checkers within the same transceiver chip. The packet checkers compare the returned packets to the expected packets. If the returned packets are inconsistent with the expected packets, the transceiver chip is defective.

Abstract: A method for self-testing of an electronic system that includes a main module and subsidiary modules, which are connected to the main module by data lines, at least some of which may be idle. One of the idle lines is selected to serve as an aid line, and the subsidiary module to which the aid line is connected is instructed to loop back traffic reaching the subsidiary module via the aid line. Another idle line is selected for testing, and a switch in the main module is configured to link the aid line and the line under test. The subsidiary module to which the line under test is connected transmits test traffic over the idle line to the main module. If the test traffic does not return to the subsidiary module within a predetermined period of time, a failure is reported.

Abstract: A bit error rate test (BERT) system is configured as a field programmable gate array that emulates multiple independent BERT generators. The BERT generators produce test frames containing test pattern codes associated with respectively different time division multiplexed (TDM) digital communication channels, that are not necessarily mutually contiguous within a plurality of TDM timeslots of a network communication frame serving digital communication circuits. A framing unit assembles the test code patterns into a test frame and transmits the test frame over a serial network interface to a plurality of digital channel units of a channel bank. The framing unit also interfaces contents of test code patterns within test frames returned from the channel units over the serial network interface with a plurality of data channel-specific virtual BERT receivers, associated with respective digital communication channels.

Abstract: A device apparatus and method are detailed that allow for improved bit error rate (BER) testing, configuration, and operation of a communication device and associated physical communication link, in particular on a HDSL communication device and link. The improved communication device apparatus and method additionally allow for the communication device to utilize an embedded BER tester (BERT) to run commonly utilized BER tests on high speed communication channels (downstream and upstream) associated with the communication device. The device apparatus and method also allow for a BER test to be configured and initiated remotely, with loopback at a remote device and masking of alarm states at the remote device or local device until the BER test is complete.

Abstract: The present invention provides system and method of identifying a failure location in any datapath in a set of datapaths in a communication element, each datapath of the set of datapaths traversing from an ingress point through at least a first component to an egress point. In an embodiment, the method comprises: providing a diagnostic cell to adapted to be inserted at a starting point upstream of the first component in the any datapath; providing at least a first diagnostic cell counter module adapted to be associated with a first location in the first component, the first diagnostic cell counter module adapted to recognize when the diagnostic cell passes the first location and adapted to track passage of the diagnostic cell past the first location; inserting the diagnostic cell into the any datapath at the starting point; and analyzing the diagnostic cell counter module to identify the failure location in the any datapath.

Abstract: An in-band communication scheme reports the results of loop performance measurements from a remote site to a test site, by deliberately injecting, into a loopback sequence of a repeated code word, a selected one of different numbers of errors. The number of errors is selectable from among a plurality of different quantification values, based upon in which of a plurality of respective ranges of loop performance parameters, measured parameter values fall. The error data is thus effectively a gray-scale type of quantification of loop performance measurement data.

Abstract: A flash memory erase check circuit is disclosed. One embodiment includes an on-chip circuit that quickly and reliably checks that the flash memory chip is actually erased even after data gain that has resulted, for example, from a long period of storage.

Abstract: A system and method of detecting/eliminating a faulty port in a fiber channel-arbitrated loop, which implements early location/elimination of a port which causes a faulty on a loop in an FC-AL. If no faulty is found in loop 7 at step 914, it can be determined that its own port normally works. Then, an enable instruction is issued to a node destined to a port on the loop 7 from loop 8 at step 915. If a fault is detected in the loop 7 at step 916, it can be determined that the port which has issued the enable instruction at step 915 has been issued faulty. The port which has issued the enable instruction at step 915 is registered as a faulty port at step 918. A bypass instruction is issued from the loop 8 at step 919.

Abstract: A method and system for reporting the status of a digital transmission line element, such as a regenerative repeater or a network interface unit, to a remote location. The line element is interconnected to a digital transmission line and receives a data stream via the transmission line from the remote location. The data stream follows predetermined coding rules. In a loopback mode, the line element loops back the data stream via the transmission line to the sending end. The line element includes a detector and an error generator. The detector senses a status query signal in the data stream and responsively enables the error generator to then selectively introduce error message into the data stream being looped back along the transmission line. The error message may then be detected at a remote location to a provide information regarding the line element, such as its location or operating mode.

Abstract: First data (“00”, “01”, “10”, “11”) corresponding to threshold voltages of four values (1 V, 2 V, 3 V, 4 V) are stored in the individual memory cells of an EEPROM. Upon reading, a decoder circuit assigns bits so that neighboring first data have only one different bit in their two-bit architectures, thus converting the first data into second data (“00”, “01”, “11”, and “10”), and outputting the second data as storage data of the memory cells. Even when multiple-valued storage data are lost from the EEPROM due to data errors arising from deterioration of memory cells which have inevitably occurred after repetitive uses, error detection and error correction can be efficiently and accurately done. Of course, the data to be stored is not limited to 2-bit data, but the present invention can also be applied to multiple-valued data of 3 bits or more.

Abstract: A method for determining failure modes of a transceiver (100) includes applying a control signal (121) to a transmitter (130) of transceiver (100). The power level of a transmit signal (131) is proportional to a predetermined voltage level of control signal (121), and is detected by a detector (132) which correspondingly produces a transmit power level indicator (133). A portion of transmit signal (131) is coupled to produce a coupled transmit signal (111) which is received by a receiver (110) of transceiver (100). Receiver (111) produces a receive signal strength indicator (112) corresponding to the power level of coupled transmit signal (111). Voltage levels of received signal strength indicator (112), transmit power level indicator (133) and predetermined voltage level of control signal (121) are stored in a memory means 125, and compared in a controller 126 to determine failure modes of receiver (110) and transmitter (130).

Abstract: A system and method for testing the most complex portions of transceiver devices integrated into digital VLSI chips. The testing is performed in a manufacturing environment with minimal external hardware and using a combination of test-specific circuitry and pattern algorithms built into a mixed signal transceiver implementing a test methodology suitable for application and measurement on a digital tester.

Abstract: In some call-switching systems, transmitted speech samples may be sent back (back-looping) to the sender from a telephone switching center if the switching center is unable to send the speech samples forward. When supplementary information is sent with the speech sample, back-looping may cause a problem if the sending device interprets the signal as originating from another device. To avoid this problem, transmitted samples are subjected to a check value calucation such as a checksum or a cyclic redundancy check. The check value is stored in memory and any received samples are subjected to a check value calculation and compared to the stored samples. If the comparison yields a match, then the device will know that the received samples originated from itself and can be properly handled.

Abstract: An improved system for allowing a digital transmission line element, such as a regenerative repeater or a network interface unit, to communicate with a remote location. The line element is interconnected to a digital transmission line, which receives an incoming data stream. The data stream follows predetermined coding rules. The line element includes a detector and an error generator. The detector senses when a status inquiry is made and responsively enables the error generator to then selectively introduce an error message into an outgoing data stream along the digital transmission line. The error message may then be detected at a remote location to a provide information regarding the line element, such as its location or operating mode.

Abstract: The functionality of a first processor is checked with a second processor. A data word with a specified number of data bits is supplied to the first processor from a second processor at specified time intervals. Each data bit is assigned a function. Having processed a function, the first processor inverts the associated data bit and, at the end of a time slice, passes the data word to the second processor, which checks the transferred data word.

Abstract: An improved diagnosis test apparatus and test method for a small computer system interface (SCSI) that are capable of controlling the input/output of SCSI test data and SCSI signal data which are generated by a host computer without using a peripheral SCSI device. The apparatus includes a host computer for inputting/outputting SCSI control data and SCSI test data, and a controller for receiving and temporarily storing the SCSI control data and SCSI test data from the host computer and for outputting the data to the host computer, for thus testing the SCSI.

Abstract: A communication-line-quality measuring system includes transmission and terminal equipment. Transmission equipment has a first frame assembling part transmitting a down-link multiplexed frame signal to a down-link line having a first frequency, and a first frame disassembling part disassembling an up-link multiplexed frame signal transmitted through an up-link line having a second frequency. Terminal equipment has a second frame disassembling part disassembling the down-link multiplexed frame signal, and a second frame assembling part transmitting the up-link multiplexed frame signal obtained by frame-multiplexing an output signal of the subscriber unit with a control signal, to the up-link line. A pattern generation part in the first frame assembling part provides a test signal to an available channel of signal frames in the down-link multiplexed frame signal.

Abstract: A computer system which includes data transmission line and a plurality of data transmissions apparatuses connected in parallel to the data transmission line. Each data transmission apparatus generates transmission data and provides the generated transmission data to the data transmission line. In each data transmission apparatus, the generated transmission data provided to the data transmission line is wrapped around back to the respective data transmission apparatus without passing through any other data transmission apparatus. Each data transmission apparatus includes a data abnormality monitoring unit which determines whether the generated transmission data correlates with the transmission data which was wrapped around. It is determined that an abnormality occurred when the data abnormality monitoring unit determines that the generated transmission data does not correlate with the transmission data which was wrapped around.

Abstract: An engineering order wire arrangement is provided for a synchronous telecommunications network comprising a plurality of nodes interconnected via transmission paths, each path accommodating a plurality of transmission channels. Engineering voice traffic is carried on a first overhead channel having a defined network route topology. A second overhead channel is used to define a model network having a a route topology identical to that of the first overhead channel. The model network is tested to determine its integrity, i.e. the absence of loops. If the model network is found to be defective, both networks are reconfigured.

Abstract: A fault recovery system of a ring network based on a synchronous transport module transmission system, having a fault data writing unit for writing, when an input fault is detected by a node, fault data in a predetermined user byte in an overhead of a frame flowing through both a working line and a protection line running in opposite directions to each other. By detecting the fault data in a supervision node or a node just before the fault position, the supervision node or the node just before the fault position executes a loopback operation.