Abstract: A hardware trace unit is integrated into a computer system that has a main memory. The trace unit includes registers that contain information defining a location in main memory, and has an input connection. This is used to eavesdrop on communications in the computer system, thereby obtaining information about the state and/or operation of the system. A trigger mechanism then compares the information received against one or more trigger conditions, such as whether a particular event has occurred. Responsive to the trigger conditions being satisfied, the trace unit generates an output record containing diagnostic information. This is sent for storage in the main memory of the computer at the location defined in the registers.

Abstract: An integrated semiconductor memory operates in synchronization with a clock signal in a normal operating state and is switched from the normal operating state to a test operating state by applying a combination of control signals. During a first test cycle, selection transistors for memory cells are turned on by asynchronously actuating the semiconductor memory using a state change in a control signal. In a second test cycle, the memory content of at least one of the previously activated memory cells is read by synchronously actuating the semiconductor memory using a second signal combination of control signals. By shifting the timing of a signal edge which prompts the state change in the first test cycle close to the time at which the second signal combination is applied in the second test cycle, it is possible to test short reading times which are within one period of the clock signal.

Abstract: A test circuit for testing a memory circuit has a data input line for providing test data and a comparator unit. The comparator unit is connected to the data input line and to the memory circuit for comparing the test data written into the memory circuit with the test data read from the memory area. The data input line is connected to the memory circuit via a data change circuit. The data change circuit is controllable depending on a result of a comparison in the comparator unit such that when an error occurs, subsequent test data can be written in an altered manner to the memory circuit.

Abstract: A system and method for testing the random access memory of a computer system is disclosed. A memory-testing engine is embedded in the utility bus controller of an application specific integrated circuit, which is coupled to a random access memory in need of testing. Upon receiving an initiation signal over a bus from the central processing unit, the memory-testing engine begins writing data to a targeted area of the memory, and then reading back the stored data and comparing the data to what was sent. Having the memory-testing engine distributed to the memory's being tested allows several memory devices to be tested simultaneously.

Abstract: A controller that receives an input of a status of an apparatus, executes predetermined arithmetic and logical operations, and outputs a control signal of the apparatus, and is equipped with a plurality of processors for executing the arithmetic and logical operations; a plurality of data storage elements for storing respective results of the arithmetic and logical operations of the plurality of the processors; a comparator for comparing the results of the arithmetic and logical operations of the plurality of the processors stored in the plurality of the data storage elements; and a comparison record storage element for storing a record of the comparison results of the comparator.

Abstract: Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data compression test mode. In the data compression test mode, reading one word of an output page provides an indication of the data values of the remaining words of the output page. The time necessary to read and verify a repeating test pattern can be reduced as only one word of each output page need be read to determine the ability of the memory device to accurately write and store data values. The memory devices include data compression circuits to compare data values for each bit location of each word of the output page. Output is selectively disabled if a bit location for one word of the output page has a data value differing from any remaining word of the output page.

Abstract: A method for testing an electronic module having a memory cell device includes writing an information item to the memory cell device at a first clock frequency and then reading-out the information item from the memory cell device at a second clock frequency. The read out information item is reflected at a reflection point and is written back to the memory cell device at the second clock frequency. The reflected information unit is then read-out from the memory cell device with the first clock frequency.

Abstract: Conventionally, when a burn-in test is performed by means of utilizing a memory BIST circuit, a control of a reset operation for the memory BIST circuit is required from an external source. According to the present invention, it is configured that the memory BIST circuit is used for the burn-in test of a memory macro, and a BIST reset control circuit detects a memory BIST test completion signal from the memory BIST circuit, and automatically resets the memory BIST circuit. Thereby, repetitive continuous tests to the memory macro by the memory BIST circuit can be achieved, and the burn-in test by means of utilizing the memory BIST circuit can be performed.

Abstract: Methods and systems are provided for transferring data and for pausing the transfer of data when certain conditions are met. In one embodiment, an error correcting code (ECC) encoder/decoder reads a codeword from a data storage device and decodes the codeword. The ECC encoder/decoder corrects any correctable errors in the codeword and outputs information regarding the condition of the codeword, such as the number of detected full errors and the number of erasures. The number of full errors is compared with a full error threshold value. When erasures are available, the number of erasures can be compared with an erasure threshold value. Both threshold values may be set at levels below the maximum levels at which errors can still be corrected. When either of the threshold values are exceeded, the transfer of data is paused and a processor is interrupted so that further action may be taken.

Abstract: The I/O compression test circuit performs test on global I/O lines divided into groups after failure occurs, thereby improving repair efficiency. The configuration of the test circuit is simplified by using a reset circuit, reducing the delay time, and thereby decreasing test time. Additionally, two strobe signals enable the I/O compression test circuit to perform a stable operation.

Abstract: An apparatus and a method are disclosed for reducing the pin driver count required for testing computer memory devices, specifically Rambus DRAM, while a die is on a semiconductor wafer. By reducing the pin count, more DRAMs can be tested at the same time, thereby reducing test cost and time. One preferred embodiment utilizes a trailing edge of a precharge clock to select a new active bank address, so that the address line required to select a new active address does not have to be accessed at the same time as the row lines.

Abstract: Method of testing the functionality of a memory which operates at a high operating clock frequency, the method specifically having the following steps, generation of test data, copying of the generated test data at the high operating clock frequency, comparison of the copied test data with the generated test data, generation of a functionality-indicating signal for indicating the functionality of the memory if the copied test data are identical to the generated test data.

Abstract: A semiconductor device has multilevel memory cells, each cell storing at least three levels of data each. The multilevel memory cells are arranged so as to correspond to a physical address space, each cell storing 2n levels of data each expressed by n (n?2) number of bits (X1, X2,. . . , Xn). A logical address is converted into a physical address of the physical address space. A judgement is made as to whether a logical address space including the logical address matches the physical address space. When matched, the most significant bit X1 is specified by performing a single comparison operation using a reference value. The specified bit is output from one of the cells corresponding to the physical address. If not matched, the bits (X2, . . . , Xn) are specified by performing multiple comparison operations using different reference values.

Abstract: Methods, apparatus, and systems are presented for communicating structured data in a system utilizing devices having different data processing capabilities. The methods, apparatus, and systems involve transmitting a unit of data from a first device, wherein the unit of data comprises at least a version-specific portion and a version identifier associated with the version-specific portion, receiving the unit of data at a second device distinct from the first device, processing the version-specific portion at the second device if the second device recognizes the associated version identifier, and disregarding the version-specific portion at the second device if the second device does not recognize the associated version identifier. Disregarding the version-specific portion may comprise examining a data length field in the data unit associated with the version-specific portion to determine a length value and skipping an amount of data corresponding to the length value.

Abstract: A method of testing write enable lines of random access memory having at least one word having one or more write enable inputs for controlling write operations in the word, comprises, for a selected memory address, shifting a series of test bits through an addressed word via a first data input to the word, and for each test bit, performing a write operation to the word using a write enable test input derived from data outputs of the word or from a test write enable signal applied concurrently to each write enable input; and, after each write operation, comparing a last bit of the word against an expected value to determine whether there exists a defect in a write enable line.

Abstract: An apparatus for testing a memory device having a plurality of data lines includes an input circuit, a compression circuit, and an output circuit. The input circuit is adapted to receive at least a first subset of the data lines and a plurality of enable signals. Each enable signal is associated with at least one of the first subset of data lines. The compression circuit is coupled to the input circuit and is adapted to detect a predetermined pattern on the first subset of data lines. The output circuit is coupled to the compression circuit and adapted to provide at least a pass signal when the predetermined pattern is detected on the first subset of data lines. The input circuit is capable of masking at least one of the first subset of data lines from the compression circuit based on the associated enable signal.

Abstract: A testing circuit includes m block test units and a first logical processing unit. The block test unit compares a first data outputted from a test object with a reference data, and outputs a result as a test circuit output signal based on a output control signal. The first logical processing unit judges whether the all of the m test circuit output signals indicate that the first data is coincident with the reference data, and outputs a result as a total judgment result signal based on the m test circuit output signals. The block test unit includes a block judging unit and a block output selecting unit. The block judging unit compares the first data with the reference data to judge whether the first data is coincident with the reference data, and outputs a result as a block judgment result signal.

Abstract: Embodiments of the present invention generally provide methods and apparatus for testing memory devices having normal memory elements and redundant memory elements. During a front-end testing procedure, normal memory elements that are found to be defective are replaced by redundant memory elements. During the front-end test, redundant memory elements that are found to be defective may be marked as defective by blowing associated mask fuses. During a back-end testing procedure, the results of testing a normal memory element may be masked (e.g., forced to a passing result) if the normal memory element has been replaced by a redundant memory element. Similarly, the results of testing a redundant memory element may be masked if the redundant memory element was previously found to be defective, as indicated by an associated mark fuse.

Abstract: A test circuit for a memory device having a pair of arrays each of which includes a plurality of memory cells arranged in rows and columns. A pair of complementary digit lines is provided for each column of each array. The digit lines are selectively coupled to a pair of I/O lines for each array which are, in turn, coupled to a pair of complementary data lines. The data lines are coupled to respective inputs of a DC sense amplifier, one of which is provided for each array. A multiplexer connects the pair of I/O lines for either one of the arrays to the data lines in a normal operating mode. Thus, in the normal operating mode, data are selectively coupled to the inputs of the DC sense amplifier from the complementary digit lines for an addressed column. In a test mode, the multiplexer connects the I/O lines for both arrays to the data lines to compress the data from the two arrays.

Abstract: An apparatus for testing an on-chip ROM and a method thereof are provided. By embedding the on-chip ROM test apparatus in a semiconductor chip and externally providing only minimal information, the apparatus and the method can prevent the possible exposure of ROM data stored in the ROM. Also, according to the apparatus and method, information related to the ROM address at which an error occurred can be provided together with the test result and by feeding the ROM address information back to the manufacturing process, product yield can be improved.

Abstract: Methods and apparatus for accessing modules on a flash memory package concurrently during testing are disclosed. According to one aspect of the present invention, a memory device for storing data includes a plurality of modules and a logic block. The plurality of modules each include a plurality of storage elements that hold the data. The logic block is arranged to enable the plurality of modules to be accessed in parallel, and is also arranged to enable the plurality of modules to be accessed serially.

Abstract: A built-in self-test (BIST) circuit is configured to divide data output bits of a RAM macro into a plurality of groups each consisting of 2 bits, and provide a 1-bit comparator of a signature analyzer for each group to share one 1-bit comparator by respective two data output bits. A selector of a bit changer sequentially selects a data output bit from each group, and the 1-bit comparator sequentially compares output data for the selected data output bit with expected value data.

Abstract: A testing method involves information being written to memory addresses and being read from the memory addresses. The method which logically combines parallel memory bank actuation of the memory addresses using an interleaved mode, which is implemented in relation to disjunct subareas of the memory banks, with one another. This shortens the test time required for testing the semiconductor memory.

Abstract: Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data compression test mode. In the data compression test mode, reading one word of an output page provides an indication of the data values of the remaining words of the output page. The time necessary to read and verify a repeating test pattern can be reduced as only one word of each output page need be read to determine the ability of the memory device to accurately write and store data values. The memory devices include data compression circuits to compare data values for each bit location of each word of the output page. Output is selectively disabled if a bit location for one word of the output page has a data value differing from any remaining word of the output page.

Abstract: A semiconductor device having many pins is tested using a test system having fewer pins. The test system includes a pin electronics (PE) card and a pattern memory. The PE card preferably includes a plurality of comparator and driver units to drive predetermined input signal pattern to be applied to an input pin of the semiconductor device and to compare data output from an output pin of the semiconductor device with a predetermined output signal pattern. Some or all of the pins of the semiconductor device may be divided into pin groups having K number of pins. The PE card also preferably includes a plurality of control units for electrically connecting each of the comparator and driver units to a selected pin in a selected pin group in response to a control signal.

Abstract: The specification may disclose a computer system that may operate a portion of available memory as backup to a primary memory, and the computer system may be adapted to test the backup memory for memory errors at times other than execution of power-on self-test procedures.

Abstract: An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. Transitions of the Read/Write control line during a burst access will terminate the burst access, reset the burst length counter and initialize the device for another burst access. The device is compatible with existing Extended Data Out DRAM device pinouts, Fast Page Mode and Extended Data Out Single In-Line Memory Module pinouts, and other memory circuit designs.

Abstract: A method of safeguarding program parts which are critical to safety against inadvertent execution is described. In this method, at least one program part is executed in a predetermined chronological sequence. At a certain time in the execution, a pattern is generated. At least at one later time, a check is then performed to determine whether the pattern is present. If the pattern is not present, the execution of the respective program part is terminated. A memory device for executing such a method is also described.

Abstract: Magnetic Random Access Memory (MRAM) can be programmed and read as fast as Static Random Access Memory (SRAM) and has the non-volatile characteristics of electrically eraseable programmable read only memory (EEPROM), FLASH EEPROM or one-time-programmable (OTP) EPROM. Due to the randomness of manufacturing process, the magnetic tunnel junctions (MTJ) in MRAM cells will require different row and column current combinations to program and not to disturb the other cells. Based on adaptive current sources for programming, this disclosure teaches methods, designs, test algorithms and manufacturing flows for generating EEPROM, FLASH EEPROM or OTP EPROM like memories from MRAM.

Abstract: A pulse generation circuit including a pulse formation circuit for generating normal and dummy pulses according to second delay value data, a data calculation circuit for calculating first delay value data at a timing at which the pulses are generated from the pulse formation circuit according to pattern data having information for determining whether to generate pulses from the pulse formation circuit, a dummy pulse control circuit for controlling generation of a dummy pulse in a no-pulse-generation cycle from the pulse formation circuit according to the second delay value data obtained by detecting the no-pulse-generation cycle from the first delay value data, and a logical gate circuit for eliminating the dummy pulses generated from the pulse formation circuit.

Abstract: It is possible to read out data in accordance with a read-out address from memory cells via bit lines and primary sense amplifiers. Each secondary sense amplifier is assigned a group of primary sense amplifiers. It is possible for the primary sense amplifiers of a group to be connected to one of the secondary sense amplifiers in each case via switching devices in order to apply the datum from one of the primary sense amplifiers to the assigned secondary sense amplifier via the switching device selected by the read-out address. For reading out data, a test control unit is provided to connect some of the switching devices in parallel depending on a test mode signal and depending on a read-out address, so that in each case one of the group of primary sense amplifiers is connected to the assigned secondary sense amplifiers.

Abstract: A fail analysis device enabling a simplified operation and a reduced operation time. A reduced data acquiring section (40) reads a reduced logical data, obtained by reducing detailed logical data as a test result, from a CFM (120) in a semiconductor test device (100) and acquires it. A main viewer generating section (80) generates a main viewer window including a list of a test result for each DUT based on the reduced logical data for displaying on a display device (94). The list includes a result image indicating a pass/fail for each DUT and the reduced image of a fail bit map.

Abstract: An emulation parameter indicative of a data processing operation performed by a data processor is exported from the data processor. The parameter value is provided as a plurality of digital bits. After determining that the bits of a first group within the plurality of bits all have the same bit value and that a predetermined bit within a second group of the plurality of bits has a bit value equal to the bit value of the bits of the first group, only the second group of bits is output from the data processor without outputting the first group of bits.

Abstract: In a storage device for maintaining information when power is OFF and being capable of executing a test process based on test signals, a test terminal inputs the test signals and an instruction part sends a read out instruction for instructing a memory storing secret data to read out data. Moreover, a decoding part decodes whether or not the data read out by the memory in response to the data reading instruction is the secret data stored in the memory and a maintaining part maintains information in a volatile state resulting from the decoding part. Furthermore, a cutting-off part cuts off the test signals input from the test terminal when the maintaining part maintains information indicating that the secret data is stored.

Abstract: A method for identifying defective data sectors in a disk drive comprising generating a test pattern on a portion of a disk surface; reading the test pattern on the portion to detect an error and if an error is detected: associating the error with a physical location on the portion to identify a defective area unsuitable for user data; and assigning a severity category to the defective area. The method further comprises providing a physical defect list (P-list) for listing each defective area, the P-list having a predetermined limit to restrict a number of P-list entries; and posting the defective areas having a first severity category to the P-list and if the P-list limit is not exceeded by the first severity category entries: posting defective areas having a second severity category to the P-list.

Abstract: An array built-in, on-chip self test system for testing a memory array and a method of testing the memory array. The memory array has data input ports, data output ports, and address ports, and a data control subsystem, an address control subsystem, and a comparator. The data control subsystem generates and applies deterministic data patterns to the data input ports of the memory array. The address control subsystem generates addresses for application to the memory array in coordination with said data control subsystem, and includes a sequence counter, a count rate controller for the sequence controller, a count rate controller divider to control the number of cycles per address, an address controller to provide granular control of addresses, and an X-OR gate receiving an input from a sequence counter and from the address controller, the X-OR gate outputting an address bit to the memory array.

Abstract: A technique for adjusting a communication system involves a link, where the link includes a data line arranged to transmit a data signal and a clock line adapted to transmit a clock signal. The technique uses one or more counters to test the transmission across the link. Dependent on one or more of these counters, a test circuit, connected to the link, compares a known test pattern signal to a latched test pattern signal transmitted on the data line. The test circuit includes an adjustment circuit arranged to generate an adjustable clock signal from the clock signal, where the adjustable clock signal determines when to latch the transmitted test pattern signal The test circuit adjusts a timing of the adjustable clock signal relative to the data signal of the link.

Abstract: Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added test pads allow a tester to probe and test more circuits within the die simultaneously. Also, the added test pads contribute to a reduction in the amount of test wiring overhead traditionally required to access and test circuits within a die, thus reducing die size.

Abstract: A semiconductor integrated circuit device includes test data output nodes arranged in a width of a plurality of bits and an internal data bus, greater in bit width than the test data output nodes, for transferring internal data. A predetermined number of bits of the internal data on the internal data bus are compared with bits of test expected value data equal in bit width to the test data output nodes for each bit. The predetermined number of bits of the internal data are selected in accordance with a test address signal. The bits selected is compared with the respective bits of the test expected valued data. Data indicating respective comparison results are output to the test data output nodes in parallel.

Abstract: A content addressable memory (CAM) device having circuitry to generate a biased sequence of addresses. A first counter circuit increments an address value in response to a clock signal and resets the address value to a start address in response to a control signal. A second counter increments a limit value in response to a control signal. A compare circuit compares the address value and the limit value and, if the address value and the limit value have a predetermined relationship, asserts the control signal.

Abstract: A system is capable of receiving Fast Page mode, Extended Data Out mode, Burst Extended Data Out mode, or a combination of these memory devices. A method of determining the type of memory present allows the system to adjust internal memory access signals in accordance with the type of memory installed. The system may be shipped with a first type of memory, and then upgraded to a second type of memory by the user to improve overall system performance. A first bank of memory may be of a first type, and a second bank may be of another type. The user may make cost versus performance decisions when upgrading memory types or capacities.

Abstract: A method for optimizing a source synchronous clock reference signal timing to capture data from a memory device (e.g., DDR SDRAM) includes conducting an iterative two-dimensional data eye search for optimizing the delay of the source synchronous clock reference signal (e.g., DQS). Embodiments of the present invention are directed to tuning the delay for each device for the optimal margin in two dimensions: maximize the distance from the data eye walls and maximize the noise margin on the interface. An iterative data eye search is performed while varying the DQS delay timing and noise margin.

Abstract: A method and system for testing multiported memories, especially when one or more of the ports are not directly accessible without intervening logic. The method and system segregates the multiported memory into at least two portions which are then used for testing the one or more ports which are not directly accessible.

Abstract: The invention provides a method for testing a memory unit (113) to be tested in a test device (100), the memory unit (113) to be tested being introduced into the test device (100), a first data register (102a–102N) to be tested being read out from the memory unit (113) to be tested and being tested in a comparator unit (106), and then at least one further data register (102a–102N) to be tested being read out of the memory unit (113) to be tested and tested in a comparator unit (106).

Abstract: The present invention relates to a packet command driving type memory device, a method for compressing output data according to the present invention is characterized to write first data of a certain bit in a corresponding address of core cell regions, read the first data of a certain bit written in the address, compare the written data and the read data by dividing it to an upper certain bit and a lower certain bit, generate compressed data of 1 bit with an information about whether a fail is.

Abstract: Method and system for shortening the time needed to test a semiconductor device having a plurality of memory circuits. The semiconductor device includes an address decoder for selecting a plurality of memory circuits and causing the memory circuits to perform a read/write operation. A comparator receives plural pieces of read data read from the plurality of memory circuits and compares the plural pieces of read data with one another. A processing unit compares one of the plural pieces of read data with write data. Using the comparison results of the comparator and the processing unit shorten the time needed to test the plurality of memory circuits.

Abstract: Disclosed is an article of manufacture, system, and program for determining device suspension and device blocking. Local session cache usage and residual counts are compared against limit values associated with that session, wherein the limit values comprise a device blocking count, a device blocking percent, a suspend count, and a suspend percent for the local session. If a cache in trouble condition is detected based on the comparison, the cache in trouble condition is processed to determine whether one or more volumes are to be blocked or suspended.

Abstract: A method for data verification in a data storage environment including the steps of (A) sending a command from an initiator to a target, where the command defines an expected data pattern, (B) sending a block write command from the initiator to the target, where the write command initiates sending data from the initiator to the target, (C) comparing data received to the expected data pattern and (D) generating a status indication in response to the comparison.

Abstract: An apparatus and a method are disclosed for reducing the pin driver count required for testing computer memory devices, specifically Rambus DRAM, while a die is on a semiconductor wafer. By reducing the pin count, more DRAMs can be tested at the same time, thereby reducing test cost and time. One preferred embodiment utilizes a trailing edge of a precharge clock to select a new active bank address, so that the address line required to select a new active address does not have to be accessed at the same time as the row lines.

Abstract: In a computer device, a latch circuit latches a program read from a ROM. Even when a program C is mistakenly read from the ROM in place of a correct program B, a CPU outputs an access signal to the ROM again to read the program B at the same address from the ROM, and a match detection circuit compares the program B with the program C output from the latch circuit. Since these programs fail to match with each other, the CPU outputs the access signal again. If the ROM outputs the program B correctly this time, the program B matches with the program B output from the latch circuit when the match detection circuit compares these programs. The CPU then executes the program B as correctly read ROM data. Thus, even when a program in the ROM is mistakenly read, safe operation by a correctly read program is ensured.

Abstract: An electrolytic cell which comprises at least one anode and at least one cathode, an inlet channel through which liquor may be charged to the electrolytic cell, and an outlet channel through which liquor may be removed from the electrolytic cell, in which the outlet channel is operatively connected to the inlet channel, and in which the inlet channel comprises an ejector. The inlet and outlet channels may be formed in a unit made up of a plurality of shaped sheets, e.g. of electrically non-conducting plastics material, which together form the inlet and outlet channels.