Abstract: Self-test instructions are loaded from a tester into a configuration array of a memory device, and then a control circuit of the memory device sequentially reads and executes the self-test instructions while the tester is in an idle state. Data patterns are written to a main memory array of the memory device the internal self-test process. The control circuit includes a comparator for detecting defective memory cells by comparing data values read from the main array with the data pattern previously written into the main memory array. A BIN counter identifies the currently-executed self-test instruction, and is read and transmitted to the tester when an error is detected.

Abstract: The memory device contains comparison units with which it is possible to check whether an address applied to the memory device is associated with a memory cell which cannot be properly written to or read out or is located in a memory cell area containing memory cells which cannot be properly written to or read out. During the testing of the memory device, the comparison units can be placed into a state which differs from the state of the comparison units during the normal operation of the memory device.

Abstract: A data processor automatically analyzes test data after a small subset of the lot of IC packages has been tested for determining whether a rescreen condition has occurred in real-time. When the rescreen condition has occurred, a warning is provided in real-time shortly after testing of the small subset. Thus, time is not wasted in testing the whole lot of articles with the rescreen condition, and a small number of failed articles is retested after the rescreen condition is corrected thus maximizing tester utilization.

Abstract: A data memory to be tested is connected to a processing unit. Data items to be stored are produced from a test pattern data item in the processing unit and are stored in the data memory. The data memory is tested in that the test pattern data items are received from a test device, processed using a first function to form data items to be stored, and the data items are then stored. After the stored data items are read from the memory they are processed with a second function to form test data items whose number is once more smaller than the stored data items that are read from the memory.

Abstract: Apparatus for transferring data from a host computing system to one or more magnetic tape storage devices or the like, the apparatus comprising input apparatus for receiving data and converting it into codeword pairs in a format suitable for storage on the tape, a write head for writing the codeword pairs in codeword quad (CQ) sets of 2×8 codeword pairs to the tape, a read head for reading back data written to the tape and transferring the read data to an error checking block which is arranged to generate a negative output if a codeword pair includes an error and/or more than a predetermined number of errors, and control apparatus for causing the write head to rewrite a CQ set to the tape in response to a negative output from the error checking block, the control apparatus being configured or configurable to rewrite a CQ set to the tape until all of the codeword pairs (or CQ's) in that CQ set are written without error (or less than a predetermined number of errors) during the same rewrite, thereby maximizing

Abstract: A test pattern generation and comparison circuit creates test pattern stimulus signals for and evaluates response signals from logic or memory such as random access memory (RAM). It utilizes both parallel and serial interfaces to the logic/memory under test. The test pattern generation and comparison circuit further provides a method for testing logic and memory utilizing built-in self test (BIST) techniques. The method uses a programmable logic/memory commands which are translated into physical logic signals and timings for the logic or memory under test. The results of the test pattern generated and applied to the logic or memory are compared to expected results. The result of the comparison is a pass/fail designation. In addition, the comparison of the expected test results with the actual test results provides information on the exact location of the failure.

Abstract: An I/O compression circuit for a semiconductor memory device operates in a same data compress mode to transmit identical data to all compressed data buses and a different data compress mode to transmit different data to adjacent compressed data buses.

Abstract: Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data compression test mode. In the data compression test mode, reading one word of an output page provides an indication of the data values of the remaining words of the output page. The time necessary to read and verify a repeating test pattern can be reduced as only one word of each output page need be read to determine the ability of the memory device to accurately write and store data values. The memory devices include data compression circuits to compare data values for each bit location of each word of the output page. Output is selectively disabled if a bit location for one word of the output page has a data value differing from any remaining word of the output page.

Abstract: Circuitry is provided to allow early switching of input signals from a first configuration directed to blow a first anti-fuse to a second configuration directed to blow a second anti-fuse, yet still allow complete blowing of the first anti-fuse. Such circuitry may be applied to methods of repairing a memory device after testing. Data concerning available repair cells may be stored in at least one on-chip redundancy register.

Abstract: An input/output pin for test corresponding to a test circuit of the digital section is used in common as the input/output pin for normal operation of the analog section. The selection switches are respectively provided between the relevant analog pin and analog circuit and on a signal line up to the test circuit of the digital section from the relevant analog pin and the switches are provided at both end portions of the signal line between the test circuit of digital section and the input/output pin for common use in order to fix the voltage of the signal line to the predetermined voltage such as the ground voltage during the normal operation.

Abstract: An electronic memory device tester has an input arranged to receive seed data with a first number (p) of seed data bits from a computer and a data generator arranged to receive an array of prepared data having a second number (q) of prepared data bits, where q>p, and arrange to generate from the prepared data a test data pattern for writing to an electronic memory device to be tested. The tester generates its own test pattern thus relieving the computer processor from that task. This in turn allows the computer to control the test cycle itself without compromising the test speed.

Abstract: The present invention pertains to radiation sources that mimic radiation environment(s) encountered by packaged semiconductor devices. The sources are suitable for use in test systems operative to test for soft error and/or failure rates in devices sensitive to such radiation. The radiation is highly active to exacerbate soft error rates and thereby accelerate testing and reduce test times. The sources are also relatively uniformly distributed within a medium to simulate the direction(s) and energy spectra of radiation that would actually be encountered by semiconductor devices in device operation.

Abstract: A system and method for chip testing is disclosed. The present invention's method includes the steps of establishing a communications link between a chip and a computer tester; receiving on the chip an initial test algorithm over a communications link; testing the chip, using a built-in self-test (BIST) circuit on the chip, in accordance with the initial algorithm; collecting a set of failure information in response to testing; and transmitting the failure information from the chip to the computer over the communications link. The present invention's system includes: a communications link; a computer, operating a set of chip testing software; and a chip under test coupled to the computer by the communications link, having, a memory array; and a BIST module for testing the memory array in response to test algorithms received from the computer and transmitting those addresses within the memory array which failed testing.

Abstract: In one embodiment, an array of content addressable memory (CAM) cells include a first plurality of CAM cells and a second plurality of CAM cells. The second plurality of CAM cells has a width sufficient to address a height of the array. A first plurality of CAM drivers are coupled to the array to drive the first plurality of CAM cells. The first plurality of CAM drivers prevent the first plurality of CAM cells from participating in a match when the array is in a test mode.

Abstract: The present invention is a self-test circuit (BIST) incorporated in the memory device, which is activated in response to a test activation signal from outside. When this self-test circuit is activated in response to a test activation signal (WBIZ) from outside, it generates a test operation command (WBI-CMD), generates a test address (WBI-ADD), and generates test data (WBI-DATA). Furthermore, after the self-test circuit writes the test data to a memory cell, it effects a comparison to establish whether or not the read data that is read from this memory cell is the same as the test data that was written thereto and stores information as to the result of this comparison. This comparison result information is then output to the outside.

Abstract: A preferred exemplary embodiment of the current invention concerns a memory testing process, wherein circuitry is provided on a chip to allow on-chip comparison of stored data and expected data. The on-chip comparison allows the tester to transmit in a parallel manner the expected data to a plurality of chips. In a preferred embodiment, at most one address—and only the column address—corresponding to a failed memory cell is stored in an on-chip register at one time, with each earlier failed addresses being cleared from the register in favor of a subsequent failed address. Another bit—the “fail flag” bit—is stored in the register to indicate that a failure has occurred. If the fail flag is present in a chip, that chip is repaired by electrically associating the column address with redundant memory cells rather than the original memory cells. Subsequently, the chip's register may be cleared and testing may continue.

Abstract: A method of testing a semiconductor device having a memory is disclosed. The method includes selecting a portion of the memory; testing the selected portion of the memory; designating the selected portion of the memory as a designated memory in response to an acceptable testing result; and storing data in the designated portion of the memory for retrieval at a later time. Provision for soft repair of the selected memory is made. Test data can be compressed before being stored in the designated memory.

Abstract: A memory testing method and apparatus are provided, which can test in short time a flash memory. In case of testing a flash memory having block function, in a memory testing method and apparatus in which a predetermined logical value is written in memory cells constituting each of blocks of the memory, the written logical value is read out from the memory cells to compare it with an expected value, and a decision that, when the read-out logical value and the expected value do not coincide with each other, such memory cell is a failure memory cell, a decision is rendered that, when the number of failure memory cells in each block reaches a predetermined number, such block is a bad block, and the test of such block is stopped.

Abstract: A method for testing semiconductor chips, in particular semiconductor memory chips, is described. In which, in a chip to be tested, at least one test mode is set, the test mode is executed in the chip and test results are output from the chip. It is provided that, after the setting and before the performance of the test mode, a check mode is executed in which the status of the test mode set in the chip is read out in a defined format.

Abstract: A method and system for testing the logic of a complex digital circuit containing embedded memory arrays. One embodiment provides for a process which first creates a model for the memory array in the circuit. Next, the memory array is loaded with values representing the model. For example, the memory array may be modeled as a wire by loading each memory location with its address. In this fashion, the data output of the memory array will be equal to the input address. Next a test pattern is generated, based upon the model of the memory array. The memory array is prevented from being written while the test pattern is scanned into the circuit. In this fashion, the output of the memory array is predictable and the output of the circuit may be monitored to determine if the combinational logic has any defects.

Abstract: An apparatus and a method are disclosed for reducing the pin driver count required for testing computer memory devices, specifically Rambus DRAM, while a die is on a semiconductor wafer. By reducing the pin count, more DRAMs can be tested at the same time, thereby reducing test cost and time. One preferred embodiment utilizes a trailing edge of a precharge clock to select a new active bank address, so that the address line required to select a new active address does not have to be accessed at the same time as the row lines.

Abstract: A semiconductor memory device having an externally controllable input and output mode is provided. The semiconductor memory device includes a first and second plurality of pads and an input and output mode set circuit electrically connected to the first plurality of pads and the second plurality of pads, for generating a plurality of input and output mode signals. The input and output mode set circuit cuts off signals received from the first plurality of pads, controls the level of each of the input and output mode signals to be at either a logic high level and a logic low level, and sets the input and output mode when a voltage higher than the supply voltage of the semiconductor memory device is applied to one of the second plurality of pads in a test mode.

Abstract: A method and apparatus for initializing dynamic random access memory (DRAM) devices is provided wherein a channel is levelized by determining the response time of each of a number of DRAM devices coupled to a bus. Determining the response time for a DRAM device comprises writing logic ones to a memory location of the DRAM device using the bus. Subsequently, a read command is issued over the bus, wherein the read command is addressed to the newly-written memory location of the DRAM device. The memory controller then measures the elapsed time between the issuance of the read command and the receipt of the logic ones from the DRAM device, and this elapsed time is the response time of the DRAM device. Following the determination of a response time for each DRAM device, and using the longest response time, a delay is computed for each of the DRAM devices coupled to the bus so that the response time, in clock cycles, of each of the DRAM devices coupled to the bus equals the longest response time.

Abstract: A system for analyzing bitmap test data includes a fault shape analyzer which continuously and automatically receives bitmap test data. In use, the user creates at least one failure pattern analysis order to be performed by the fault shape analyzer, the order specifying a particular failure pattern to be identified. Based on the order, the fault shape analyzer creates a bitmap display of a user-specified sector using selected bitmap test data. The fault shape analyzer identifies the user-specified failure pattern in the bitmap display by multiplying, at various locations, the bitmap display in the frequency domain and the failure pattern in the frequency domain. A comparison between the product of the multiplication process and the failure pattern is performed to locate failure patterns in the bitmap display. Failure patterns identified from the comparison process are saved as defect files which, in turn, are stored in a failure pattern classification database.

Abstract: A memory block is subject to an erasure operation by a batch operation. Subsequently, a read-out test is conducted upon the memory block to count the number of unerased memory cells. If the count FN is equal to or greater than a given number TF, a plurality of erasure operations are conducted consecutively next. If FN<TF, a single erasure operation is conducted next, subsequently followed by a read-out test. The erasure operations and the read-out tests are repeated.

Abstract: A semiconductor memory includes a memory cell array, a fail-memory configured to store data for deficient bits, deficient rows, and deficient columns, a comparator configured to compare a value stored in the memory cell with a value of the test vector, and to detect deficient bits, and a deficient row detector configured to compare the number of deficient bits with a first criterion, to detect an address of the deficient rows when the number of deficient bits is larger than the first criterion.

Abstract: Memory segment overwrites are detected by providing a redundant header at the end of a segment and comparing a redundant header to an initial header. In specific embodiments, overwrites may be detected both after segment writes and prior to buffer reads. In further embodiments, some header overwrite errors may be corrected to increase the mean time between failure of a logic system.

Abstract: A memory circuit having a memory cell array in which a plurality of memory cells are provided at intersection points of a plurality of word lines and a plurality of bit line pairs and a peripheral circuit for performing an operation of selecting an address is provided with a computing circuit for generating an address signal for test; a packet decoder for designating the kind of computation to the computing circuit; and an input circuit for supplying a test signal comprising a plurality of bits for designating a test operation to the packet decoder.

Abstract: Embodiments of the present invention generally provide methods and apparatus for testing memory devices having normal memory elements and redundant memory elements. During a front-end testing procedure, normal memory elements that are found to be defective are replaced by redundant memory elements. During the front-end test, redundant memory elements that are found to be defective may be marked as defective by blowing associated mask fuses. During a back-end testing procedure, the results of testing a normal memory element may be masked (e.g., forced to a passing result) if the normal memory element has been replaced by a redundant memory element. Similarly, the results of testing a redundant memory element may be masked if the redundant memory element was previously found to be defective, as indicated by an associated mark fuse.

Abstract: A method and a test tool 110 are provided for verifying the functionality of a software based unit 100 which is provided with an interface 105 for its external communication. Pre-recorded data is used for the reproduction of a test case and for the verification of a unit subject to the test case. The pre-recorded data includes pre-recorded input data 125 and pre-recorded output data 126. The pre-recorded input data is applied to an interface of the unit and the pre-recorded output data is compared with the data transmitted from the unit in response to the applied pre-recorded input data. If the data transmitted from the unit is in correspondence with the pre-recorded output data, the functionality of the unit in accordance with the specific test case has been verified.

Abstract: A system is capable of receiving Fast Page mode, Extended Data Out mode, Burst Extended Data Out mode, or a combination of these memory devices. A method of determining the type of memory present allows the system to adjust internal memory access signals in accordance with the type of memory installed. The system may be shipped with a first type of memory, and then upgraded to a second type of memory by the user to improve overall system performance. A first bank of memory may be of a first type, and a second bank may be of another type. The user may make cost versus performance decisions when upgrading memory types or capacities.

Abstract: A method for testing a data path for a semiconductor memory device, in accordance with the present invention, includes providing a semiconductor memory device including a plurality of stages in a data path, and transferring data into the data path. Components are disabled to isolate at least one stage of the plurality of stages such that data written to or read from the at least one stage is available at an output. The data at the output is preferably compared to expected data. Alternately, system level calibration between devices may be performed to ensure proper communication between devices without destroying data in a memory array and making a dynamic data skew calibration possibly while running an application.

Abstract: A method for testing the refresh device of an information memory contains the following: a refresh selector for selecting memory cells to be refreshed; a sensor for sensing the state of each cell selected by the selector and a restorer for setting each selected cell into a fresh state, which, in a refresh operating mode of the restorer which effects the refreshing, represents the information derived from the sensed state. According to the invention, at the beginning of the test, the states of the cells that are to participate in the test are verified and before the elapsing of the guaranteed minimum retention time of the memory cells after this verification, the restorer is operated in a test operating mode in which the fresh state that it is to set for each participating cell is in each case a predetermined state which differs perceptively from the previously verified state.

Abstract: The present invention provides a system and method for performing a memory test algorithm with a static random access memory (SRAM) unit having a read control module with no read enable control and write control module with write enable control. The system and method conduct read and write operations to the SRAM unit by avoiding simultaneously reading and writing to the same memory address. Simultaneously reading and writing to the same memory address is avoided by offsetting the read and write signals provided to the SRAM unit.

Abstract: An apparatus for verifying the data retention in a non-volatile memory is described which comprises at least one multiplexer and at least one shift register. The multiplexer and the at least one shift register are disposed so that the data of the non-volatile memory are in input to the multiplexer the output of which is in turn in input to the at least one shift register. The apparatus comprises a logical circuitry which by suitable commands controls the data transfer from said multiplexer to said at least one shift register, the data loading and the output data shifting in said at least one shift register.

Abstract: A method of forming an optical disc, and an optical disc formed, so as to facilitate identifying unauthorized copies of the disc by using a defined procedure for reading the disc. The method comprises the steps of encoding digital data, comprised of a series of 0s and 1s, in the disc by forming a series of spaced pits along a track, so that the track comprises a series of pits and lands, and wherein, when said defined procedure is used to read the disc, each of said pits and lands is read as either a 0 or a 1. The method comprises the further step of forming at least one fuzzy area on the track so that when the defined procedure is used to read the disc, the fuzzy area is sometimes read as 0 and sometimes read as 1. With a preferred procedure, the pits reflect a given light beam at a first intensity, the lands reflect the given light at a second intensity, and the fuzzy area reflects the given light at a third intensity substantially midway between the first and second intensities.

Abstract: According to one embodiment of the invention, a method is provided for testing linked list integrity. The method includes storing a plurality of link pointers in memory in association with respective integrity parameters. The link pointers point to a next location in the memory storing a subsequent link pointer in the linked list. The method also includes reading the stored integrity parameter for at least one of the link pointers. The method also includes determining whether the value of the read integrity parameter matches the value of the stored integrity parameter.

Abstract: The invention provides a structure that does not employ complicated and large-scale control circuits or control memory, minimizes the circuits for real time processing, and allows the use of refresh memory. The invention provides a test clock (8-1) comprising a data processing apparatus (1-1) provided for each electrode pin of the measured device (11), a memory (2-1) that carries out reading and writing of the test pattern data and the like, a first-in-first-out element (4-1) that executes queue processing of the data read out from the memory, a delay circuit (5-1) that delays the output signal of the first-in-first-out element, and a measured device driver (6-1) that inputs into the electrode pin the output signal of the delay circuit, and in which the data processing apparatus (1-1) of adjacent test blocks are connected into a loop via the input-output circuit (3-1).

Abstract: A circuit that may be used to support testing of a memory block. The circuit generally comprises a decoder and a generator. The decoder may be configured to (i) decode a command signal into an address field, an operation field, and a data field and (ii) present a control signal to the memory block in response to the operation field. The generator may be configured to (i) present an address signal to the memory block in response to the address field and (ii) present a data signal to the memory block in response to the data field.

Abstract: An efficient and reliable technique is disclosed for detecting faults which occur in FIFO's, including control faults which are specific to FIFO's, as well as faults common to conventional memories, such as interport faults and faults that occur in single port memories. The technique utilizes a sequence of read, write and control operations, thereby avoiding the need to directly observe internal values within the FIFO, such as the full and empty flag values and the shift register values.

Abstract: A method of testing cache memory is used in a memory system having a primary memory unit and a cache memory unit. The method first writes a block of test data into the cache memory unit. Then, the test data is converted by a first encoding process into a first block of encoded data. The first block if encoded data is written into the primary memory unit. Data from the primary memory unit is fetched. The fetched data from the primary memory unit is converted by a second encoding process into a second block of encoded data. The second block of encoded data is stored into the cache memory unit. Either the first block of encoded data or the second block of encoded data is compared with a predetermined block of reference data to check whether the read/write operation to the cache memory unit is normal.

Abstract: A plurality of processors in a data processing system share a common memory through which they communicate and share resources. When sharing resources, one processor needs to wait for another processor to modify a specified location in memory, such as unlocking a lock. Memory and bus traffic are minimized during this waiting by first reading and testing the memory location. Then, the memory location is not read and tested again until the local copy of the cache line containing that memory location is invalidated by another processor. This feature is utilized both for a Lock instruction and a Wait for Change instruction, both of which utilize a timer parameter for specifying a maximum number of cycles to wait for another processor to modify the specified location in memory.

Abstract: A plurality of processors in a data processing system share a common memory through which they communicate and share resources. When sharing resources, one processor needs to wait for another processor to modify a specified location in memory, such as unlocking a lock. Memory and bus traffic are minimized during this waiting by first reading and testing the memory location. Then, the memory location is not read and tested again until the local copy of the cache line containing that memory location is invalidated by another processor. This feature is utilized both for a Lock instruction and a Wait for Change instruction, both of which utilize a timer parameter for specifying a maximum number of cycles to wait for another processor to modify the specified location in memory.

Abstract: A method of collecting failure information when testing a memory comprises performing a test of the memory according to a test algorithm, and, while performing the test, counting failure events which occur after a predetermined number of masked events; stopping the test upon occurrence of a stopping criterion which comprises one of occurrence of a first failure event, a change of a test operation; a change of a memory column address; a change of a memory row address; a change of a memory bank address; and a change of a test algorithm phase; and storing failure information.

Abstract: A method is disclosed for detecting defects in a recordable medium such as a hard disc drive based on error energy. The method may include the steps of writing test data to the medium and reading back the test data. The method may also include the steps of computing an error energy based on the square of the difference between the read back data and an ideal version of the test data and comparing the error energy with an energy threshold. The method generates a defect signal when the error energy exceeds the energy threshold. The method may also be used to identify the media defect according to its error energy profile. An apparatus for detecting defects in a recordable medium is also disclosed.

Abstract: A method wherein a special programming mode of a memory is entered. The special programming mode disables internal verification by the memory. The memory includes automation circuitry for program verification. A plurality of words is programmed into the memory without the memory performing internal program verification. Hashing is performed with respect to the plurality of data words to generate a first hash value. The host processor compares the first hash value with a second hash value to see whether the first and second hash values are the same or different. The special programming mode is exited and internal program verification by the memory is enabled. An apparatus is also described having a host processor and a memory with special programming mode circuitry.

Abstract: A method and apparatus for optimizing control on a bank to bank basis of a memory subsystem having a plurality of memory banks which are installed with different types of dynamic random access memory (DRAM) devices is presented. The present invention includes an improved DRAM controller comprises a set of configuration registers which store configuration bits corresponding to each memory bank in the main memory that is populated with the DRAM devices. The memory controller also includes a detection logic which together with a memory bank decode logic enables the memory controller determine whether a particular memory bank is populated with a page mode DRAM or an extended data out DRAM. The preferred embodiment also includes a column address strobe state machine which automatically controls timing requirements of both type of DRAM devices installed in the main memory to quickly and efficiently handle access requests.

Abstract: A method for calculating and analyzing redundancies for semiconductor memories, in accordance with the present invention, includes providing a memory device including at least one memory chip. The at least one memory chip includes a redundancy calculation region. The at least one memory chip is tested to determine failure addresses of failed components on each memory chip. The addresses of the failed components are input to the redundancy calculation region to compare the failure addresses to previous failure addresses stored in the redundancy calculation region to determine if new failures have been discovered. If a match exists between the previous failure addresses and the failure addresses, the failure addresses which match are terminated. Otherwise, the failure addresses are stored in the redundancy calculation region. It is then determined if the at least one memory chip is fixable based on the new failures which have been discovered. A system, preferably for on-chip implementation is also included.

Abstract: It is possible to read out data in accordance with a read-out address from memory cells via bit lines and primary sense amplifiers. Each secondary sense amplifier is assigned a group of primary sense amplifiers. It is possible for the primary sense amplifiers of a group to be connected to one of the secondary sense amplifiers in each case via switching devices in order to apply the datum from one of the primary sense amplifiers to the assigned secondary sense amplifier via the switching device selected by the read-out address. For reading out data, a test control unit is provided to connect some of the switching devices in parallel depending on a test mode signal and depending on a read-out address, so that in each case one of the group of primary sense amplifiers is connected to the assigned secondary sense amplifiers.

Abstract: A method for testing a semiconductor memory device according to one embodiment comprises the steps of: checking data in all addresses of the semiconductor memory device for correctness in-units of m×n bits: ending if it is determined that data in all the semiconductor memory device; if there is a defective address, comparing each m-bit data constituting the (m×n)-bit data corresponding to the defective address with its expected value; and if the comparison result indicates that the m-bit data is erroneous, determining whether the defective semiconductor memory device can be repaired. Due to this step, man hours required for testing a semiconductor memory device having a wide data bus of an (m×n)-bit width can be considerably reduced.