Special Test Pattern (e.g., Checkerboard, Walking Ones) Patents (Class 714/720)
  • Patent number: 10439925
    Abstract: This document describes systems, devices, and methods for testing the integration of a content provider's origin infrastructure with a content delivery network (CDN). In embodiments, the teachings hereof enable a content provider's developer to rapidly and flexibly create test environments that send test traffic through the same CDN hardware and software that handle (or at least have the ability to handle) production traffic, but in isolation from that production traffic and from each other. Furthermore, in embodiments, the teachings hereof enable the content provider to specify an arbitrary test origin behind its corporate firewall with which the CDN should communicate.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: October 8, 2019
    Assignee: Akamai Technologies, Inc.
    Inventors: Bradford A. Jones, Manish Gupta
  • Patent number: 10431301
    Abstract: Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a predetermined number of bits having a first logic state prior to storing the user data in memory cells. The auto-referenced read may store a total number of bits of the user data having a first logic state in a separate set of memory cells. Subsequently, reading the user data may be carried out by applying a read voltage to the memory cells storing the user data while monitoring a series of switching events by activating a subset of the memory cells having the first logic state. During the read operation, the auto-referenced read may compare the number of activated memory cells to either the predetermined number or the total number to determine whether all the bits having the first logic state has been detected.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: October 1, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Graziano Mirichigni, Paolo Amato, Federico Pio, Alessandro Orlando, Marco Sforzin
  • Patent number: 10338983
    Abstract: In general, the technology relates to a method for managing persistent storage. The method includes selecting a sample set of physical addresses in a solid state memory module, and performing a garbage collection operation on the sample set of physical addresses. The method further includes, after the garbage collection operation, issuing a write request to the sample set of physical addresses, issuing a request read to the sample set of physical addresses to obtain a copy of the data stored in the sample set of physical addresses, determining an error rate in the copy of the data stored using an Error Correction Code codeword or known data in the write request, determining a calculated P/E cycle value for the SSMM using at least the error rate, and updating an in-memory data structure in a control module with the calculated P/E cycle value.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: July 2, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Seungjune Jeon, Haleh Tabrizi, Andrew Cullen
  • Patent number: 10310742
    Abstract: The write reliability of a nonvolatile memory is improved by performing accurate verification of write data. In a memory controller of an information processing system, a determination unit determines whether a state of a memory cell after writing data is stable in a nonvolatile memory including the memory cell having an unstable state period after writing data. A verification unit performs verification by comparing read data which is read from the memory cell where the data is written on the basis of a result of the determination, with write data involved in the writing. A write control unit performs writing of the data and rewriting of the write data based on a result of the verification.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: June 4, 2019
    Assignee: Sony Corporation
    Inventor: Yasushi Fujinami
  • Patent number: 10288685
    Abstract: An apparatus that moves stimulus data and response data between a memory and a device under test (DUT) over a plurality of data transfer banks. In a first mode the data transfer banks output the stimulus data to the DUT as respective independent banks of serial stimulus data channels, and write the response data into the memory responsive to data provided as respective independent banks of channels of serial data from the DUT. In a second mode the data transfer banks output the stimulus data to the DUT as a single bank of combined serial stimulus data channels, and write the response data into the memory responsive to the data provided as a combined single bank of channels of serial data from the DUT.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: May 14, 2019
    Assignee: Keysight Technologies, Inc.
    Inventors: John H. Guilford, Gidget A. Cathcart, Joseph E. Mueller, Gregory A. Hill, Steven Joseph Narciso
  • Patent number: 10267855
    Abstract: IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: April 23, 2019
    Assignee: Texas Instruments Incorporated
    Inventors: Lee D. Whetsel, Baher S. Haroun, Brian J. Lasher, Anjali Vij
  • Patent number: 10204700
    Abstract: A memory system includes a semiconductor memory device and a test device. The semiconductor memory device includes a memory cell array, an error correction circuit and a test circuit. The test device controls a test of the semiconductor memory device, and the test device includes a first fail address memory and a second fail address memory. The test circuit performs a first test on the memory cell array to selectively record a first test result associated with the first test in the first fail address memory and performs a second test on the memory cell array to record a second test result associated with the second test in the second fail address memory. The test circuit is configured to perform the first test and the second test based on a test pattern data from the test device in a test mode.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: February 12, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoon-Na Oh, Deok-Gu Yoon, Sang-Uhn Cha
  • Patent number: 10074436
    Abstract: A memory device and a data reading method are provided. A dummy circuit performs a read operation in synchronism with a data access circuit according to an address signal, so as to estimate time points at which the data access circuit completes each of operating procedures, and enable the data access circuit to execute a next operating procedure when completing an operating procedure.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: September 11, 2018
    Assignee: Winbound Electronics Corp.
    Inventors: Koying Huang, Teng Su
  • Patent number: 9996295
    Abstract: A semiconductor memory device and a scrambling method thereof are provided, which are capable of realizing a balance between a data scrambling function and an accessible time. The semiconductor memory device of the invention includes a page buffer/sense circuit with the data scrambling function. During a programming operation, the page buffer/sense circuit holds data to be programmed, performs a scrambling process on the held data and programs the scrambled data to a selected page of a memory array. During a reading operation, the page buffer/sense circuit holds data read from the selected page and performs a descrambling process on the held data.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: June 12, 2018
    Assignee: Winbond Electronics Corp.
    Inventor: Naoaki Sudo
  • Patent number: 9875155
    Abstract: Provided are a memory device and a memory module, which perform both an ECC operation and a redundancy repair operation. The memory device repairs a single-bit error due to a ‘fail’ cell by using an error correction code (ECC) operation, and also repairs the ‘fail’ cell by using a redundancy repair operation when the ‘fail’ cell is not repairable by the ECC operation. The redundancy repair operation includes a data line repair and a block repair. The ECC operation may change a codeword corresponding to data per one unit of memory cells including the ‘fail’ cell, and may also change the size of parity bits regarding the changed codeword.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: January 23, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-soo Sohn, Kwang-il Park, Chul-woo Park, Jong-pil Son, Jae-youn Youn, Hoi-ju Chung
  • Patent number: 9864525
    Abstract: Systems, methods, and/or devices are used to implement variable bit encoding per NAND flash cell to extend life of flash-based storage devices and preserve over-provisioning. In some embodiments, the method includes detecting a trigger condition with respect to one or more non-volatile memory portions (e.g., portions configured to store data encoded in a first encoding format and having a first storage density) of a plurality of non-volatile memory portions of a storage device. In response to detecting the trigger condition and in accordance with a first determination that a projected amount of over-provisioning (e.g., corresponding to over-provisioning for the storage device after reconfiguring the one or more non-volatile memory portions to store data encoded in a second encoding format and having a second storage density) meets predefined over-provisioning criteria, the method includes reconfiguring the one or more non-volatile memory portions to store data encoded in the second encoding format.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: January 9, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Navneeth Kankani, Linh Tien Truong
  • Patent number: 9823860
    Abstract: A portion of a reprogrammable storage device is used to implement permanent data storage. The storage device includes a plurality of electrically erasable memory elements and a controller. The plurality of electrically erasable memory elements are configured to store data. Each memory element is programmable a number of write cycles before reaching a write failure state. The controller is coupled to the plurality of memory elements. The controller includes a receiver and a write engine. The receiver receives an instruction to drive a selected memory element to the write failure state. The write engine repeatedly writes a data value, in a plurality of write operations, to the selected memory element until the write failure state of the selected memory element is established.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: November 21, 2017
    Assignee: NXP B.V.
    Inventors: Marc Vauclair, Philippe Teuwen
  • Patent number: 9817070
    Abstract: IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: November 14, 2017
    Assignee: Texas Instruments Incorporated
    Inventors: Lee D. Whetsel, Baher S. Haroun, Brian J. Lasher, Anjali Vij
  • Patent number: 9787330
    Abstract: A controller has an error correction capability by including: a state monitoring unit that analyzes a state of a monitoring target and outputs state information; an error correction processing unit that switches error correction codes so that a correction rate for the respective states becomes a value within a predetermined range; and a correction rate calculation unit that calculates the correction rate for the respective states based on the correction result by the error correction processing unit.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: October 10, 2017
    Assignee: FANUC Corporation
    Inventor: Shinji Akimoto
  • Patent number: 9685241
    Abstract: A test circuit includes a control circuit that tests a memory having a plurality of data holding circuits holding data, a plurality of write ports, and a plurality of read ports, a write port selection circuit that selects any one of the plurality of write ports based on the write port identification information identifying any one of the plurality of write ports; and a read port selection circuit that selects any one of the plurality of read ports based on the read port identification information identifying any one of the plurality of read ports, wherein the control circuit sets the write port identification information and sets the read port identification information and carries out a test on the memory via the selected write port and the selected read port.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: June 20, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Koji Kuroda
  • Patent number: 9654111
    Abstract: Various embodiments of the invention allow to protect data in a logic circuit from being detected by commonly known observation methods. In certain embodiments, this is accomplished by selecting a set of reconfigurable logic blocks within the logic circuit to form a routing path in such a manner that the circuit performs a given function while making it virtually impossible to follow data through the circuit as the data is being processed. The routing path may be selected in a random or pseudorandom fashion, for example, in response to detecting an environmental change. In some embodiments, known data is injected into the logic path and the output is compared to a known value. If the result is incorrect, for example, because a section of the hardware ceased to properly perform due to a faulty circuit component, signals are routed through an operational part of the circuit to provide a different and valid logic path, while avoiding faulty logic gates.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: May 16, 2017
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Robert Michael Muchsel, Edward Tangkwai Ma, Donald Wood Loomis, III
  • Patent number: 9378845
    Abstract: A system for test plural memories simultaneously includes a pattern generation part which generates a pattern signal for testing and transmits the signal to the memories, a delay part which receives data through a first data line from a first memory device that is disposed in a closest position from the delay part and a second data line from a second memory device that is disposed in a farthest position from the delay part, and a determination part which determines the result of testing by comparing the data from the first memory device and the second memory device. The delay part output the first data and the second data to the determination part simultaneously.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: June 28, 2016
    Assignee: UNITEST INC.
    Inventor: Ho Sang You
  • Patent number: 9286964
    Abstract: Techniques and mechanisms to facilitate an operational mode of a memory device to prepare for a targeted refresh of a row in memory. In an embodiment, the memory device performs one or more operations while in the mode to prepare for a future command from a memory controller, the command to implement, at least in part, a targeted refresh of a row in a first bank of the memory device. Prior to such a command, the memory device services another command from the memory controller. In another embodiment, servicing the other command includes the memory device accessing a second bank of the memory device while the memory device operates in the mode, and before completion of an expected future targeted row refresh.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: March 15, 2016
    Assignee: Intel Corporation
    Inventors: John B. Halbert, Kuljit S. Bains
  • Patent number: 9280417
    Abstract: A codeword is generated from a message. One or more anchor values are appended to the codeword at predetermined anchor positions. Before the codeword is stored in a memory block, the locations and values of stuck cells in the memory block are determined. Based on the values and positions of the stuck cells, the values of the codeword are remapped so that values of the codeword that are the same as the values of the stuck cells are placed at the positions of the stuck cells. The remapped codeword is stored in the memory block. When the message is later read, the original codeword can be recovered from the remapped codeword based on the locations of the anchor values in the remapped codeword.
    Type: Grant
    Filed: May 21, 2013
    Date of Patent: March 8, 2016
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: John D. Davis, Parikshit Gopalan, Mark Manasse, Karin Strauss, Sergey Yekhanin
  • Patent number: 9246519
    Abstract: A method for producing a LDPC encoded test pattern for media in a LDPC based drive system includes adding error detection code data to a predominantly zero bit test pattern and adding additional zero bits to produce a test pattern of a desirable length. The test pattern may then be scrambled to produce a desirable flaw detection test pattern. The flaw detection test pattern may then be encoding with an LDPC code, or other error correction code with minimal disturbance to the run length constraints of the data pattern, and written to a storage medium.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: January 26, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Jefferson E. Singleton, Shaohua Yang, Bruce A. Wilson, Keenan T. O'Brien
  • Publication number: 20150067418
    Abstract: Disclosed is a storage tester capable of individual control for a plurality of storages, which comprises a host terminal for receiving user's control signal for storage test; a communication interface unit transmitting data among the host terminal, an embedded processor and a data engine unit; a data engine unit for generating pattern data and command data and reading the data from the storage; a sequence control module for controlling respectively a plurality of SATA/SAS/PCIe interface units; and SATA/SAS/PCIe interface unit for connecting to the storage through one among SATA, SAS, PCIe interface according to the signal for interface selection generated from the embedded processor and controlling a plurality of storages according to control of the sequence control module by the embedded processor in order to test respectively connected storage.
    Type: Application
    Filed: August 7, 2014
    Publication date: March 5, 2015
    Applicant: UNITEST INC.
    Inventor: Eui Won LEE
  • Publication number: 20150039953
    Abstract: A system for simultaneously determining a memory test result includes a pattern generation part generating a pattern signal for testing so as to transmit the signal through an address line and a command line; a delay part receiving read data through a first data line from a closest memory device that is disposed closer to the system and to receive read data through a second data line from a farthest memory device that is disposed farther from the system; and a determination part simultaneously determining the read data of the closest memory device and the read data of the farthest memory device, which are simultaneously output from the delay part, using a determination clock, wherein the delay part recognizes the read data of the closest memory device and the read data of the farthest memory device.
    Type: Application
    Filed: July 30, 2014
    Publication date: February 5, 2015
    Applicant: UNITEST INC.
    Inventor: Ho Sang YOU
  • Patent number: 8943239
    Abstract: A direct memory access controller for efficiently detecting a character string within memory, the direct memory access controller generating signatures of character strings stored within the memory and comparing the generated signatures with the signature of the character string for which detection is desired.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: January 27, 2015
    Assignee: Qualcomm Incorporated
    Inventors: Jian Shen, Jing Li
  • Patent number: 8930780
    Abstract: The present invention is related to systems and methods for harmonizing testing and using a storage media. As an example, a data system is set forth that includes: a data decoder circuit, a data processing circuit, and a write circuit. The data decoder circuit is configured to decode a test data set to yield a result. The data processing circuit is configured to encode a user data set guided by the result to yield a codeword. The write circuit is configured to store an information set corresponding to the codeword to a storage medium.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: January 6, 2015
    Assignee: LSI Corporation
    Inventors: Shaohua Yang, Bruce A. Wilson
  • Patent number: 8914688
    Abstract: In a method of executing a BIST operation on IC memory arrays having a common BIST control unit, a first BIST sequence is initiated. Each address for the arrays is incremented. The BIST control unit receives a signal indicating a maximum valid address in the array is reached, receiving a plurality of maximum valid addresses, which are recorded. A single relatively highest maximum valid address is determined. A first mode, which prevents BIST testing, is engaged in each array having reached the maximum valid address. A second BIST sequence is initiated based on having received the signal indicating a maximum valid address is reached from all the arrays connected to the common BIST control unit. An address count is decremented from the single relatively highest maximum valid address. The first mode is disengaged for each array as the address count reaches each of the maximum valid addresses during the decrementing.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: December 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: George M. Belansek, Kevin W. Gorman, Kiran K. Narayan, Krishnendu Mondal, Michael R. Ouellette
  • Patent number: 8910001
    Abstract: Method for testing a memory under test (1) including a plurality of memory cells and a Memory Built-In Self-Test Engine (2) connectable to a memory under test. The MBIST engine (2) is arranged to generate appropriate addressing and read and/or write operations to the memory under test (1). The MBIST engine (2) is connected to a March Element Stress register (MESR) (3), a generic march element register (GMER) (4), and a Command Memory (5). The GMER (4) specifies one of a set of Generic March Elements (GME), and the MESR (3) specifies the stress conditions to be applied. Only a few GMEs are required in order to specify most industrial algorithms. The architecture is orthogonal and modular, and all speed related information is contained in the GME. In addition, only little memory is required for the specification of the test, providing a low implementation cost, yet with a high flexibility.
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: December 9, 2014
    Assignee: Technische Universiteit Delft
    Inventors: Said Hamdioui, Zaid Al-Ars, Georgi Nedeltchev Gaydadjiev, Adrianus van de Goor
  • Patent number: 8819502
    Abstract: Exemplary method, system, and computer program embodiments for performing deterministic data verification by a storage controller are provided. Each of a plurality of concurrent write tasks is configured to be placed in a plurality of overlapping data storage ranges by performing at least one of: implementing a data generation function for generating pseudo-random data using a data seed, and generating a range map, the range map utilized as a lookup data structure to verify a chronological order for performing the plurality of concurrent write tasks, wherein a data address space is first designated in the range map as undetermined. Each of a plurality of read tasks is analyzed by comparing data read from a sub range in the plurality of overlapping data storage ranges against the data seed associated with the sub range.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: August 26, 2014
    Assignee: International Business Machines Corporation
    Inventors: Yair G. Chuchem, Adi Goldfarb, Zohar Zilberman
  • Patent number: 8775881
    Abstract: Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure is coupled to the logic chip. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: July 8, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Joe M. Jeddeloh
  • Publication number: 20140181602
    Abstract: A method includes receiving in a computing apparatus a model of an integrated circuit device including a memory array. The memory array is modeled as a plurality of device primitives. A test pattern analysis of the memory array is performed using the model in the computing apparatus. A system includes a memory array modeling unit and a test pattern analysis unit. The memory array modeling unit is operable to generate a model of an integrated circuit device including an memory array. The memory array is modeled as a plurality of device primitives. The test pattern analysis unit is operable to performing a test pattern analysis of the memory array using the model in the computing apparatus.
    Type: Application
    Filed: December 21, 2012
    Publication date: June 26, 2014
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Vibhor Mittal, Anirudh Kadiyala
  • Patent number: 8762799
    Abstract: A method for checking the functional ability of a memory element having a stack memory, wherein the stack memory occupies a defined region within the memory element. A stack memory pointer is defined, which displays, in the form of an address, a stack memory position, from which data are currently being removed or to which data are currently being written. In the memory element, a section of defined length arranged outside a memory region to be checked is delimited and used as an auxiliary memory; the current address of the stack memory pointer is stored before the start of a test program for checking the memory element and the stack memory pointer is then assigned an address associated with the auxiliary memory, so that during the test program the auxiliary memory is used as working memory; and after terminating the test program the stack memory pointer is reassigned the address of that position, which it displayed before the start of the test program.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: June 24, 2014
    Assignee: Endress + Hauser GmbH + Co. KG
    Inventor: Franco Ferraro
  • Publication number: 20140157067
    Abstract: A device under test has a connection interface, a controller, and a functional block. The connection interface is used to receive a test pattern transmitted at a first clock rate and output a functional test result. The controller is used to sample the test pattern by using a second clock rate and accordingly generate a sampled test pattern, wherein the second clock rate is higher than the first clock rate. The functional block is used to perform a designated function upon the sampled test pattern and accordingly generate the functional test result.
    Type: Application
    Filed: November 25, 2013
    Publication date: June 5, 2014
    Applicant: Silicon Motion Inc.
    Inventor: Tsung-Chieh Yang
  • Patent number: 8743638
    Abstract: A method and circuit for testing a multi-chip package is provided. The multi-chip package includes at least a memory chip, and the memory chip includes a number of memory cells. The method includes performing a normal read operation on the memory cells to check if data read from the memory cells is the same with preset data in the memory cells; and performing a special read operation on the memory cells to check if data read from the memory cells is the same with an expected value, wherein the expected value is independent from data stored in the memory cells.
    Type: Grant
    Filed: August 1, 2012
    Date of Patent: June 3, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Chun-Hsiung Hung, Wen-Chiao Ho, Kuen-Long Chang
  • Publication number: 20140149810
    Abstract: In a method of executing a BIST operation on IC memory arrays having a common BIST control unit, a first BIST sequence is initiated. Each address for the arrays is incremented. The BIST control unit receives a signal indicating a maximum valid address in the array is reached, receiving a plurality of maximum valid addresses, which are recorded. A single relatively highest maximum valid address is determined. A first mode, which prevents BIST testing, is engaged in each array having reached the maximum valid address. A second BIST sequence is initiated based on having received the signal indicating a maximum valid address is reached from all the arrays connected to the common BIST control unit. An address count is decremented from the single relatively highest maximum valid address. The first mode is disengaged for each array as the address count reaches each of the maximum valid addresses during the decrementing.
    Type: Application
    Filed: November 27, 2012
    Publication date: May 29, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: George M. Belansek, Kevin W. Gorman, Kiran K. Narayan, Krishnendu Mondal, Michael R. Ouellette
  • Patent number: 8725938
    Abstract: An apparatus, system, and method are disclosed for testing physical regions in a solid-state storage device. The method includes defining a physical storage region on solid-state storage media of a solid-state storage device. The physical storage region includes a subset of storage capacity of the solid-state storage media. The method includes implementing the physical storage region definition on a storage controller such that memory operations are bounded to the physical storage region. The method includes testing wear of solid-state storage media associated with the physical storage region using memory operations bounded to the physical storage region.
    Type: Grant
    Filed: September 24, 2012
    Date of Patent: May 13, 2014
    Assignee: Fusion-io, Inc.
    Inventors: David Flynn, Jonathan Thatcher, Joshua Aune, Robert Barry Wood
  • Publication number: 20140095949
    Abstract: An area of a memory has a diagnosis area and a non diagnosis area, with the diagnosis area divided into a plurality of Row areas which do not overlap each other, and each of the Row areas is divided into a plurality of Cell areas which do not overlap each other. A memory fault diagnostic method has a diagnostic step in a Row area to diagnose between Cell areas with respect to all the combinations of a set of Cell areas in the Row area, and a diagnostic step between Row areas to diagnose between Row areas with respect to all the combinations of a set of Row areas in the diagnosis area. A Row area size is determined to be a size in which a time of the diagnosis in a Row area becomes equal to a time of the diagnosis between Row areas.
    Type: Application
    Filed: January 30, 2013
    Publication date: April 3, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroshi NAKATANI, Naoya OHNISHI, Satoru AMAKI, Yoshito SAMEDA, Makoto TOKO
  • Patent number: 8645775
    Abstract: A repetitive bit value pattern associated to a predetermined bit position of a sequence of data words, the data words having two or more bits in a bit order, a bit position describing a position within the bit order being indicative of a value represented by the bit at the bit position, can be determined from program loop information, the program loop information having a program expression for determining an updated data word of the sequence of data words. Using the predetermined bit position, a sequence length value associated to the predetermined bit position is determined. The program expression is evaluated for a number of loop iterations indicated by the sequence length value, to obtain updated bit values associated to the predetermined bit position. The repetitive bit value pattern is determined using the updated bit values of the number of loop iterations.
    Type: Grant
    Filed: May 21, 2008
    Date of Patent: February 4, 2014
    Assignee: Advantest (Singapore) Pte Ltd
    Inventors: Jens Dressler, Jens Sundermann
  • Publication number: 20140026006
    Abstract: A method and apparatus for multi-site testing of computer memory devices. An embodiment of a method of testing computer memory devices includes coupling multiple memory devices, each memory device having a serializer output and a deserializer input, wherein the serializer output of a first memory device is coupled with a deserializer input of one or more of the memory devices of the plurality of memory devices. The method further includes producing test signal patterns using a test generator of each memory device, serializing the test signal pattern at each memory device, and transmitting the serialized test pattern for testing of the memory devices, wherein testing of the memory devices includes a first test mode and a second test mode.
    Type: Application
    Filed: September 24, 2013
    Publication date: January 23, 2014
    Applicant: Silicon Image, Inc.
    Inventor: Chinsong Sul
  • Patent number: 8599609
    Abstract: A Flash memory system and a method for data management using the system's sensitivity to charge-disturbing operations and the history of charge-disturbing operations executed by the system are described. In an embodiment of the invention, the sensitivity to charge-disturbing operations is embodied in a disturb-strength matrix in which selected operations have an associated numerical value that is an estimate of the relative strength of that operation to cause disturbances in charge that result in data errors. The disturb-strength matrix should also include the direction of the error which indicates either a gain or loss of charge. The disturb-strength matrix can be determined by the device conducting a self-test in which changes in the measured dispersion value are provoked by executing a selected operation until a detectable change occurs. In alternative embodiments the disturb-strength matrix is determined by testing selected units from a homogeneous population.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: December 3, 2013
    Assignee: HGST Netherlands B.V.
    Inventors: Luiz M. Franca-Neto, Richard Leo Galbraith, Travis Roger Oenning
  • Patent number: 8595573
    Abstract: A method for data storage in a memory including multiple memory cells arranged in blocks, includes storing first and second pages in respective first and second groups of the memory cells within a given block of the memory. A pattern of respective positions of one or more defective memory cells is identified in the first group. The second page is recovered by applying the pattern identified in the first group to the second group of the memory cells.
    Type: Grant
    Filed: February 26, 2012
    Date of Patent: November 26, 2013
    Assignee: Apple Inc.
    Inventors: Ofir Shalvi, Naftali Sommer, Oren Golov
  • Patent number: 8522099
    Abstract: Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure is coupled to the logic chip. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: August 27, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Joe M. Jeddeloh
  • Patent number: 8521986
    Abstract: A method for allocating storage memory space is provided. The method involves receiving a request for storage memory allocation for a file of a current size; estimating a future size of the file, different than the current size of the file, based at least on a particular attribute associated with the file; and causing allocation of storage memory space for storage of the file based on the future size of the file.
    Type: Grant
    Filed: August 11, 2010
    Date of Patent: August 27, 2013
    Assignee: Condusiv Technologies Corporation
    Inventors: Charles E. Beckmann, Richard Cadruvi, Gary Quan, Craig Jensen
  • Patent number: 8510613
    Abstract: A method includes temporarily storing write-data to be written into non-volatile memory cells, respectively, the memory cells being divided into cell groups, performing a first operation including write-phases performed in series and on an associated cell group and including applying a write-voltage to the memory cells belonging to the associated cell group in response to an associated write-data to be written into the memory cells belonging to the cell groups, and performing a second operation after the first operation is completed, which includes read-phases performed in series and on an associated cell group and including applying a first read-voltage to the memory cell or cells belonging to the associated one of the cell groups to produce first read-data therefrom, and comparing the first read-data with the write-data to be written into the memory cells belonging to the associated cell groups to produce comparison data.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: August 13, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Akiyoshi Seko
  • Patent number: 8495439
    Abstract: Exemplary method, system, and computer program embodiments for performing deterministic data verification by a storage controller are provided. Each of a plurality of concurrent write tasks is configured to be placed in a plurality of overlapping data storage ranges by performing at least one of: implementing a data generation function for generating pseudo-random data using a data seed, and generating a range map, the range map utilized as a lookup data structure to verify a chronological order for performing the plurality of concurrent write tasks, wherein a data address space is first designated in the range map as undetermined. Each of a plurality of read tasks is analyzed by comparing data read from a sub range in the plurality of overlapping data storage ranges against the data seed associated with the sub range.
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Yair Gur-Aryeh Chuchem, Adi Goldfarb, Zohar Zilberman
  • Patent number: 8495440
    Abstract: A pseudo random bit stream generator is disclosed which has a fully programmable pseudo random polynomial up to the supported width of the CSRs, fully programmable tap selection for providing any specified combination of generator state taps, and fully programmable parallel sequence generation which determines the number of sequential bits calculated and how much the sequence generator advances per clock.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: July 23, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Glenn A. Dearth
  • Patent number: 8453033
    Abstract: According to one embodiment, a semiconductor memory device includes semiconductor memory chips having writable storage regions in which data is written. The data has one or more pieces of first data, and one or more pieces of the first data includes second data. The device includes a determining unit that determines a prescribed number or fewer of semiconductor memory chips to which the first data is written; a write controller that writes the the first data and redundant information calculated from the second data and used for correcting an error in the second data into the writable storage regions in the determined semiconductor memory chips; and a storage unit that stores identification information and region specifying information associated with each other.
    Type: Grant
    Filed: September 20, 2010
    Date of Patent: May 28, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichiro Yoshii, Kazuhiro Fukutomi, Shinichi Kanno, Shigehiro Asano
  • Publication number: 20130103993
    Abstract: A scan asynchronous memory element includes: an asynchronous memory element configured to receive an n-input; and a scan control logic circuit configured to generate an n-bit signal input and the n-input to the asynchronous memory element from a scan input. The scan control logic circuit outputs the signal input when a control signal supplied to the scan control logic circuit has a first bit pattern, the scan control logic circuit outputs the scan input when the control signal has a second bit pattern, and the scan control logic circuit outputs a bit pattern allowing the asynchronous memory element to hold a previous value when the control signal has a bit pattern other than the first and second bit patterns.
    Type: Application
    Filed: December 14, 2012
    Publication date: April 25, 2013
    Applicant: NATIONAL UNIVERSITY CORPORATION NARA INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventor: National University Corporation Nara Institute Of Science and Technology
  • Patent number: 8427854
    Abstract: Searching for patterns stored on a hardware storage device. A method includes, as part of a memory refresh operation, performing a read to read contents of a portion of a memory. The method further includes writing the read contents of the portion of memory back to the portion of memory. The read contents are provided to data comparison logic. Using the data comparison logic; the read contents are compared to predetermined data patterns. A determination is made as to whether or not the contents match at least one of the predetermined data patterns. When the read contents match at least one of the predetermined data patterns, a software readable indicator is provided indicating that the read contents match at least one of the predetermined data patterns. Similar embodiments may be implemented using hard drive head wear leveling operations.
    Type: Grant
    Filed: April 15, 2010
    Date of Patent: April 23, 2013
    Assignee: Microsoft Corporation
    Inventors: Yaron Weinsberg, John Joseph Richardson
  • Patent number: 8411483
    Abstract: A one time programming (OTP) memory array is divided into a user section and a test section. The cells in the user section and in the test section are configured to form a checkerboard pattern, that is, having repeats of one user cell and one test cell in both column and row directions. Programming the test section and various additional tests are performed to both the user and test sections and other circuitry of the memory array while the user section is not programmed. Even though the OTP user section is not programmed or tested, the provided tests in accordance with embodiments of the invention can provide a very high probability that the OTP memory including the user section is of high quality, i.e., the OTP cells in the user section can be programmed and function appropriately.
    Type: Grant
    Filed: July 9, 2010
    Date of Patent: April 2, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sung-Chieh Lin, Kuoyuan (Peter) Hsu
  • Publication number: 20130055039
    Abstract: A pseudo random bit stream generator is disclosed which has a fully programmable pseudo random polynomial up to the supported width of the CSRs, fully programmable tap selection for providing any specified combination of generator state taps, and fully programmable parallel sequence generation which determines the number of sequential bits calculated and how much the sequence generator advances per clock.
    Type: Application
    Filed: August 30, 2011
    Publication date: February 28, 2013
    Inventor: Glenn A. Dearth
  • Patent number: RE44726
    Abstract: A data inversion register technique for integrated circuit memory testing in which data input signals are selectively inverted in a predetermined pattern to maximize the probability of identifying failures during testing. In accordance with the technique of the present invention, on predetermined input/outputs (I/Os,) data inputs may be inverted to create a desired test pattern (such as data stripes) which are “worst case” for I/O circuitry or column stripes which are “worst case” for memory arrays. A circuit in accordance with the technique of the present invention then matches the pattern for the data out path, inverting the appropriate data outputs to obtain the expected tester data. In this way, the test mode is transparent to any memory tester.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: January 21, 2014
    Assignee: Invensas Corporation
    Inventors: Michael C. Parris, Oscar Frederick Jones, Jr.