Abstract: A memory cell test circuit for use in a semiconductor memory device having a plurality of banks connected to a plurality of global input/output lines, including: a plurality of bank switching units for transferring data outputted from the plurality of banks to the plurality of global input/output lines based on a test mode signal and a plurality of control clock signals; a logic operation unit for performing a logic operation to the data outputted to the plurality of global input/output lines and for outputting a result of the logic operation to a test global input/output line; and a switching unit coupled to the test global input/output line and the plurality of global input/output lines for selectively passing data of the test global input/output line and data of the global input/output lines based on the test mode signal and the plurality of control clock signals.

Abstract: Methods and systems for configuring characteristics associated with at least one portion of a memory array comprising addressable units are provided. In one aspect, a method for controlling a power supply voltage for a memory array comprises detecting whether an error occurred in performing a read operation on an addressable unit of the memory array using a first power supply voltage coupled to the memory array. The method further comprises incrementing an error counter for tracking an error count associated with the memory array and switching the memory array to a second power supply voltage if the error count is equal to or exceeds an error threshold for the memory array. The method further comprises, based on at least one condition, switching the memory array to the first power supply voltage and resetting the error counter to an initial value.

Abstract: A method includes an integrated circuit with a memory. The memory operates with an operating voltage. A value of a minimum operating voltage of the memory is determined. The value of the minimum operating voltage is stored in a non-volatile memory location that maybe a non-volatile register. This minimum operating voltage information can then be used in determining when an alternative power supply voltage may be switched to the memory or ensuring that the minimum voltage is otherwise met. The minimum voltage can be used only internal to the integrated circuit or also provided externally to a user.

Abstract: A semiconductor memory device, having a test mode and a normal mode, includes a frequency multiplier and a test command sequence generator. The frequency multiplier receives a test clock signal in the test mode and generates multiple internal test clock signals, each of which has a frequency equal to a frequency of an operation clock signal in the normal mode. The test clock signal has a frequency lower than the frequency of the operation clock signal. The test command sequence generator generates at least one command signal in response to the internal test clock signals in the test mode. The at least one command signal corresponds to at least one operation timing parameter of the semiconductor memory device that is to be measured. The frequency multiplier may include a Phase Locked Loop (PLL) or a Delay Locked Loop (DLL).

Abstract: Example embodiments relate to a memory test system having a semiconductor memory device, a coupling circuit and a tester. The semiconductor memory device may include a plurality of first output nodes and a plurality of second output nodes. The first output nodes may be connected to respective first on-die termination circuits that may not be tested, and the second output nodes may be connected to second on-die termination circuits that may be tested. The semiconductor memory device may be configured to generate test signals of the second on-die termination circuits and to provide the test signals to the second output nodes. The coupling circuit may be configured to connect the first output nodes and the second output nodes to communication channels, respectively. The tester may be configured to test a logic state of the test signals of the communication channels.

Abstract: A memory combines plural memory cells for storing data wherein the differential stages voltage levels of memory cells are not limited in square value of 2 and can be improved linearly. The feature of the present invention can also increase memory capacity without increasing memory area. Furthermore it can remain voltage levels which cannot express 0 and 1 combination for error erasure messages when data is read. For efficient usage of memory, the increased memory capacity is not only for storing data but also for storing error correction scheme to assure the veracity of the storing data and improve producing yield and reliability for multilevel memory systems.

Abstract: In general, various methods, apparatuses, and systems that generate an augmented repair signature to repair all of the defects detected in a first test of a memory as well as in a second test of the memory.

Abstract: A method of testing and repairing an integrated circuit having a total number of fuses for effecting repair of the integrated circuit. The method including: testing a memory array with a set of tests and reserving a first number of the total number of fuses for use in repairing the memory array based on results of the first set of tests; and shmoo testing the memory array by incrementing, decrementing or incrementing and decrementing values of a test parameter until a minimum or maximum value of the test parameter is reached that utilizes a second number of the total number of fuses for use in repairing the memory array to operate at the minimum or maximum value of the test parameter.

Abstract: Methods (400, 500, and 600) are disclosed for testing a memory device by tailoring an algorithm (460) used in the testing based on the preferred or intrinsic data state 425 that is obtained upon power-up of an advanced technology SRAM memory device (100). The methods (400, 500, and 600) take advantage of the observation that such SRAM devices repeatedly power-up in a preferred state 310. Accordingly, one method 500 comprises powering-up 510 the memory device and reading 520 a preferred power-up data state of each cell of the memory device without memory initialization or writes. The method 500 then captures and stores 530 a data state associated with the preferred power-up data state of each cell 100 and utilizes the stored power-up data state 310 or an inverse of the power-up data state 320 to tailor 540 a test pattern used by the test algorithm 460.

Abstract: A memory hub includes an on-board diagnostic engine through which diagnostic testing and evaluation of the memory system can be performed. The memory hub includes a link interface for receiving memory requests for access to memory devices of the memory system and a memory device interface coupled to the memory devices for coupling memory requests to the memory devices. A memory hub diagnostic engine is coupled through a switch to the link interface and the memory device interface to perform diagnostic testing of the memory system. The diagnostic engine includes a maintenance port that provides access to results of the diagnostic testing and through which diagnostic testing commands can be received.

Abstract: In an apparatus for analyzing a magnetic random access memory (MRAM), and a method of analyzing an MRAM, the apparatus includes an MRAM mounting unit on which an MRAM is mounted, a magnetic field applying unit positioned around the MRAM mounting unit for applying an external magnetic field to the MRAM mounted on the MRAM mounting unit, a cell addressing unit for selecting one of a plurality of unit cells of the MRAM mounted on the MRAM mounting unit, a source measurement unit for applying an internal magnetic field to the selected unit cell of the MRAM or for measuring a resistance of the selected unit cell of the MRAM, and a computer unit for storing and for analyzing data regarding the measured resistance of the each of the plurality of unit cells of the MRAM.

Abstract: A semiconductor device has multilevel memory cells, each cell storing at least three levels of data each. The multilevel memory cells are arranged so as to correspond to a physical address space, each cell storing 2n levels of data each expressed by n (n?2) number of bits (X1, X2, . . . , Xn). A logical address is converted into a physical address of the physical address space. A judgement is made as to whether a logical address space including the logical address matches the physical address space. When matched, the most significant bit X1 is specified by performing a single comparison operation using a reference value. The specified bit is output from one of the cells corresponding to the physical address. If not matched, the bits (X2, . . . , Xn) are specified by performing multiple comparison operations using different reference values.

Abstract: A multi-bit test value is loaded into a built-in latch of the IC component, and a pad of the component is selected for testing. A number of different sequences of test values are automatically generated, based on the stored test value, without scanning-in additional multi-bit values into the latch. A signal that is based on the different sequences of test values is driven into the selected pad and looped back. A difference between the test values and the looped back version of the test values is determined, while automatically adjusting driver and/or receiver characteristics to determine a margin of operation of on-chip I/O buffering for the selected pad.

Abstract: An accelerated test method evaluates, under accelerated conditions (a temperature T2 and a voltage V2), an endurance characteristic of a ferroelectric memory device having a capacitor element including a ferroelectric film under actual operating conditions (a temperature T1 and a voltage V1). An acceleration factor (K) required to evaluate the endurance characteristic is derived by using an expression: logK=A(1/V1?1/V2)+B(1/V1T1?1/V2T2) (where each of A and B is a constant).

Abstract: In the present invention, a computer in which a plurality of programs are executed under a management of an Operation System having a memory management mechanism includes a unit for ensuring atomicity of a first user process without requiring a dedicated CPU instruction. The unit for ensuring atomicity includes a unit for detecting an interrupt by a second user process, a unit for canceling the first user process by utilizing a memory protection function possessed by said Operating System, and a unit for executing an operation of the first user process again.

Abstract: It is possible to read out data in accordance with a read-out address from memory cells via bit lines and primary sense amplifiers. Each secondary sense amplifier is assigned a group of primary sense amplifiers. It is possible for the primary sense amplifiers of a group to be connected to one of the secondary sense amplifiers in each case via switching devices in order to apply the datum from one of the primary sense amplifiers to the assigned secondary sense amplifier via the switching device selected by the read-out address. For reading out data, a test control unit is provided to connect some of the switching devices in parallel depending on a test mode signal and depending on a read-out address, so that in each case one of the group of primary sense amplifiers is connected to the assigned secondary sense amplifiers.

Abstract: A method for optimizing a source synchronous clock reference signal timing to capture data from a memory device (e.g., DDR SDRAM) includes conducting an iterative two-dimensional data eye search for optimizing the delay of the source synchronous clock reference signal (e.g., DQS). Embodiments of the present invention are directed to tuning the delay for each device for the optimal margin in two dimensions: maximize the distance from the data eye walls and maximize the noise margin on the interface. An iterative data eye search is performed while varying the DQS delay timing and noise margin.

Abstract: Potential of a word line connected to any selected one of memory cells is lowered and potential of word lines connected to non-selected memory cells are raised. The potential of the plate line is raised and lowered. The potential of the bit line is raised and lowered. After this, reading data from the memory cells after potential raising and lowering of the plate line and potential raising and lowering of the bit line have been alternately performed at least one time, thereby to determine attenuation of polarization in the ferroelectric capacitor.

Abstract: Method and apparatus are disclosed for checking the resistance of antifuse elements in an integrated circuit. A voltage based on the resistance of an antifuse element is compared to a voltage based on a known resistance, and an output signal is generated whose binary value indicates whether the resistance of the antifuse element is higher or lower than the known value of resistance. The method and apparatus are useful in verifying the programming of antifuse elements.

Abstract: A self-aligning memory cell design is provided to allow testing of transistors in every cell of a memory circuit. A test array of these cells is fabricated with contact pads in each cell for specific components in the cell. Then, metal lines are provided to couple the contact pads in the test array. The whole test array is then probed via these metal lines. Tests may then be performed to detect random and systematic transistor degradation electrically for all cells in the circuit. Different components in the memory design may be tested by providing contact pads for the components of interest and providing metal lines coupling the contact pads.

Abstract: A method is described for parametrizing an integrated circuit by applying a digital start command signal followed by a parametrization data signal to the supply voltage terminal and/or the output terminal of the integrated circuit. During the parametrization process, the voltage level applied to the supply voltage terminal and/or the output terminal is kept above the normal operating voltage level and detected by a detector device provided in integrated circuit. The integrated circuit includes the supply voltage terminal, a reference potential terminal, and the output terminal, as well as an internal memory which is preferably non-volatile. The adjustment specification for parametrizing the integrated circuit is stored in the memory and activated by the parametrization data signal.

Abstract: Embodiments of the present invention are illustrated in a random access memory. In one embodiment, the random access memory includes memory banks and precharge timers configured to provide precharge signals to the memory banks. Each of the precharge timers corresponds to one of the memory banks and each of the precharge timers is configured to provide one of the precharge signals to the corresponding one of the memory banks in normal mode and in test mode.

Abstract: A system and method are provided for non-causal channel equalization in a communications system. The method comprises: receiving a non-return to zero (NRZ) data stream input; establishing thresholds to distinguish a first bit estimate; comparing the first bit estimate in the NRZ data stream to a second bit value received prior to the first bit, and a third bit received subsequent to the first bit; in response to the comparisons, determining the value of the first bit; tracking the NRZ data stream inputs in response to sequential bit value combinations; maintaining long-term averages of the tracked NRZ data stream inputs; adjusting the thresholds in response to the long-term averages; and, offsetting the threshold adjustments to account for the asymmetric noise distribution. Two methods are used to offset the threshold adjustments to account for the asymmetric noise distribution: forward error correction (FEC) decoding and tracking the ratio of bit values.

Abstract: A terminating circuit for terminating a common data bus to a predetermined voltage level is inactivated in a test mode, a level detection circuit detects a potential of an internal test data bus line coupled to the common data bus line, and an output state of a ternary output circuit is controlled in accordance with a detection result. In a semiconductor integrated circuit device including the memory integrated together with a logic on a common semiconductor substrate, it is accurately determined whether the output state of the memory is a ternary state while operating the memory under actual operation conditions.

Abstract: A method for protecting a security module includes the steps of monitoring proper insertion of the module on a device motherboard with first, second and third function units, erasing sensitive data due to an improper use or a replacement of the module with the second function unit, inhibiting the functionality of the module with the third function unit during a replacement of the security module, re-initializing the previously erased, sensitive data following proper use or replacement of the security module, and re-commissioning by enabling the function units of the security module. An arrangement implementation of the method has an unplugged status detection unit that has a circuit for resettable self-holding of a status indicator, the self-holding being triggered when the voltage level on a test voltage line deviates from a predetermined potential. A processor connected to the other function units and is programmed to identify and modify the status of the security module.

Abstract: A multiple-way cache memory having a plurality of cache blocks and associated tag arrays includes a select circuit that stores way select values for each cache block. The way select values selectively disable one or more cache blocks from participating in cache operations by forcing tag comparisons associated with the disabled cache blocks to a mismatch condition so that the disabled cache blocks will not be selected to provide output data. The remaining enabled cache blocks may be operated as a less-associative cache memory without requiring cache addressing modifications.

Abstract: The present invention provides a method, system and apparatus for providing failsafe detection for a differential receiver. A bus activity signal (11) is activated when receiving a differential data signal of sufficient amplitude to transition through a predetermined threshold. A failsafe signal (620) indicates a low differential voltage condition. A countdown time period commences (85) upon activation of either signal, and a failsafe condition is determined (89) to exist if the failsafe signal is active (87) when the countdown time period expires (86).

Abstract: A wiring fault detection, diagnostic and reporting technique enables linking devices within a process control system to measure the electrical characteristics of a segment protocol bus and the electrical characteristics of the signals transmitted via the protocol bus. The technique connects a signal line of a segment protocol bus to one of a plurality of measurement blocks within a wiring fault detection unit. The one of the plurality of measurement blocks measures an electrical characteristic associated with the segment protocol bus and sends the measured electrical characteristic to a wiring fault diagnostic manager. The wiring fault diagnostic manager analyzes the measured electrical characteristic to determine a type of the wiring fault and reports the type of the wiring fault via a user interface.

Abstract: A memory control circuit is connected between a CPU and a memory. The memory control circuit comprises an access control circuit for controlling reading/writing access speed between the CPU and the memory. The memory control circuit further comprises a speed measurement circuit for writing predetermined data into a given address of the memory at a first speed when a speed measurement mode is specified. Thereafter the speed measurement circuit reads out the data from the given address of the memory at a second speed hat is different from the first speed. Finally, the speed measurement circuit measures an optimum speed ensuring a normal reading operation.

Abstract: A method for testing semiconductor chips, in particular semiconductor memory chips, is described. In which, in a chip to be tested, at least one test mode is set, the test mode is executed in the chip and test results are output from the chip. It is provided that, after the setting and before the performance of the test mode, a check mode is executed in which the status of the test mode set in the chip is read out in a defined format.

Abstract: A method and apparatus for initializing dynamic random access memory (DRAM) devices is provided wherein a channel is levelized by determining the response time of each of a number of DRAM devices coupled to a bus. Determining the response time for a DRAM device comprises writing logic ones to a memory location of the DRAM device using the bus. Subsequently, a read command is issued over the bus, wherein the read command is addressed to the newly-written memory location of the DRAM device. The memory controller then measures the elapsed time between the issuance of the read command and the receipt of the logic ones from the DRAM device, and this elapsed time is the response time of the DRAM device. Following the determination of a response time for each DRAM device, and using the longest response time, a delay is computed for each of the DRAM devices coupled to the bus so that the response time, in clock cycles, of each of the DRAM devices coupled to the bus equals the longest response time.

Abstract: The number of failure bits is counted with respect to each row and each column in a fail bit map (9), to find respective average numbers of failure bits with respect to rows and columns. One-half of the average number of failure bits of rows is defined as a threshold value of rows, and one-half of the average number of failure bits of columns is defined as a threshold value of columns. Thereafter, on the basis of the respective threshold values of rows and columns, the number of failure bits is converted to digital form with respect to each row and each column. The respective average values of the digitized numbers of failure bits with respect to rows and columns are calculated, which are respectively referred to as average values of rows and columns. It is determined that a semiconductor device contains a block failure in a row direction, a block failure in a column direction, or a random block failure.

Abstract: Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its originally intended level. The error is initially not readily detected during normal read until the cumulative drift becomes so severe that it develops into a hard error. Data could be lost if enough of these hard errors swamps available error correction codes in the memory. A memory device and techniques therefor are capable of detecting these drifts and substantially maintaining the threshold voltage of each memory cell to its intended level throughout the use of the memory device, thereby resisting the development of soft errors into hard errors.

Abstract: An individual-well adaptive method of body bias control that mitigates the effects of D2D and WD process variations is shown. It is assumed that p-type transistors are grouped in sections. The bodies of all the p-type transistors within a section are connected to a single n-well. This section size can be small enough to provide fine-granular adjustments to the circuit without having any impact on area overhead. With a small amount of additional circuitry and routing, individual well biases can be intelligently adjusted resulting in closely controlled chip power and performance. Experimental results show that binning yields as low as 17% can be improved to greater than 90% using the proposed method.

Abstract: An error detection structure is proposed for a multilevel memory device including a plurality of memory cells each one being programmable at more than two levels ordered in a sequence, each level representing a logic value consisting of a plurality of digits, wherein the structure includes means for detecting errors in the values of a selected block of memory cells; the structure further includes means for partitioning the digits of each memory cell of the block into a first subset and a second subset, the digits of the first subset being unchanged in the values of a first and a second ending range in the sequence, the means for detecting errors only operating on the digits of the second subset of the block.

Abstract: A method and an apparatus for testing an SDRAM are described. The SDRAM is used as a main memory in the PC, and an additional circuit configuration is accommodated on a plug-in board and has an additional memory in the form of an SRAM and logic circuits. The method according to the invention allows the SDRAM to be tested in a module bank in the running PC to be set deliberately to a test mode. In this case the code for test mode activation is modified by a high-level language program (PASCAL) in accordance with the user requirements, is copied to the additional memory on the plug-in board, and is then called by the high-level language program using MS DOS. After activation of the selected test mode by a code programmed in Assembler, a defined jump is made back to the calling program once again. This allows the use of the test mode provided in the SDRAM in standard PCs and using standard operating systems. This greatly increases the test options for SDRAMs on standard PCs.

Abstract: An apparatus for verifying the data retention in a non-volatile memory is described which comprises at least one multiplexer and at least one shift register. The multiplexer and the at least one shift register are disposed so that the data of the non-volatile memory are in input to the multiplexer the output of which is in turn in input to the at least one shift register. The apparatus comprises a logical circuitry which by suitable commands controls the data transfer from said multiplexer to said at least one shift register, the data loading and the output data shifting in said at least one shift register.

Abstract: In a first aspect, a method of operating a disk drive includes detecting a trigger event during non-idle operation of the disk drive, and responding to the detected trigger event by performing a predictive failure analysis with respect to the disk drive. According to a second aspect, a method of operating a disk drive includes performing a predictive failure analysis with respect to the disk drive at a regular time interval, detecting a trigger event during non-idle operation of the disk drive, and responding to the detected trigger event by reducing the regular time interval at which the predictive failure analysis is performed. Numerous other aspects are provided.

Abstract: One embodiment of the present invention provides a system that facilitates fully characterizing propagation delay through an n-input circuit. The system operates by first receiving the n-input circuit. Next, the system establishes programmable voltage sources at each input of the n-input circuit. The system then programs each programmable voltage source to provide a sequence of input patterns to the n-input circuit. This sequence includes the 22n possible transitions between all possible pairs of input patterns. Next, the system measures the propagation delay between the input and the output of the n-input circuit for each transition in the sequence of input patterns and then reports the results.

Abstract: A plurality of processors in a data processing system share a common memory through which they communicate and share resources. When sharing resources, one processor needs to wait for another processor to modify a specified location in memory, such as unlocking a lock. Memory and bus traffic are minimized during this waiting by first reading and testing the memory location. Then, the memory location is not read and tested again until the local copy of the cache line containing that memory location is invalidated by another processor. This feature is utilized both for a Lock instruction and a Wait for Change instruction, both of which utilize a timer parameter for specifying a maximum number of cycles to wait for another processor to modify the specified location in memory.

Abstract: An embodiment of the invention is circuitry 25 that contains a programmable delay 8 and a pulse generator 16 that send clock signals of a certain frequency to a device under test 1. The programmable delay 8 increases the frequency of the clock signal to the device under test 1 until the device under test fails. The cycle time measurement of the device under test 1 is the period of maximum frequency at which the device under test 1 operates properly.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells, and has a package configuration that is compatible with an SDRAM. The memory device includes a memory array, a programmable register circuitry to store protection data, and a voltage detector to determine if a memory power supply voltage drops below a predetermined level. Control circuitry is provided to program the register circuitry and prevent erase or write operations to the memory array in response to the voltage detector. In operation, the memory monitors a power supply voltage coupled to the memory, and prohibits write or erase operations from being performed if the supply voltage drops below a predetermined value.

Abstract: The present invention relates to a method and apparatus for reducing data errors in a magneto-resistive random access memory (MRAM). According to the disclosed method, data bits and associated error correction code (ECC) check bits are stored into a storage area. Thereafter, the data bits and ECC check bits are read out and any errors are detected and corrected. A data refresh is then initiated based on a count and data bits and associated ECC check bits stored in the storage area are then refreshed by accessing the stored data bits and the associated ECC check bits, and ultimately by checking, correcting and restoring the data bits and the ECC check bits to the storage area.

Abstract: A head testing apparatus is provided for testing an output of a magnetic data recording head. The apparatus includes first and second tester input terminals for coupling to the head, first and second input stages and an AC-coupled differential amplifier. The first input stage has a first buffer input, which is coupled to the first tester input terminal, a first buffer output and a plurality of parallel-connected buffer amplifiers coupled between the first buffer input and the first buffer output. The second input stage has a second buffer input, which is coupled to the second tester input terminal, a second buffer output and a plurality of parallel-connected buffer amplifiers coupled between the second buffer input and the second buffer output. The AC-coupled differential amplifier has first and second amplefier inputs coupled to the first and second buffer outputs through first and second capacitors, respectively, and has a measurement output.

Abstract: Disclosed is a device that includes a built-in-self-test controller having a mechanism for providing an interface signal that indicates whether a dynamic voltage screen (DVS) test is being performed. The self-test controller is associated with a memory array that includes a clock having a clock speed. The memory array also includes a clock adjuster that receives the interface signal and reduces the clock speed when the interface signal indicates that a DVS test is being performed.

Abstract: A system that adapts wireless link parameters for a wireless communication link. A measure is determined of errors occurring in communication over a wireless link. In a case that the measure of errors corresponds to more errors than a first predetermined threshold, communication changes from a first set of wireless link parameters to a second set of wireless link parameters. The second set of wireless link parameters corresponds to higher error tolerance than the first set of wireless link parameters. In a case that the measure of errors corresponds to fewer errors than a second predetermined threshold, communication changes from the first set of wireless link parameters to a third set of wireless link parameters. The third set of wireless link parameters corresponds to lower error tolerance than the first set of wireless link parameters. Preferably, the measure of errors is determined by monitoring a number of NACK messages and a number of ACK messages that occur.

Abstract: In a threshold analysis method obtaining threshold voltages of all bits in a flash memory through single processing, fail bit map information is examined in order from a smaller voltage applied to the flash memory. As to a bit exhibiting a value, read from the flash memory, first mismatching a determination value, the threshold voltage is settled on the basis of a voltage applied when the bit fails in reading.

Abstract: According to one embodiment, a method of conducting a switching state (AC) loop back test at a buffer circuit comprises varying the relationship between the generation of strobe signals at a strobe input/output (I/O) circuit of a first group of I/O circuits and the reception of data at the first group of I/O circuits receiving the strobe signals fails, and comparing the time at which the first I/O circuit fails with a predetermined timing performance for the first group of I/O circuits. Subsequently, it is determined whether the first group of I/O circuits satisfies the predetermined timing performance.

Abstract: A method for testing and safeguarding the availability of a networked system which is assigned to a system carrier, wherein a multiplicity of subscribers exchange data via a bus-type network which is comprised of one or more bus lines. Specific voltage levels are applied to the bus line or the lines by the appropriate subscribers. By virtue of this, as a minimum, at least individual subscribers transmit data. The bus line or the lines is/are monitored by the at least one receiving subscriber for an overshoot or undershoot of voltage levels. Due to this, the data is evaluated in at least one receiving subscriber with the aid of voltage levels. During operation of the system, signals present on the bus-type network are discriminated, tested or measured with respect to at least one signal criterion by individual subscribers under conditions defined in a network-wide manner for all subscribers.

Abstract: A collection of testing circuits are disclosed which can be used to form a comprehensive built-in test system for MRAM arrays. The combination of testing circuits can detect MRAM array defects including: open rows, shorted memory cells, memory cells which are outside of resistance specifications, and simple read/write pattern errors. The built-in test circuits include a wired-OR circuit connecting all the rows to test for open rows and shorted memory cells. A dynamic sense circuit detects whether the resistance of memory cells is within specified limits. An exclusive-OR gate combined with global write controls is integrated into the sense amplifiers and is used to perform simple read-write pattern tests. Error data from the margin tests and the read-write tests are reported through a second wired-OR circuit. Outputs from the two wired-OR circuits and the associated row addresses are reported to the test processor or recorded into an on-chip error status table.