Abstract: An automatic test apparatus for assuring quality and reliability of semiconductor integrated circuit devices comprising a computerized tester controller performing virtual timing, formatting, and pattern generation for testing said devices; and a test head controlled by the controller, comprising pin electronics, dc subsystem, and support for self-testing built into the circuit. The computerized tester controller comprises pattern sequence control, pattern memory, scan memory, timing system and driver signal formatter, thereby executing virtually high speed functional tests based on test patterns, combined with ac parametric tests of said devices. Furthermore, the computerized tester controller dynamically transforms data stored in the computer into instructions for the test head and into pattern sequence matched to the digital function stimulus and response required by the design of the devices.

Abstract: A magnetic field is applied to a defective semiconductor device to be tested. A current is applied from a power supply to a wiring of the semiconductor device. At this time, a stress occurs to the wiring of the semiconductor device. A stress detector detects the stress and creates a first stress image. Next, a same magnetic field and a same current are applied to a good semiconductor device same in type and a stress is detected. By doing so, a second stress image as a comparison stress image is created. Next, a difference image between the first and second stress images is created by an image processor. As a result, only a stress resulting from a leak current is extracted. Next, the difference image is compared with a wiring pattern image of the semiconductor device to thereby specify a leakage portion.

Abstract: An array threshold voltage test mode for a flash memory device is disclosed. During the test mode, a test voltage is routed directly to the gates of the flash memory transistors selected by a given address. If the test voltage causes the selected transistors to change state by crossing their threshold voltage level, the change will be reflected in the data outputs of the device. By varying the test voltages and the addresses and monitoring the data outputs, the array threshold voltage distribution can be determined for the entire device.

Abstract: A method of determining a redundancy solution for a semiconductor memory under test (DUT) having redundant rows and columns is disclosed. The method includes the steps of first testing the DUT in a first environment with a first tester to generate a first fail data set. The first fail data set is then transferred to a second tester where the DUT is test in a second environment to generate a second fail data set. The first and second failure data sets are then merged to create a merged fail data set. A highly optimized redundancy solution is then determined based on the merged fail data set.

Abstract: A method and system for determining degradation of the tape drive and the tape in a multichannel recording system provides refined definition of correction for data recording statistics. The method and system generate a count signal indicative of the number of data blocks read from multi-track tape having more than a predetermined threshold of data bytes in error. The method and system generate a degradation signal indicative of tape drive and tape degradation if the ratio of corrected data blocks versus the total number of data blocks read from the tape is above a predetermined ratio. The degradation signal is indicative of tape drive degradation if the ratio of data blocks having more than the predetermined number of error data bytes along a single track versus the total number of data blocks read from the tape is above a predetermined ratio.

Abstract: A memory device is described which includes a latch circuit for latching a normally externally provided signal during a test mode. The input pin which is normally enabled to receive the external signal is re-routed to provide an external reference voltage, Vref, to internal circuitry. During testing operations the external Vref signal is used. Once an integrated circuit is determined to be good, an internal generator circuit is set to provide Vref. The integrated circuit can be a flash memory device, and the input pin can be a BYTE command pin. This method of substituting the source of Vref eliminates time required to set the internal generator circuit in defective memory devices.

Abstract: A memory testing apparatus is provided, which can test in short time a memory having a block function like a flash memory. In addition to a failure analysis memory AFM capable of storing failures of all bits of a memory under test MUT, are provided a first bad block memory BBM and a second bad block memory CFM each having its storage capacity corresponding to the number of blocks that the memory under test has. The results of an initial test are stored in the first bad block memory. Utilizing the results of the initial test as mask data, bad blocks which have been determined to be failure in the initial test are masked by the mask data, respectively, so that a functional test for the bad blocks are omitted and the functional test for only pass blocks is performed. The results of the functional test are stored in the second bad block memory, and only the blocks having their bad block data stored in the second bad block memory are determined as to whether they are repairable or not.

Abstract: A system is described for providing pulses to test a semiconductor device, such as a memory device. The system includes several voltage sources, each voltage source being coupled to an output terminal through a pass gate. A control logic circuit provides a control signal to each of the pass gates to render the pass gates conductive in a sequence. A voltage generated by each voltage source is coupled to the output terminal in a sequence to generate a series of pulses at the output terminal. Each of the voltage sources may be a programmable digital-to-analog converter receiving a voltage control signal and generating a voltage based on the voltage control signal.

Abstract: A memory module test system with reduced driver output impedance. A test system includes a plurality of driver circuits, each of which is coupled to a transmission line on a loadboard. The loadboard includes a socket for insertion of the memory module to be tested. A test signal is generated and driven onto a transmission line by a driver circuit. A duplicate test signal is driven by a separate driver circuit onto a separate transmission line. The transmission lines carrying the test signal and duplicate test signal are electrically shorted on the loadboard. Electrically shorting these transmission lines effectively reduces their impedance by half. Multiple test signals generated by the test system are shorted in this manner in order to allow the electrical environment of the test system to more closely approximate that of the application environment of the tested memory module.

Abstract: A method for identifying intercell defects in a memory device activates a plurality of spaced-apart rows simultaneously. Each of the rows includes cells that are written to logic states corresponding to high voltages. Cells in rows adjacent to the activated rows are written to logic states corresponding to low voltages. After the rows are activated, a testing interval passes to allow charge from cells of the activated rows to leak to adjacent cells through any stringers or other defects. In a device according to the invention, a variable voltage level circuit is incorporated in a precharge and equalization circuit to allow both inverting and non-inverting digit lines of the memory array to be set at the same voltage levels. Because the inverting and non-inverting digit lines are held at the same voltage levels, the number of word lines that can be activated for testing is increased, thereby reducing the overall time for testing.

Abstract: A semiconductor integrated circuit device, which has an internal circuit that operates during a normal operation on the basis of a reference signal and input signals supplied from the outside of the device. A detecting circuit detects the voltage level of the reference signal. When the detecting circuit has detected that the reference signal is at a predetermined voltage level that differs from a voltage level assumed during the normal operation, a transfer circuit transfers an internal signal in the internal circuit to the outside of the device, instead of the regular output signal of the internal circuit.

Abstract: A method of testing a computer system includes the steps of partitioning a physically formatted hard disk to define a whole region of the hard disk as a first partition region and a part of the first partition region as a second partition region, setting the second partition region as a boot driver, installing a test program file in the second partition region to form an original hard disk, testing the computer system using the test program file in the second partition region, erasing the second partition region overlapped with part of the first partition region, and setting the first partition region as a boot driver region. To substantially test the computer system, the program files which are installed on the first and second partition regions of the original hard disk are duplicated on other hard disks with a disk duplicating apparatus. The hard disks thus duplicated are established in computer systems, respectively.

Abstract: The present invention provides a memory refresh structure having a memory array and two clock generators. The memory array has a plurality of cells grouped into original segments. The two clock generators generate two clock signals, CLK0 and CLK1. CLK0 takes responsibility for the refresh operations of the cells in the original segments to meet an original refresh time. A portion of the original segments that having at least one cell whose retention time is longer than the original refresh time are defined as first segments. CLK1 takes responsibility for the refresh operations of the cells in the first segments to make the refreshed cell meet a first refresh time shorter than the original refresh time.

Abstract: A voltage regulator is disclosed which is coupled with a programmable trimming circuit by a trim test circuit. When disabled, the trim test circuit passes the logic states of the signals produced by the trimming circuit to the voltage regulator. When enabled, the trim test circuit applies signals to the voltage regulator which correspond with asserted logic states of signals producible by the trimming circuit. Thus, the effect of the trimming circuit on the voltage regulator is testable without actual programming of the trimming circuit.

Abstract: A plurality of testing units, each of which is applied to an input or output terminal of a device under test, are provided. An input pattern is supplied to a first testing unit that is applied to an input terminal, while expected patterns are supplied to second and third testing units that are applied to first and second output terminals, respectively. These testing units are operated in synchronism with a common clock signal. The second testing unit, which has received the expected pattern, communicates an evaluative result, indicating a point in time when the logical level of a voltage signal appearing at the first output terminal of the device under test matches with the expected pattern, to the third testing unit. And the third testing unit performs timing and functional tests on a signal appearing at the second output terminal with reference to this evaluative result.

Abstract: A detection circuit and a test mode circuit incorporating the detection circuit is disclosed. The detection circuit includes an N-channel transistor having a first source, a first gate, and a first drain, wherein the first drain is connected to a supply voltage. The detection circuit also includes a P-channel transistor having a second source, a second gate, and a second drain, wherein the second source is connected to the first source and the second drain provides an output signal indicative of a supervoltage being applied to the first gate. The test mode circuit also includes a memory access cycle time-out feature override circuit.

Abstract: In order, in the case of a programmable logic controller having a modular structure, to be able to insert and withdraw assemblies even in the course of operation, without disturbing the data traffic taking place via the bus of the programmable logic controller, provision is made for arranging an evaluation circuit in a bus access circuit. The evaluation circuit controls a variable resistor, which is arranged in one of the supply lines for the assemble, to have a low resistance if the assembly is connected to the bus and to have a high resistance again if a potential present at a test input of the evaluation circuit lies outside a predetermined value range after a run-up time has elapsed.

Abstract: A step-down circuit 10A comprises a voltage follower circuit 20A for receiving a voltage VG, to be measured, of an internal circuit, activated in response to activation of a test mode signal TM, and providing its output to an on-chip pad 16A. Although a large current flows through an output buffer circuit 22 of the voltage follower circuit 20A compared with that of an output buffer circuit 15 of a voltage control circuit 12, this large current does not flow when the signal TM is inactive. The voltage follower circuit having a comparatively large area on chip can commonly be used with a selection circuit for selecting one of nodes with voltages to be measured. In a case of SDRAM, the signal TM may be an output of the command decoder and a selection control signal may be an address signal.

Abstract: A Defect Leakage Screen Test apparatus and method is introduced to eliminate or reduce steps in the failure analysis process of memory devices, such as DRAM cells, or to eliminate the necessity for the application of a physical failure analysis on the memory device. Special single bit failures due to leakage current, junction current, or threshold leakage current, are characterized by varying the p-well voltage of the memory device during the read operation of the test. The p-well voltage is varied with a test code Initial Program Load (IPL). Additional logic is provided on the memory IC to decode the IPL logic signals. In order to perform the p-well varying test, the memory device is provided with the following: IPL decoding logic; a reference voltage generator; an IPL voltage reference multiplexor; a p-well voltage feed-back circuit; and a differential amplifier circuit.

Abstract: In a semiconductor memory capable of verifying data stored therein, a verification pass signal output from a verification circuit is input to a control signal output circuit. In the case of a normal mode operation of the control signal output circuit, a signal having a voltage level corresponding to that of the verification pass signal is output therefrom. In the case of a test mode operation of the control signal output circuit, a signal having a given voltage level regardless of voltage level of the verification pass signal is output therefrom. In cases where the signal having the given voltage level is output from the control signal output circuit, a write control circuit and a write counter execute a preset maximum number of program processings and verifications processing.

Abstract: A BIST controller (112) and methodology uses the DRAM controller (108) refresh signals to test the data retention characteristics of a DRAM memory array (132). The BIST controller blocks a fraction of the refresh cycles generated by the DRAM controller to provide a margin of confidence above the DRAM's specified retention time. The BIST controller is especially suited to embedded applications in which access to the memory is indirect and to applications in which the memory system is modular. The invention may also be used to characterize the actual retention time of a particular DRAM allowing the system to optimize the DRAM's refresh interval.

Abstract: A circuit for parametric testing of I/O's including bidirectionals includes logic which ties the I/O's into a single test chain. A pulse is applied moved down the chain to test the switching levels of the input buffers and the output buffers. The circuit features the ability to program the bidirectionals as either inputs (test mode 1) or outputs (test mode 2) and so allows for its input and output buffers to be tested. The test mode can be selected simply by writing to an externally accessed data register.

Abstract: A circuit for measuring the access time of a memory circuit. The circuit includes a storage element 908 having an input terminal, an output terminal, and a clock terminal. The input terminal of the storage element is coupled to an output of the memory circuit 900. A clock signal source 906 is coupled to the clock terminal of the storage element and to a clock terminal of the memory circuit. The circuit also includes test circuitry 902 coupled to address and control terminals of the memory circuit and to the output terminal of the storage element. The test circuitry is operable to store or generate a test data pattern and compare the pattern to data output from the storage element. In one embodiment, the storage element is a data latch comprising a clock-enabled inverter serially coupled with a flip-flop. The flip-flop in one embodiment is a cross-coupled inverter storage cell or “keeper”.

Abstract: An IC testing system is provided with comparator circuits for comparing at two types of voltage levels, with respect to an output signal of a device to be measured, a memory for storing the state of window strobe of each test cycle, based on test control signals for strobe decisions, control signal generating circuits for generating control signals related to the generation of window strobes, based on the state stored in the aforementioned memory, and a signal decision circuit generating strobe signals which have been timing-corrected, in response to the voltage levels for window strobe decisions for producing window strobes, based on the control signals from the aforementioned control signal generating circuit and the aforementioned test control signals, and window strobes for performing window strobe decisions with respect to signals from the aforementioned comparator circuits.

Abstract: Method and apparatus for predicting future failure of a disc drive head from degradation in a head readback response characteristic, such as electrical resistance, readback signal amplitude, asymmetry or nonlinearity. During manufacturing, the disc drive determines and store a baseline level for a selected readback response characteristic of the head indicative of head performance as data are read back from a disc. During subsequent data processing use, the disc drive subsequently periodically determines a subsequent level for the readback response characteristic of the head. The possibility of a future failure of the drive is next predicted in relation to a difference between the baseline level and the subsequent level for the readback response characteristic of the head. An indication of the possibility of the future failure is provided to allow a host device to reallocate data stored on the disc before the failure of the head.

Abstract: Integrated circuit memory devices include a stress voltage generator that generates a stress voltage that is higher than the internal supply voltage of the integrated circuit memory device and that applies the stress voltage to the memory cell array during the stress BIST of the memory cell array. The stress voltage generator is preferably responsive to a BIST request signal and to a stress test signal that are applied from external of the integrated circuit memory device, to apply the stress voltage to the memory cell array and to perform a BIST of the memory cell array. The stress voltage generator is responsive to the BIST request signal and absence of the stress test signal, to apply the internal supply voltage to the memory cell array and to perform a BIST of the memory cell array. Accordingly, circuits within the integrated circuit memory device can be responsive to external test signals to generate stress voltages during BIST.

Abstract: Disclosed is a method of executing test programs for a semiconductor testing system performing function tests on a semiconductor device through the execution of the test programs by means of an operating system. When a statement of a test program for designating a predetermined set value is executed, the set value is stored in a data area. Then, when a statement on the execution of a function test is executed, the above set value is read to set a corresponding circuit, after which the function tests are carried out.

Abstract: In order, in the case of a programmable logic controller having a modular structure, to be able to insert and withdraw assemblies even in the course of operation, without disturbing the data traffic taking place via the bus of the programmable logic controller, provision is made for arranging an evaluation circuit in a bus segment or a bus access circuit. The evaluation circuit establishes whether an assembly is connected to the bus and accordingly controls a variable resistor, which is arranged in one of the supply lines for the assembly, to have a high resistance or a low resistance.

Abstract: Method and apparatus are disclosed for checking the resistance of antifuse elements in an integrated circuit. A voltage based on the resistance of an antifuse element is compared to a voltage based on a known resistance, and an output signal is generated whose binary value indicates whether the resistance of the antifuse element is higher or lower than the known value of resistance. The method and apparatus are useful in verifying the programming of antifuse elements.

Abstract: An IC tester enabling the performance of the decision of the conditions of output signals of the device under test in a period of time having a predetermined time interval between two decision trigger signals, thereby providing the IC tester capable of deciding the conditions of output signals of the device under test in a scope wider than that of the conventional IC tester. If the output voltage of each device under test is higher than a high reference voltage, it is decided that each device under test outputs a high signal while if the output voltage of the each device under test is lower than a low reference voltage, it is decided that each device under test outputs a low signal. If the output voltage of each device under test is lower than the high reference voltage but higher than the low reference voltage, it is decided that the output of each device under test is in high impedance.

Abstract: A system is described for providing pulses to test a semiconductor device, such as a memory device. The system includes several voltage sources, each voltage source being coupled to an output terminal through a pass gate. A control logic circuit provides a control signal to each of the pass gates to render the pass gates conductive in a sequence. A voltage generated by each voltage source is coupled to the output terminal in a sequence to generate a series of pulses at the output terminal. Each of the voltage sources may be a programmable digital-to-analog converter receiving a voltage control signal and generating a voltage based on the voltage control signal.

Abstract: A method and apparatus for reducing the time for determining a memory refresh frequency for a dynamic random access memory. The method includes disabling the bootstrap circuitry associated with a word line when writing data into a memory cell during a test operation. For instances in which data representing a high logic level is written into the memory cell, the resulting charge that is stored is less than the stored charge under normal operation of the dynamic memory. Consequently, the decay time for the stored charge is shortened, thereby shortening the time for testing the refresh frequency of the memory cell. Testing time for the dynamic memory is thus reduced.

Abstract: A memory-test-mode detection circuit for an integrated circuit uses one or more of the input pins of an integrated circuit to detect at least one non-standard signal level. To avoid false triggering several other non-standard logic levels can also be used with some of the other input pins. Each of the non-standard signal levels are detected by a separate signal level detection circuit. A predetermined combination of input signals then provides a control signal which sets the integrated-circuit into a predetermined test mode. A non-standard Vcc/2 signal level is detected by determining that it is above a predetermined low threshold level of 1/4 Vcc and below a predetermined high threshold level of 3/4 Vcc. Additional non-standard input signal levels which are close to Vcc and Vss are also used. A chip enable (CEX) signal is used to enable the signal level detection circuit when a chip is enabled.

Abstract: A memory device is described which includes a latch circuit for latching a normally externally provided signal during a test mode. The input pin which is normally enabled to receive the external signal is re-routed to provide an external reference voltage, Vref, to internal circuitry. During testing operations the external Vref signal is used. Once an integrated circuit is determined to be good, an internal generator circuit is set to provide Vref. The integrated circuit can be a flash memory device, and the input pin can be a BYTE command pin. This method of substituting the source of Vref eliminates time required to set the internal generator circuit in defective memory devices.

Abstract: A circuit and method are provided for stress-testing EEPROMS by incrementally selecting and deselecting word lines. The circuit of the invention comprises a memory cell array, a set of decoders for decoding a memory address bus and controlling word lines for the memory cell array, a control circuit, and a shift register driven by the control circuit. Each bit of the shift register has the capability of overriding a group of one or more of the decoders. When the initiation signal is received by the control circuit, a state control bit is set high and is clocked through the shift register. The high bit overrides successive groups of decoders as it is shifted through the shift register, until all word lines in the memory cell array are selected. After the stress test has been performed, the state control bit is returned to zero and is cycled through the shift register on successive clock cycles, incrementally deselecting groups of word lines until all word lines are deselected.

Abstract: A voltage regulator is disclosed which is coupled with a programmable trimming circuit by a trim test circuit. When disabled, the trim test circuit passes the logic states of the signals produced by the trimming circuit to the voltage regulator. When enabled, the trim test circuit applies signals to the voltage regulator which correspond with asserted logic states of signals producible by the trimming circuit. Thus, the effect of the trimming circuit on the voltage regulator is testable without actual programming of the trimming circuit.

Abstract: A method and apparatus for detecting resistive defects in a memory device. A pulldown device is placed at the end of a wordline opposite the end of the wordline having a wordline driver. When the test mode is enabled the wordline pulldown device is turned on. By tailoring the on resistance of the pulldown device such that it is a few times larger than the wordline wire resistance, a resistive divider may be created between the wordline wire resistance and the pulldown device resistance. If a resistive defect exists in the wordline, the increased wordline resistance will create a voltage drop in the wordline when the pulldown device is turned on. This voltage drop indicates that a defect exists in the wordline, and the defect may be located by determining the area of the wordline in which the voltage drop occurs.

Abstract: A method for error detection and correction in an electronic trip unit is presented. The electronic trip unit includes a ROM having trip unit application code, e.g., main functionality firmware, including initializing parameters, and boot code, stored therein and an EEPROM having operational parameter code, e.g., encoded enumerations for parameters such as 50/60 Hz., UL/ANSI/IEC, ect., stored therein The integrity of the code is monitored using CRC or checksum. Corrupted data is recovered by using encoded enumerations with at least two repetitive bit patterns of appropriate width. Encoding enumerations with greater that two repetitive bit patterns allows for each enumerated value to be recovered from any single bit corruption by replacing the corrupted pattern with the matching pattern. Alternatively, with a plurality of encoded enumeration groups stored in the EEPROM a corrupted enumeration can be properly selected and corrected by cross correlating the enumeration groups.

Abstract: Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its originally intended level. The error is initially not readily detected during normal read until the cumulative drift becomes so severe that it develops into a hard error. Data could be lost if enough of these hard errors swamps available error correction codes in the memory. A memory device and techniques therefor are capable of detecting these drifts and substantially maintaining the threshold voltage of each memory cell to its intended level throughout the use of the memory device, thereby resisting the development of soft errors into hard errors.

Abstract: A flash memory capable of solving a problem of a conventional flash memory in that it requires considerable time and effort to measure supply voltages generated in the flash memory during writing, erasing and verifying operations, and is difficult to acquire accurate results, because they cannot be measured by a tester and must be measured manually by putting a probe directly to voltage supply lines.

Abstract: A system and method for injecting and canceling a bias voltage in an attenuated circuit is presented. The attenuated circuit is disposed within a tri-state logic-level measurement apparatus. The bias voltage is provided to ensure that when the measurement apparatus is floating, it floats at the tri-state voltage. In one embodiment, a summing network is connected to an attenuator, a first voltage generator which provides a bias voltage and a second voltage generator which provides a cancellation voltage. In another embodiment, a FET amplifier is provided in place of the summing network.

Abstract: A device and a process for testing a memory element are described. A second memory element is connected in parallel to the first memory element. In order to measure the charge status of the first memory element, the second memory element is brought into a predefined first status and the time required by the second memory element to go from the first status to a second status is measured. This time is analyzed in order to test the memory element.

Abstract: In a memory device using an electrically rewritable nonvolatile memory as a storage medium, wherein, in order to allow the memory to deteriorate evenly, the erasing time and writing time are measured, the influence of scatter of cells in the memory being eliminated on the basis of the resultant measurement values, a substantial degree of deterioration being thereby determined with a high accuracy, whereby a memory device of a high reliability and a high efficiency is practically obtained. In order to rewrite an electrically rewritable nonvolatile memory (1), there are provided a means for measuring the erasing time and writing time, a means for comparing an erasing time with a stored reference time, a means for correcting writing time on the basis of the results of the comparison, and a means for determining deterioration on the basis of the results of the correction.

Abstract: An integrated circuit package having external pins includes a function circuit, such as an address buffer, receiving an input voltage through one of the pins. If the input voltage exceeds a maximum rated voltage, the function circuit can be damaged by voltage over-stress. To provide a definitive indication that the function circuit may have been over-stressed, a diode and a fuse are connected in series between the function circuit's pin and ground. When the input voltage nears the maximum rated voltage, the diode biases and applies a voltage to the fuise. The fuse is selected so that when the input voltage exceeds the maximum rated voltage, the applied voltage blows the fuse. At a later time, the function circuit can be tested for over-stress by applying a voltage to the function circuit's pin which is sufficient to forward bias the diode. If no current flows after a sufficient biasing voltage is applied to the pin, it is a definitive indication that the function circuit may have been over-stressed.

Abstract: A data interleaving system (20) provides flexibility by performing the interleaving function in a high level controller (32) and a separate low level controller (34). The high level controller (32) receives commands to operate on a codeword basis, in which a codeword is made up of a plurality of symbols which are grouped into a programmable number of frames. The low level controller (34) operates under the direction of the high level controller (32) on a symbol-by-symbol basis. By separating the codeword level tasks from the symbol level tasks, the data interleaving system (20) is able to accommodate various ratios of the number of frames per codeword without significant complexity. An analogous data de-interleaving system (220) includes a high level controller (232) and a low level controller (234).

Abstract: An integrated memory circuit is described which can be tested using both a burn-in test and an application specific test. The application specific test is initiated by providing a supervoltage on one of the integrated memory circuit external input pins. A reference voltage circuit is described for producing a variable or multi-level reference voltage used by a supervoltage detection circuit. If a burn-in test is being performed, the reference voltage is adjusted from a level used when the memory is not operating in a burn-in test mode. A multi-level reference voltage is provided to the supervoltage detection circuit, thereby, adjusting the supervoltage level needed to initiate an application specific test.