Abstract: The present invention pertains to semiconductor memory devices, and particularly to a system and method for adaptively setting the operating voltages for SRAM for both Vtrip and SNM to reduce power while maintaining functionality and performance, based on modeling and characterizing a test structure. One embodiment comprises an SRAM array, a test structure that characterizes one or more parameters that are predictive of the SRAM functionality and outputs data of the parameters, a test controller that reads the parameters and identifies an operating voltage that satisfies predetermined yield criteria, and a voltage controller to set an operating voltage for the SRAM array based on the identified operating voltage. One method sets an operating voltage for an SRAM by reading test structure data of the parameters, analyzing the data to identify an operating voltage that satisfies predetermined yield criteria, and setting the operating voltage for the SRAM based on the identified operating voltage.

Abstract: A memory includes an array of memory cells arranged in a plurality of rows and a plurality of columns. An address transform module receives a logical address including a logical column address and logical row address, and transforms the logical address into a physical address having a physical row address and a physical column address. An address decoder module accesses an individual memory cell of the array of memory cells based on the physical address.

Abstract: A communication control system has a plurality of control units that are connected via a communication bus to provide bidirectional communication. A control unit detects a failure when it occurs. Upon failure detection, the control unit generates a failure detection signal which operates a communication signal cutoff means to cut off the communication signal transmission from the control unit. In accordance with the communication signal reception state in a control unit other than the control unit in which the failure is detected, the former control unit identifies a failure occurrence in the latter faulty control unit.

Abstract: Methods, systems, and apparatuses for monitoring and refreshing data stored in radio frequency identification (RFID) tags are described. A voltage margin for data stored in memory of a tag is checked. If the voltage margin has decreased to an undesirable level, the data stored in the tag is refreshed.

Abstract: Various methods and apparatuses are described for a system that includes some on-chip components, e.g., I/Os, test processors, soft wrappers, etc., an external testing unit that provides Parametric Measurement Unit (PMU) capability, a Device Interface Board (DIB) that includes resistors between the chip and the external tester, and various tests performed on the I/Os by the on-chip testing logic and external testing unit facilitated through the DIB.

Abstract: The data detecting apparatus may provide a voltage comparison unit that compares a reference voltage, associated with a specific data bit from among a plurality of data bits stored in a memory cell, with a threshold voltage in the memory cell, a detection unit that detects a value of the specific data bit based on a result of the voltage comparison unit, and a decision unit that decides whether the specific data bit is successfully detected based on whether an error occurs in the detected data. The detection unit may re-detect a value of the specific data bit based on detection information with respect to at least one of an upper data bit and a lower data bit in relation to the specific data bit, in response to a result of the decision unit.

Abstract: A system and method, including computer software, allows reading data from a flash memory cell. Voltages from a group of memory cells are detected. The group of memory cells have associated metadata for error detection, and each memory cell stores a voltage representing a data value selected from multiple possible data values. Each possible data value corresponds to one range of multiple non-overlapping ranges of analog voltages. Memory cells having uncertain data values are identified based on the detected voltages. Alternative data values for the memory cells having the uncertain data values are determined, and a combination of alternative data values is selected. An error detection test is performed using the metadata associated with the multiple memory cells and the selected combination of alternative data values.

Abstract: A partial voltage level read is made on memory cells of a solid state memory device during a voltage settling time after the memory cells are charged (e.g., by a pulse from a charge pump). Digital values representing partial voltage levels are checked for errors (e.g., by an error correction code (ECC) engine). If the values can be corrected, then the values are released for host access. If the values cannot be corrected, then a full voltage read is performed on the memory cells after the voltage levels have substantially settled. Digital values corresponding to the full voltage reads can be released for host access. The use of partial voltage reads results in faster read of solid state memory devices.

Abstract: A system and method that utilizes a dedicated transmission queue to enable expedited transmission of data messages to adaptive “nearest neighbor” nodes within a cluster. Packet descriptors are pre-fetched by the communications adapter hardware during the transmission of the preceding data element and setup for the next transmission is performed in parallel with the transmission of the preceding data element. Data elements of a fixed length that is equal to the cache line size of the communication hardware can optionally be used to provide optimized transfer between computer memory and communications hardware. The data receiving processing can also be optimized to recognize and handle cache line size data elements.

Abstract: There is provided an output controller with a test unit, which can test an appropriate delay amount according to an operating frequency under a real situation. The output controller includes an initial synchronizing unit for outputting a first output enable signal when a read CAS signal is activated; a plurality of synchronizing units connected in series to output an output signal of a previous stage as an output enable signal in synchronization with a corresponding driving clock, a first stage of the synchronizing units receiving the first output enable signal; and a test unit for adjusting a delay amount of an input clock according to a test signal and outputting the driving clock.

Abstract: In a test apparatus for a data storage device, embodiments of the present invention help to support data storage devices with different specifications using a single processor. According to one embodiment, a test apparatus comprises a processor card and adapter cards. The adapter cards comprise power supply circuits to generate power supply voltages to be supplied to the hard disk drives (HDDs). Implementing power supply circuits in the adapter card accomplishes flexible support for HDDs with various specifications with a single processor cards. Since a plurality of HDDs are concurrently tested with a single processor card, it is not necessary to mount a plurality of power supply circuits on the processor card so that the processor card can be decreased in size.

Abstract: A test device that can improve test reliability is provided. In the test device, an error detecting unit detects an error of inputted test signals to generate an error flag, a normal test unit performs a test operation according to the test signals when the error flag is deactivated, and an error information providing unit indicates the error of the test signals when the error flag is activated.

Abstract: According to this invention, a highly reliable memory device that uses up a life of a flash memory can be provided. The memory device is a nonvolatile memory device including a plurality of memory cells, in which: each of the plurality of memory cells is an FET which includes a floating gate; the plurality of memory cells are divided into a plurality of deletion blocks; and the nonvolatile memory device reads data stored in a first deletion block, detects and corrects an error contained in the read data, stores, when the number of bits of the detected error exceeds a threshold, the corrected data in a second deletion block, sets a smaller value as the threshold as an error frequency detected in the first deletion block is higher, and sets a smaller value as the threshold as the number of deletion times executed in the first deletion block is larger.

Abstract: A method and system for determining element voltage selection control values for a storage device provides energy conservation in storage arrays while maintaining a particular performance level. The storage device is partitioned into multiple elements, which may be sub-arrays, rows, columns or individual storage cells. Each element has a corresponding virtual power supply rail that is provided with a selectable power supply voltage. At test time, digital control values are determined for selection circuits for each element that set the virtual power supply rail to the minimum power supply voltage, unless a higher power supply voltage is required for the element to meet performance requirements. The set of digital control values can then be programmed into a fuse or used to adjust a mask at manufacture, or supplied on media along with the storage device and loaded into the device at system initialization.

Abstract: A data preserving method and a data accessing method for a non-volatile memory are provided. In the data preserving method, a data is checked according to an error correcting code (ECC) to obtain an error bit number of the data. When the error bit number is greater than a threshold, the data is moved from a first memory unit to a second memory unit and is corrected according to the ECC. Thereby, the data stability of the non-volatile memory is improved.

Abstract: Embodiments of the present disclosure provide methods, devices, and systems for performing a programming operation on an array of non-volatile memory cells. One method includes programming a number of cells to a number of final data states. The method includes performing, prior to completion of, e.g., finishing, the programming operation, an erase state check on a subset of the number of cells, which were to be programmed to an erased state.

Abstract: A burn-in test system. A burn-in test system includes a device under test (DUT), a temperature controller coupled to the DUT, and a test controller. During testing, the test controller: (a) sets a parameter of the DUT to a first value and applies a test stimulus to the DUT, and (b) sets the parameter of the DUT to a second value and applies the test stimulus to the DUT. A change in the value of the parameter results in a change in the amount of heat dissipated by the DUT. The temperature controller maintains the DUT at a pre-determined temperature during testing with the parameter set to both the first and the second values. The DUT may be further coupled to a module that comprises circuitry employed in a product-level application environment. The module is configured by the test controller to simulate a product-level application.

Abstract: The present invention provides a semiconductor testing apparatus and method capable of reliably determining whether a semiconductor memory is good or bad. A “1” reading test of each cell corresponding to one bit at a first step is first performed on a memory cell array. “0” writing of each cell corresponding to one bit at a second step and a “0” reading test of each cell corresponding to one bit at a third step are executed on the memory cell array. Thus, the time taken from the supply of power to the start of the “0” reading test of the reference cell at the third step can be significantly shortened. As a result, a defect of a reference bit line due to a breaking or high resistance of a gate of a reference column switch transistor corresponding to a normally ON transistor can be screened.

Abstract: A method for managing a memory device, a memory device so managed and a system that includes such a memory device. A value of a longevity parameter of the device is monitored after a data operation on the device in which the monitoring is performed by the device. A grade of the device is derived from the value. Preferred longevity parameters include a ratio of successfully-processed data to unsuccessfully-processed data and a deviation in a power consumption of the device. The grade serves as a forecast of a life expectancy of the memory. Preferred grades include: a comparison grade, a maximum grade, and an average grade.

Abstract: A method and system for testing memory modules is disclosed. The system includes a memory module and a connector configured to receive the module. The memory module is configured to operate in two modes: In the first operation mode the module uses a frequency between a low frequency and a high frequency. In the second operation mode, the module uses a frequency lower than the lower frequency. A control circuit is coupled to the connector. The control circuit is configured to apply a control signal to the circuit module when the circuit module is received in the connector. When the circuit module is received in the connector, the control signal is applied. This applied control signal causes the module to operate in the second operation mode.

Abstract: A method for detecting word line leakage in a memory device includes coupling a first plurality of word lines in the memory device to a voltage source while grounding a second plurality of word lines. Each of the second plurality of word lines is adjacent to a corresponding one of the first plurality of word lines. The method includes waiting for a period of time to allow the word lines to reach a predetermined read voltage level. The method also includes decoupling the first plurality of word lines from the voltage source and waiting for a second predetermined period of time to allow the first plurality of word lines to discharge. The method further includes sensing a current associated with the word lines, and comparing the current with a predetermined reference current which is selected for identifying a word line leakage condition associated with the first plurality of word lines.

Abstract: A storage medium reproducing apparatus includes a storage unit, a correction history storage unit, a correction history implementing unit, and a correcting unit. The storage unit includes a plurality of information storage units storing information depending on whether a charge quantity is greater than a predetermined charge quantity threshold value, and a correction code storage unit storing error correction codes for the information stored in the information storage units. The correction history storage unit stores a correction history containing identification information for the information storage unit corrected with an error correction code is performed, and a content of the correction. The correction history implementing unit corrects information in compliance with the content of the correction when the information is read from the information storage unit.

Abstract: This invention provides a semiconductor memory device and its data writing method capable of saving the needed time to a minimum even in repeating a data write operation maximum number of times. More specifically, this invention provides a semiconductor memory device and its data writing method as follows. A flash memory 101 is set at a test mode by fixing the test pad TP at L level. When a verify operation passes, a verify pass signal input terminal (VPASS) of a data write controlling circuit WCC and a verify pass signal input terminal (VPASS) of a data write counter circuit WCT are fixed at L level by a verify pass signal invalidating means 3 although a verify circuit VC outputs an L level verify pass signal VPASS. A latch circuit LC holds a latched verify pass signal VPL at H level and a verify start signal input terminal (VR) of the verify circuit VC is fixed at L level. A write operation without a verify operation is repeated number of times preset in the data write counter circuit WCT.

Abstract: Methods are provided to monitor and report performance data of a device such as a data storage drive. A plurality of quantitative values are obtained from feedback and measurement mechanisms in a data storage device of a first model during operation of the storage device. The plurality of quantitative values are normalized. Then, one or more qualitative values are generated from one or more normalized quantitative values and evaluated against corresponding baseline performance values established for the first model.

Abstract: Categories are established for use in physiological monitoring devices and these categories are prioritized such that data indicative of a critical event self-triggers a communication to an external receiver for the purpose of re-transmitting the critical data for use by a clinician. The categories can be established by the clinician and, if desired, the precise monitored data parameters can be assigned to specific categories. Far-field transmission can be used to send certain stored data to an external receiver, provision is made for externally charging the device batteries.

Abstract: A memory (10) has a memory array (12), a charge pump (18), a voltage regulator (20), a refresh control circuit (16), and a refresh counter (22). The charge pump (18) provides a substrate bias to the memory array (12). The voltage regulator (20) provides a pump enable signal for maintaining a voltage level of the substrate bias within upper and lower limits. The refresh control circuit (16) controls refresh operations. The refresh counter (22) is coupled to receive the pump enable signal, and in response, provides a refresh timing signal to the refresh control circuit (16) to control a refresh rate of the memory array (12). A programmable fuse circuit (26) is provided to program the refresh rate using the counter (22). The programmable fuse circuit (26) may be programmed during wafer probe testing or board level burn-in. A built-in self test (BIST) circuit (24) may be included to facilitate testing.

Abstract: A method suitable for testing an integrated circuit device is disclosed, the device comprising at least one module, wherein the at least one module incorporates at least one associated module monitor suitable for monitoring a device parameter such as temperature, supply noise, cross-talk etc. within the module.

Abstract: An error detection structure is proposed for a multilevel memory device including a plurality of memory cells each one being programmable at more than two levels ordered in a sequence. Each level representsmg a logic value consisting of a plurality of bits, wherein the structure includes components for detecting errors in the values of a selected block of memory cells. The structure further includes components for partitioning the bits of each memory cell of the block into a first subset and a second subset, the bits of the first subset being unchanged in the values of a first and a second ending range in the sequence. The components_for detecting errors only operate on the bits of the second subset of the block.

Abstract: In a nonvolatile memory system, first raw data is obtained from stored data using a first set of reading parameters. Subsequently, the first raw data is transferred to an ECC circuit where it is decoded. While the first raw data is being transferred and decoded, second raw data is obtained from the same stored data using a second set of reading parameters.

Abstract: It is aimed to efficiently test devices that can transfer data at a very high bit rate. A test apparatus for testing a device under test includes a capture memory that stores thereon an output pattern received from the device under test, a header detecting section that reads the output pattern from the capture memory and detects a portion matching a predetermined header pattern in the output pattern, and a judging section that judges whether the output pattern is acceptable based on a result of comparison between a pattern, in the output pattern, which starts with the portion matching the predetermined header pattern and a corresponding expected value pattern.

Abstract: An apparatus and method for detecting an over-programming condition in a multistate memory cell. The invention is also directed to identifying the over-programmed cells and providing an alternate location at which to write the data intended for the over-programmed cell. An over-programmed state detection circuit generates an error signal when the data contained in a multistate memory cell is found to be over-programmed relative to its intended programming (threshold voltage level) state. Upon detection of an over-programmed cell, the programming operation of the memory system is modified to discontinue further programming attempts on the cell. The over-programmed state detection circuit is also used to assist in correcting for the over-programming state, permitting the programming error to be compensated for by the memory system.

Abstract: A method of testing a dynamic random access memory (DRAM) device that has N rows of storage cells and that requires, in at least one operating mode, at least N refresh commands to be received from an external source within a specified time interval. The rows of storage cells are tested in a first retention test to identify rows that fail to retain data over the specified time interval. The rows that fail to retain data over the specified time interval are tested in a second retention test to identify rows that retain data over an abbreviated time interval, the abbreviated time interval being shorter than the specified time interval.

Abstract: An apparatus, system, and method are disclosed for modifying memory device timing and voltage. A detection module detects a change of memory device stress. A timing modification module modifies the memory device timing in response to the change of the memory device stress. In addition, a voltage modification module modifies the memory device voltage in response to the change of the memory device stress. In one embodiment, a processor pause module pauses the operation of a processor module while the timing modification module modifies the memory device timing and the voltage modification module modifies the memory device voltage.

Abstract: A semiconductor device has multilevel memory cells, each cell storing at least three levels of data each. At least a first data composed of first data bits and a second data composed of second data bits are arranged in order that at least a bit of an N-order of the first bits and a bit of the N-order of the second bits are stored in one of the cells, the N being an integral number. A voltage corresponding to the N-order bits is generated and applied to the one of the cells in response to an address information corresponding thereto. Another semiconductor device has multilevel memory cells arranged so as to correspond to a physical address space, each cell storing 2n levels of data each expressed by n (n?2) number of bits (X1, X2, . . . , Xn). A logical address is converted into a physical address of the physical address space. Judging is made whether a logical address space including the logical address matches the physical address space.

Abstract: According to one embodiment of the present invention, an integrated circuit includes a plurality of memory cells, the integrated circuit being operable in a memory cell testing mode in which testing signals are applied to the memory cells, wherein the strengths and durations of the testing signals at least partly differ from the strengths and durations of programming signals or sensing signals used for programming and sensing memory states of the memory cells.

Abstract: A method for checking the refresh function of a memory having a refresh device includes the steps of, first, ascertaining whether or not refresh request pulses are being produced on the information memory and, if so, at what intervals of time from one another these refresh request pulses are produced. Next, a control unit for the information memory is supplied with refresh test pulses produced outside of the information memory instead of being supplied with the refresh request pulses. Then, the refresh test pulses are used to check a refresh device situated on the information memory.

Abstract: Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its originally intended level. The error is initially not readily detected during normal read until the cumulative drift becomes so severe that it develops into a hard error. Data could be lost if enough of these hard errors swamps available error correction codes in the memory. A memory device and techniques therefor are capable of detecting these drifts and substantially maintaining the threshold voltage of each memory cell to its intended level throughout the use of the memory device, thereby resisting the development of soft errors into hard errors.

Abstract: A method for testing a word line failure of a memory device is provided. The memory device comprises a memory cell with a transistor connecting to a word line and a bit line. The method comprises driving the word line to a predetermined voltage level by a word line driver so as to turn off or on the transistor of the memory cell; and reducing the driving ability of the word line drive.

Abstract: A memory card includes a non-volatile memory, a memory controller for controlling the operation of the memory card. The memory controller is capable of providing an interface with outside according to a predetermined protocol, and performs error detection and correction of the memory information at regular time intervals or at the timing of connection of electric power supply, independently of reading out the memory information according to external access request. Therefore, it is possible to improve reliability of data retention in the non-volatile memory without the host device reading out the memory information from the non-volatile memory of the memory card.

Abstract: Methods of performing a sector erase of flash memory devices incorporating built-in self test circuitry are provided. The present invention employs an interactive verification and sector erase algorithm to verify and repeatedly erase the sector until a portion of the groups of each page of the sector are erased or a first maximum number of erase pulses is achieved. The algorithm further includes a word verification and erase operation that sequentially verifies and erases each word of the sector until each word is erased or a second maximum number of erase pulses is achieved. The second maximum number of erase pulses may be based on a function of the first maximum number of erase pulses. The second maximum number of erase pulses may be input to the sector erase algorithm as a multi-bit code. The second maximum number of erase pulses and conversion of the multi-bit code may be based on a binary multiple of the first maximum number of erase pulses.

Abstract: A memory device including a cell array is disclosed. One embodiment includes a plurality of memory cells, wherein each memory cell is capable of showing at least two distinguishable states, a programmable read voltage source adapted to supply an alterable read voltage and a test control unit. The test control unit includes a voltage control unit that is capable of controlling the read voltage source, a counter unit that is capable of counting the memory cells exhibiting a predetermined state and an analysis unit that is capable of rating a currently determined number of memory cells exhibiting a predetermined state.

Abstract: A host device 1 includes an NG table 10 for storing addresses specifying areas of a bulk memory 3 into which data cannot be written, a performance-guaranteed environment determination means 11 for determining whether or not the current environment of the bulk memory 3 is outside a performance-guaranteed environment where the performance of the bulk memory 3 is guaranteed, and control means 12, 13, 14, and 15 for writing data in an area of the bulk memory which is specified by an address which is not stored in the NG table 10 when the performance-guaranteed environment determination means 11 determines that the current environment is outside the performance-guaranteed environment. Therefore, even if the current environment of the bulk memory is outside the performance-guaranteed environment, the host device can normally write data in the bulk memory, thereby improving the reliability of the system.

Abstract: A system and method for determining a fault threshold for an operational module according to the model of the operational module are described. The system includes an operational module, a storage unit, and a monitoring unit. The operational module has circuitry for producing a characterization signal with an electrical characteristic that uniquely correlates to the model of the operational module. A storage unit maintains an association between at least one parameter value and a fault threshold. A monitoring unit is in communication with the operational module to receive the characterization signal and with the storage unit. The monitoring unit measures the electrical characteristic of the characterization signal to derive a parameter value therefrom and accesses the storage unit to determine the fault threshold associated with the derived parameter value.

Abstract: A method and apparatus for data analysis according to various aspects of the present invention is configured to automatically select one or more outlier identification algorithms for identifying statistical outliers in test data for components.

Abstract: The present invention provides a test apparatus comprising: a threshold voltage setting unit for setting threshold voltages of a logic device component connected to the signal propagation path; a test signal supply unit for supplying a test signal to the test subject device so as to operate the logic device component provided to the signal propagation path in a state in which the threshold voltages have been set to first threshold voltages, and in a state in which the threshold voltages have been set to second threshold voltages, by the threshold voltage setting unit; a current measurement unit, for measuring a first operating current which is the current consumption of the test subject device in a case in which the logic device component operates in a state in which the first threshold voltages have been set, and for measuring a second operating current which is the current consumption of the test subject device in a case in which the logic device component operates in a state in which the second threshold v

Abstract: According to embodiments of the present invention, an integrated circuit such as a processor includes a counter to count an actual number of unreliable storage locations in the processor cache, at least one register to store an acceptable number of unreliable storage locations for the cache, a detector to measure a thermal environment of the processor, and circuitry to raise an operating voltage of the processor if the actual number of unreliable storage locations exceeds the acceptable number of unreliable storage locations, and if the thermal environment is acceptable.

Abstract: The present method generates a greater number of hot holes than those generated by normal write/erase operations, thereby making it possible to evaluate an operation of a non-volatile memory with respect to hot holes. The present method performs a write operation to the non-volatile memory at lower temperatures than normal temperatures at normal use or/and at a lower operation voltage than a normal operation voltage at normal use, so as to generate a greater number of hot holes than those generated by normal write/erase operations between floating gates and drains of the memory, and then evaluates the operation of the memory while exposing it to the normal operation temperatures. This method is applicable to reliability tests of non-volatile memories such as FLASH memories.

Abstract: A test method includes providing an integrated circuit, where the integrated circuit includes a memory base cell, where the memory base cell includes a first storage node set, a second storage node set, a set of other nodes, and a set of circuit elements each having a plurality of terminals, where the set of other nodes includes a first data node for accessing the first storage node set, a first access control node for controlling the access of the first storage node set, a first supply node for supplying the first storage node set, and a second supply node for supplying the second storage node set, where the first and second supply nodes are of the same sinking or sourcing type.

Abstract: A method and system for monitoring and compensating the performance of an operational circuit is provided. The system includes one or more integrated circuit chips and a controller. Each integrated circuit chip includes one or more operational circuits, each operational circuit having at least one controllable circuit parameter. Each integrated circuit chip also includes a process monitor module at least partially constructed thereon. The controller is coupled to each process monitor module and to each operational circuit. The controller includes logic for evaluating the performance of an operational circuit based on data obtained from process monitor module and operational circuit related data stored in a memory. Based on the evaluation, the controller determines whether any deviations from desired or optimal performance of the circuit exist. If deviations exist, the controller generates a control signal to initiate adjustments to the operational circuit to compensate for the deviations.

Abstract: A testing apparatus for testing a memory-under-test includes a writing section for writing preset test data into each page of said memory-under-test to test said memory-under-test and a fail memory unit for storing the test result of said memory-under-test. The fail memory unit includes a write time measuring section for measuring a write time required for writing said test data per each of said pages, an integrating section for integrating said write time across a plurality of said pages set in advance, and a judging section for judging whether or not said memory-under-test is defect-free by comparing a value integrated by said integrating section with an expected value set in advance. The integrating section further integrates said write time per page group having said predetermined number of pages. The judging section further judges whether or not said page group is defect-free based on an integral value of said write time per said page group.