Abstract: An integrated circuit (IC) includes a plurality of intellectual properties (IPs), each of the plurality of IPs includes a test logic. A first memory controller provides user data received from at least one of the plurality of IPs to a first memory in a first operation mode. A scanner gathers debugging data from the test logics of the plurality of IPs in a second operation mode. And a second memory controller receives the debugging data from the scanner and provides the debugging data to the first memory in the second operation mode.

Abstract: When a computer boots up, a Basic Input/Output System (BIOS) configures system memory to have a crash memory area within the system address map, which can be used by a processor to dump crash memory data. When an error event occurs, the processor can initiate a dump to the crash memory area. Any desired data can be placed into the crash memory area, but typical data can include a state of registers in the processor. The processor then sets a flag, such as an external pin, indicating that the crash memory data is ready to be read. The flag can be read by a secure processor, which then reads the crash memory area at normal memory access speeds using the system bus. For example, the secure processor can access the crash memory area using Direct Memory Access (DMA) reads over a PCIe system bus.

Abstract: A circuit comprises a scan chain comprising one or more multi-bit flip-flops, a plurality of multiplexers, and new scan enable signal generation circuitry. Each of the plurality of multiplexers is associated with a particular bit of the one or more multi-bit flip-flops with an output of the each of the plurality of multiplexers coupled to a data input of the particular bit, which is configured to select, based on a scan direction control signal, between an input signal from functional circuitry of the circuit and an input signal from a data output of a bit of the scan chain immediately following the particular bit in a normal scan shift direction. The new scan enable signal generation circuitry is configured to generate a new scan enable signal for the one or more multi-bit flip-flops based on the scan direction control signal and a scan enable signal for the scan chain.

Abstract: Testing systems and method of testing an integrated circuit are provided. A testing system comprises an input terminal, multiple circuit elements, each having a register, and an output terminal forming a scan chain through which an input signal is propagated. The testing system further comprises a debugger that includes a mapping module that stores information mapping register values to their respective functional meanings. The input signal is applied to extract all values of all of the registers whether or not accessible by a processor.

Abstract: This application discloses a computing system implementing an automatic test pattern generation tool can generate test patterns to apply to a reversible scan chain in an integrated circuit. The reversible scan chain can be configured to serially load and unload the test patterns in multiple directions to generate test responses. The computing system can implement a defect diagnosis tool to detect a presence of a suspected defect associated with the reversible scan chain based on the test responses, identify which of the multiple directions used to load and unload the test patterns corresponds to the suspected defect in the reversible scan chain based on the test responses, and determine a portion of the integrated circuit to inspect for a manufacturing fault corresponding to the suspected defect based, at least in part, on the identification of which of the multiple directions corresponds to the suspected defect in the reversible scan chain.

Abstract: An emulation system may include an emulator. The emulator may include at least one chip and at least one FPGA. The chip may be associated with the FPGA. The FPGA may operate as a coprocessor to implement in-system scan test of the chip. In a scan mode of the in-system scan test, the coprocessor may transmit one or more in-system test instructions to the chip through its existing connections with the chip. The coprocessor may capture test response data from the chip in response to the one or more in-system test instructions through its existing connections with the chip. In an offline mode, the coprocessor may compare the test response data with expected response data to determine if the chips are functioning correctly.

Abstract: Embodiments of the present invention are directed to methods, systems, and circuitry for memory arrays. A system for testing a memory array having self-test circuitry includes a register having register latches operable to receive error logic signals having respective first states or second states. The register latches are arranged in series having respective latch inputs cascaded with preceding latch outputs operable to shift the error logic signals to a serial output according to a control signal that is common to the register latches. The system includes an aggregate latch operable to receive the serial output and having input logic configured to maintain a first state of the aggregate latch until the serial output is a second state. The system includes a built-in self-test (BIST) engine including stored instructions operable upon execution by the BIST engine to output the control signal.

Abstract: A method for securing the communications between a publisher and a subscriber in an Internet of things networks. An example method includes receiving a challenge vector from a subscriber and determining a response vector using a physically unclonable function (PUF) for each challenge value in the challenge vector to generate a response value. The response vector it is sent to the subscriber.

Abstract: A computer device comprises a user interface configured to display time information associated with a feature. The time information indicates when the feature will change from one of being available and unavailable to the other of being available and unavailable. The time information changes at a first rate. At least one processor is configured, in response to a user interaction via the user interface, to cause the user interface to display content, the time information being configured to change at a second different rate while the content is displayed.

Abstract: Methods and systems for determining a systematic defect in a circuit under test is provided. Elements of the circuit under test converted into scan cells. A first scan chain that includes a first plurality of scan cells is formed. Each scan cell of the first plurality of scan cells of the first scan chain are of a first cell type. The first scan chain contains a first scan input and a first scan output. A first test pattern is applied at the scan input and a first test output is collected for the applied first test pattern at the first scan output. The collected first test output is compared with a first expected test output. The first cell type is marked to be a suspect for a systematic defect when the first test output is different from the first expected test output.

Abstract: There is disclosed a silicon integrated circuit comprising a Physically Unclonable Function and an online or embedded test circuit, said online test circuit comprising one or more circuit parts being physically adjacent to said PUF and said one or more circuits embodying one or more tests which can be performed to determine one or more quality properties of said PUF or otherwise characterize it. Different tests with specific associated method steps are described.

Abstract: The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Further the disclosure provides an approach to access the TCA of a device when the device exists in a daisy-chain arrangement with other devices, such as in a customer's system. Additional embodiments are also provided and described in the disclosure.

Abstract: The present disclosure relates to testing structures and, more particularly, to a circuit and method for design of RF integrated circuits for process control monitoring. The circuit includes a radio frequency integrated circuit comprising a plurality of active NFET devices and passive devices arranged in a single topography; and a plurality of NFET switches which are configurable to diagnose physical failures of the plurality of active NFET devices and the passive devices by isolating selected ones of the plurality of active NFET devices and the passive devices into different built-in circuit topologies by selectively turning on and off the plurality of active NFET devices and the passive devices.

Abstract: Systems, methods, media, and other such embodiments described herein relate to improved operation of test devices which verify circuit operations. One embodiment involves accessing a circuit design comprising a plurality of instances of one or more blocks, where each block of the one or more blocks is associated with a corresponding block test pattern comprising one or more test subpatterns. Each corresponding block test pattern is processed to identify independent test subpatterns, and then each instance is processed to identify each independent test subpattern for the circuit design. Similar types of independent test subpatterns are merged into a circuit design test pattern, such that at least two of the independent test subpatterns associated with the circuit design occupy shared test cycles within the circuit design test pattern.

Abstract: A logic BIST circuits concurrently execute a first scan test for a scan chain as a target and a second scan test for a scan chain as a target, when they are set to a an LBIST mode, and execute the first scan test without executing the second scan test, when they are set to a simultaneous test mode. Memory BIST circuits execute a test for memory circuits concurrently with the first scan test, when they are set to the simultaneous test mode.

Abstract: A falling edge controller includes a controller having an inverted TCK (Test Clock) input, a TMS (Test Mode Select) input, a shift register control output, an update register control output, and a shift output; a shift register having a TDI (Test Data In) input, a shift register control input coupled to the shift register control output, address inputs, a select input, address and select outputs, and a TDO (Test Data Out) output; an update register having address and select inputs coupled to the address and select outputs, an update register control input coupled to the update register control output, address outputs coupled to the address inputs, and a select output coupled to the select input; and address circuitry having address inputs coupled to the address outputs, and having an enable output.

Abstract: Embodiments provided in this disclosure include a method, computer program product, and system for protecting sensitive data in a processing system comprising a plurality of processor cores. The method includes designating at least one processor core for processing sensitive data, and during a dump event, capturing data from each of the plurality of processor cores except the designated processor core to prevent unauthorized access to sensitive data.

Abstract: Embodiments provided in this disclosure include a method, computer program product, and system for protecting sensitive data in a processing system comprising a plurality of processor cores. The method includes designating at least one processor core for processing sensitive data, and during a dump event, capturing data from each of the plurality of processor cores except the designated processor core to prevent unauthorized access to sensitive data.

Abstract: A method and test circuit are provided for implementing enhanced scan data testing with minimization of over masking in an on product multiple input signature register (OPMISR) test, and a design structure on which the subject circuit resides. Common Channel Mask Scan Registers (CMSR) data is used with a multiple input signature register (MISR) in each satellite. A test algorithm control is used for implementing enhanced scan data testing by independently skewing scan unload shifting of selected OPMISR+ satellite by selected cycles. With this modified shifting, for the same test or a repeated run of the test, Channel Mask Enable (CME) triggered masking lines up on a different bit position in channels of each satellite avoiding over masking.

Abstract: The present disclosure provide techniques for semiconductor testing, and more particularly, to systems and methods for laser-based fault isolation and design for testability (DFT) diagnosis techniques. In one embodiment, an integrated chip (IC) testing apparatus, includes an input pin; a decompressor connected to the input pin; a plurality of scan chains, each scan chain of the plurality of scan chains comprising a plurality of scan cells; a plurality of scan chain control elements, each scan chain control element of the plurality of scan chain control elements being connected between the decompressor and a respective scan chain of the plurality of scan chains, wherein each scan chain control element is configured to enable or disable test data from flowing from the compressor to the respective scan chain; a compressor connected to an output of each scan chain of the plurality of scan chains; and an output pin connected to the compressor.

Abstract: A circuit debugging method includes: utilizing a debugging circuit to determine an operating status of a specific circuit to generate a result; utilizing a register located in a scan chain path to store the result, wherein the scan chain path is arranged for a scan test; and utilizing an output pad located in the scan chain path to output the result, wherein the result is arranged to be indicative of the operating status of the specific circuit.

Abstract: A method, apparatus and system are provided for the tuning of embedded subsystems of a device under test (DUT) that have analog characteristics. In response to a tester invoking one or more test procedures via a command channel between the tester and a target embedded subsystem of the DUT, test firmware of the invoked tests is loaded into the target embedded subsystem. The target embedded subsystem executes the tests under control of the tester in accordance with test parameters received from the tester over the command channel and in accordance with test commands received from the tester over a test signaling channel. The target embedded subsystem returns results of the one or more tests to the tester via the command channel. The results can be used to trim analog characteristics of the target embedded subsystem and can be stored in memory. The test firmware can then be deleted to free up memory space.

Abstract: The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Further the disclosure provides an approach to access the TCA of a device when the device exists in a daisy-chain arrangement with other devices, such as in a customer's system. Additional embodiments are also provided and described in the disclosure.

Abstract: The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Further the disclosure provides an approach to access the TCA of a device when the device exists in a daisy-chain arrangement with other devices, such as in a customer's system. Additional embodiments are also provided and described in the disclosure.

Abstract: Exemplary method, computer-accessible medium, and test configuration can be provided for testing at least one flip-flop. For example, the exemplary test configuration can include at least one scan-out channel having a plurality of regions and a plurality of compactors associated with the plurality of regions. Further, exemplary method, computer-accessible medium, and test configuration can be provided for testing at least on flip-flop that in which at least one scan-out channel having a plurality of regions, a plurality of compactors, and associating the plurality of compactors with the plurality of regions can be provided.

Abstract: An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP of another IC. The Off Chip TAP interface can be selected by a TAP Linking Module on the IC.

Abstract: A method and system of testing an integrated circuit (IC), using a multiple input shift register (MISR) with supporting hardware for diagnosing failure locations in an IC with built-in self-test (BIST) logic, including an On-Product MISR. The system includes BIST logic of a circuit under test (CUT) and a tester including an isolation hash table (IHT) that translates signature fail data of the MISR to a failure location of a latch in the CUT. Signature fail data, and consequently, failure locations in the CUT, are obtained by standard testing of the CUT, testing of selected single channels of the CUT, and data insertion functions to the selected single channels of the CUT to obtain compressed MISR signature changes that, when translated, provide failure locations in the CUT.

Abstract: A programmable integrated circuit may implement a safety function in a first region and a non-safety function in a second region of the programmable integrated circuit. The safety function may require that periodic tests verify the integrity of the programmable integrated circuit during safety test intervals. For this purpose, the programmable integrated circuit may halt the operation of the safety function, partially reconfigure the first region by loading a test function, and execute the test function, while the non-safety function in the second region continues to operate. In the event that the test function executed successfully without finding any defects, the programmable integrated circuit may partially reconfigure the first region by re-loading the safety function. Additional tests may be performed if the test function detected problems with the integrity of the programmable integrated circuit.

Abstract: Embodiments of the present disclosure provide a shift register and a driving method thereof, a gate driving circuit and a display device. The shift register includes a control signal generation module, a first low level pulse generation module, a second low level pulse generation module, and a high level pulse generation module. The control signal generation module generates a first control signal and a second control signal. The first low level pulse generation module receives the first control signal and the second control signal and generate a first low level pulse signal. The second low level pulse generation module receives the first control signal and the second control signal and generate a second low level pulse signal. The high level pulse generation module receives the first control signal and generates a high level pulse signal. This shift register reduces the number of circuit elements.

Abstract: A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection logic selects various of the components to be members of a scan chain under the direction of a host computer. The override selection logic detects a change in the scan chain and, as a result, blocks the entire scan chain from progressing.

Abstract: Described is a signature accumulator with a first set of logic devices, a second set of logic devices, and a memory device. The first set of logic devices includes compaction logic that couples an N-bit input bus to a K-bit first intermediate bus. The second set of logic devices includes commutative arithmetic operation logic that couples both the K-bit first intermediate bus and a K-bit signature bus to a K-bit second intermediate bus. The memory storage device includes a storage element that couples the K-bit second intermediate bus to the K-bit signature bus. The K-bit signature bus is also coupled to a valid-data input signal path.

Abstract: Embodiments of the invention provide a scan test system for an integrated circuit comprising multiple processing elements. The system comprises at least one scan input component and at least one scan clock component. Each scan input component is configured to provide a scan input to at least two processing elements. Each scan clock component is configured to provide a scan clock signal to at least two processing elements. The system further comprises at least one scan select component for selectively enabling a scan of at least one processing element. Each processing element is configured to scan in a scan input and scan out a scan output when said the processing element is scan-enabled. The system further comprises an exclusive-OR tree comprising multiple exclusive-OR logic gates. The said exclusive-OR tree generates a parity value representing a parity of all scan outputs scanned out from all scan-enabled processing elements.

Abstract: Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.

Abstract: A falling edge controller includes a controller having an inverted TCK (Test Clock) input, a TMS (Test Mode Select) input, a shift register control output, an update register control output, and a shift output; a shift register having a TDI (Test Data In) input, a shift register control input coupled to the shift register control output, address inputs, a select input, address and select outputs, and a TDO (Test Data Out) output; an update register having address and select inputs coupled to the address and select outputs, an update register control input coupled to the update register control output, address outputs coupled to the address inputs, and a select output coupled to the select input; and address circuitry having address inputs coupled to the address outputs, and having an enable output.

Abstract: An integrated circuit is configured to receive a test clock input and includes circuitry configured to generate test clocks from the test clock input, and test circuitry configured to use the test clocks in a test mode.

Abstract: A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection logic selects various of the components to be members of a scan chain under the direction of a host computer. The override selection logic detects a change in the scan chain and, as a result, blocks the entire scan chain from progressing.

Abstract: An integrated circuit (IC) chip includes a first circuit block, a second circuit block, an inter-block circuit and a control circuit. The first circuit block is configured to form a first scan chain to set states of flip-flops in the first circuit block. The second circuit block is configured to form a second scan chain to set states of flip-flops in the second circuit block. The inter-block circuit interfaces the first circuit block and the second circuit block. The control circuit is configured to load a first portion and a second portion of a test pattern separately to the first scan chain and the second scan chain to set states of flip-flops in the first circuit block and the second circuit block, enable a test of the inter-block circuit to capture a test result, and unload the test result from the first scan chain and the second scan chain.

Abstract: A scan chain may be formed throughout an integrated circuit in which the scan chain includes at least a first segment and a second segment. A first portion of a test pattern is scanned into the first segment by clocking a first scan cell of the first segment with an even clock while clocking a remainder of the plurality of scan cells in the first segment with an odd clock, in which the odd clock is out of phase with the even clock, in which the even clock and odd clock have a rate equal to a scan rate of the test pattern divided by an integer N. A second portion of the test pattern is scanned into the second segment by clocking the plurality of scan cells in the second segment with the odd clock, such that the second portion of the test pattern is not scanned into the first segment.

Abstract: IC device comprising a plurality of functional components arranged into self-test cells. The IC device is configurable into a first self-test configuration comprising a first set of self-test partitions. Each self-test partition within the first set comprising at least one self-test cell. Functional components of the self-test cell(s) of each self-test partition within the first set are arranged to be configured into at least one scan-chain for said self-test partition when the IC device is configured into the first self-test configuration. The IC device is configurable into a second self-test configuration comprising a second set of self-test partitions. Each self-test partition within the second set comprising at least one self-test cell. Functional components of the self-test cell(s) of each self-test partition within the second set are arranged to be configured into at least one scan-chain for said self-test partition when the IC device is configured into the second self-test configuration.

Abstract: An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.

Abstract: Systems and methods disclosed herein provide for utilizing extra variables in the decompression equation set of an ATPG process for test patterns requiring an excess number of care bits than can be supported efficiently by the current hardware. An elastic interface is utilized between a tester and a decompressor network (e.g., sequential and combinational decompressors) in order to expand the test pattern length and/or the number of input variables. The systems and methods also provide care bits in early scan cycles of the ATPG process for sequential decompressors starting from a fixed state.

Abstract: Methods, systems, and integrated circuits for decompressing a set of scan input data in a Design for Test (DFT) application, in which implementation may include determining a number of scan inputs to applied circuit from automated test equipment (ATE). Based on the number of scan inputs, another aspect of implementation may involve generating a 2-dimensional grid on the integrated circuit (IC). Another implementation aspect may involve decompressing the scan inputs from the ATE according to decompression logic that is sequentially distributed such that the grid can locally apply the last stage of the decompression logic. In accordance with aspects of the method, the physical structure of an IC decompression logic is more accessible to individual scan chains and reduces congestion on board the IC.

Abstract: Operating a scan chain of a test circuit of an integrated circuit to have either a single fanout or multiple fanout to a compressor. The test circuit receives a fanout control signal for configuring the fanout of the scan chain. If the fanout control signal indicates configuring of the scan chain with a single fanout, the output of the scan chain is sent to one input of a compressor. If the fanout control signal indicates configuring of the scan chain with multiple fanout, the output of the scan chain is sent to multiple inputs of the compressor.

Abstract: Functional circuits and cores of circuits are tested on integrated circuits using scan paths. Using parallel scan distributor and collector circuits for these scan paths improves test access of circuits and cores embedded within ICs and reduces the IC's power consumption during scan testing. A controller for the distributor and collector circuits includes a test control register, a test control state machine and a multiplexer. These test circuits can be connected in a hierarchy or in parallel. A conventional test access port or TAP can be modified to work with the disclosed test circuits.

Abstract: Testing of an electrical device is achieved by providing a test access mechanism within the device that can receive scan frames from an external tester. The received scan frames contain stimulus data to be applied to circuitry within the device to be tested, a command for enabling a test control operation, and a frame marker bit to indicate the end of the scan frame pattern. The inputting of scan frames can occur continuously and simultaneous with a commanded test control operation.

Abstract: Disclosed is a test apparatus including: test target sections each having a connector to connect a Device Under the Test (DUT); measuring sections that include measuring devices that have same measuring item respectively; a switch section that switches connection between the test target section and the measuring section under direction of a controller; wherein the controller selects one of the algorithms of connection, 1) searching vacancy of the measuring sections and directs the switch section to make a path between the test target section and the measuring section of vacancy, 2) holding the path that former selected.

Abstract: Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.

Abstract: A system and method for testing an integrated circuit using methodologies to reduce voltage drop during ATPG and LBIST testing. In one embodiment, delay elements may be added to a clock circuit used to generate the various clock signals that trigger the switching of the various electronic components. In another embodiment, logic circuitry may be added to a clock generation circuit to isolate clock domains in order to enable a clock signal in each clock domain in a specific pattern. In yet another embodiment, capture phases for LBIST testing may be made to be asynchrounous within each capture phase, such that data capture for one LBIST partition may be timed different from other capture phases for other LBIST partitions. Finally, a further embodiment ATPG circuitry may also be partitioned such that logic circuitry only enables one (or less than all) ATPG partition at a time.

Abstract: Aspects of the invention relate to techniques of using two-dimensional scan architecture for testing and diagnosis. A two-dimensional scan cell network may be constructed by coupling input for each scan cell to outputs for two or more other scan cells and/or primary inputs through a multiplexer. To test and diagnose the two-dimensional scan cell network, the two-dimensional scan cell network may be loaded with chain patterns and unloaded with corresponding chain test data along two or more sets of scan paths. Based on the chain test data, one or more defective scan cells or defective scan cell candidates may be determined.

Abstract: Performing series equivalent scans spanning a plurality of scan technologies in a complex scan topology may be performed by performing shift operations in the complex scan topology while only one branch of the complex scan topology connectivity is enabled, and performing capture and update operations in parallel while scan topology connectivity of two or more of the plurality of scan technologies is enabled.