Plural Scan Paths Patents (Class 714/729)
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Patent number: 10871518Abstract: Methods and systems for determining a systematic defect in a circuit under test is provided. Elements of the circuit under test converted into scan cells. A first scan chain that includes a first plurality of scan cells is formed. Each scan cell of the first plurality of scan cells of the first scan chain are of a first cell type. The first scan chain contains a first scan input and a first scan output. A first test pattern is applied at the scan input and a first test output is collected for the applied first test pattern at the first scan output. The collected first test output is compared with a first expected test output. The first cell type is marked to be a suspect for a systematic defect when the first test output is different from the first expected test output.Type: GrantFiled: September 12, 2018Date of Patent: December 22, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sandeep Kumar Goel, Yun-Han Lee, Ankita Patidar
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Patent number: 10855476Abstract: There is disclosed a silicon integrated circuit comprising a Physically Unclonable Function and an online or embedded test circuit, said online test circuit comprising one or more circuit parts being physically adjacent to said PUF and said one or more circuits embodying one or more tests which can be performed to determine one or more quality properties of said PUF or otherwise characterize it. Different tests with specific associated method steps are described.Type: GrantFiled: July 1, 2016Date of Patent: December 1, 2020Assignee: SECURE-IC SASInventors: Rachid Dafali, Jean-Luc Danger, Sylvain Guilley, Florent Lozac'h
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Patent number: 10845415Abstract: The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Further the disclosure provides an approach to access the TCA of a device when the device exists in a daisy-chain arrangement with other devices, such as in a customer's system. Additional embodiments are also provided and described in the disclosure.Type: GrantFiled: February 13, 2019Date of Patent: November 24, 2020Assignee: Texas Instruments IncorporatedInventor: Lee D. Whetsel
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Patent number: 10817644Abstract: The present disclosure relates to testing structures and, more particularly, to a circuit and method for design of RF integrated circuits for process control monitoring. The circuit includes a radio frequency integrated circuit comprising a plurality of active NFET devices and passive devices arranged in a single topography; and a plurality of NFET switches which are configurable to diagnose physical failures of the plurality of active NFET devices and the passive devices by isolating selected ones of the plurality of active NFET devices and the passive devices into different built-in circuit topologies by selectively turning on and off the plurality of active NFET devices and the passive devices.Type: GrantFiled: October 19, 2018Date of Patent: October 27, 2020Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Varun Gupta, Wendy Wee Yee Lau, Szu Huat Goh
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Patent number: 10796041Abstract: Systems, methods, media, and other such embodiments described herein relate to improved operation of test devices which verify circuit operations. One embodiment involves accessing a circuit design comprising a plurality of instances of one or more blocks, where each block of the one or more blocks is associated with a corresponding block test pattern comprising one or more test subpatterns. Each corresponding block test pattern is processed to identify independent test subpatterns, and then each instance is processed to identify each independent test subpattern for the circuit design. Similar types of independent test subpatterns are merged into a circuit design test pattern, such that at least two of the independent test subpatterns associated with the circuit design occupy shared test cycles within the circuit design test pattern.Type: GrantFiled: April 19, 2019Date of Patent: October 6, 2020Assignee: Cadence Design Systems, Inc.Inventors: Rajesh Khurana, Vivek Chickermane, Divyank Mittal, Balveer Singh Koranga
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Patent number: 10677844Abstract: A logic BIST circuits concurrently execute a first scan test for a scan chain as a target and a second scan test for a scan chain as a target, when they are set to a an LBIST mode, and execute the first scan test without executing the second scan test, when they are set to a simultaneous test mode. Memory BIST circuits execute a test for memory circuits concurrently with the first scan test, when they are set to the simultaneous test mode.Type: GrantFiled: April 17, 2018Date of Patent: June 9, 2020Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Iwao Suzuki, Naoki Kato
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Patent number: 10585144Abstract: A falling edge controller includes a controller having an inverted TCK (Test Clock) input, a TMS (Test Mode Select) input, a shift register control output, an update register control output, and a shift output; a shift register having a TDI (Test Data In) input, a shift register control input coupled to the shift register control output, address inputs, a select input, address and select outputs, and a TDO (Test Data Out) output; an update register having address and select inputs coupled to the address and select outputs, an update register control input coupled to the update register control output, address outputs coupled to the address inputs, and a select output coupled to the select input; and address circuitry having address inputs coupled to the address outputs, and having an enable output.Type: GrantFiled: December 20, 2018Date of Patent: March 10, 2020Assignee: Texas Instruments IncorporatedInventor: Lee D. Whetsel
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Patent number: 10387668Abstract: Embodiments provided in this disclosure include a method, computer program product, and system for protecting sensitive data in a processing system comprising a plurality of processor cores. The method includes designating at least one processor core for processing sensitive data, and during a dump event, capturing data from each of the plurality of processor cores except the designated processor core to prevent unauthorized access to sensitive data.Type: GrantFiled: July 8, 2014Date of Patent: August 20, 2019Assignee: International Business Machines CorporationInventors: Corville O. Allen, Lee N. Helgeson, Russel L. Young
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Patent number: 10372925Abstract: Embodiments provided in this disclosure include a method, computer program product, and system for protecting sensitive data in a processing system comprising a plurality of processor cores. The method includes designating at least one processor core for processing sensitive data, and during a dump event, capturing data from each of the plurality of processor cores except the designated processor core to prevent unauthorized access to sensitive data.Type: GrantFiled: December 11, 2014Date of Patent: August 6, 2019Assignee: International Business Machines CorporationInventors: Corville O. Allen, Lee N. Helgeson, Russel L. Young
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Patent number: 10371750Abstract: A method and test circuit are provided for implementing enhanced scan data testing with minimization of over masking in an on product multiple input signature register (OPMISR) test, and a design structure on which the subject circuit resides. Common Channel Mask Scan Registers (CMSR) data is used with a multiple input signature register (MISR) in each satellite. A test algorithm control is used for implementing enhanced scan data testing by independently skewing scan unload shifting of selected OPMISR+ satellite by selected cycles. With this modified shifting, for the same test or a repeated run of the test, Channel Mask Enable (CME) triggered masking lines up on a different bit position in channels of each satellite avoiding over masking.Type: GrantFiled: August 31, 2018Date of Patent: August 6, 2019Assignee: International Business Machines CorporationInventors: Steven M. Douskey, Mary P. Kusko, Matthew B. Schallhorn
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Patent number: 10324131Abstract: The present disclosure provide techniques for semiconductor testing, and more particularly, to systems and methods for laser-based fault isolation and design for testability (DFT) diagnosis techniques. In one embodiment, an integrated chip (IC) testing apparatus, includes an input pin; a decompressor connected to the input pin; a plurality of scan chains, each scan chain of the plurality of scan chains comprising a plurality of scan cells; a plurality of scan chain control elements, each scan chain control element of the plurality of scan chain control elements being connected between the decompressor and a respective scan chain of the plurality of scan chains, wherein each scan chain control element is configured to enable or disable test data from flowing from the compressor to the respective scan chain; a compressor connected to an output of each scan chain of the plurality of scan chains; and an output pin connected to the compressor.Type: GrantFiled: January 16, 2018Date of Patent: June 18, 2019Assignee: QUALCOMM IncorporatedInventors: Lesly Endrinal, Rakesh Kinger, Joseph Fang, Srinivas Patil, Lavakumar Ranganathan, Chia-Ying Chen
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Patent number: 10234503Abstract: A circuit debugging method includes: utilizing a debugging circuit to determine an operating status of a specific circuit to generate a result; utilizing a register located in a scan chain path to store the result, wherein the scan chain path is arranged for a scan test; and utilizing an output pad located in the scan chain path to output the result, wherein the result is arranged to be indicative of the operating status of the specific circuit.Type: GrantFiled: December 20, 2016Date of Patent: March 19, 2019Assignee: Realtek Semiconductor Corp.Inventors: Chun-Yi Kuo, Ying-Yen Chen, Jih-Nung Lee
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Patent number: 10222419Abstract: A method, apparatus and system are provided for the tuning of embedded subsystems of a device under test (DUT) that have analog characteristics. In response to a tester invoking one or more test procedures via a command channel between the tester and a target embedded subsystem of the DUT, test firmware of the invoked tests is loaded into the target embedded subsystem. The target embedded subsystem executes the tests under control of the tester in accordance with test parameters received from the tester over the command channel and in accordance with test commands received from the tester over a test signaling channel. The target embedded subsystem returns results of the one or more tests to the tester via the command channel. The results can be used to trim analog characteristics of the target embedded subsystem and can be stored in memory. The test firmware can then be deleted to free up memory space.Type: GrantFiled: December 21, 2016Date of Patent: March 5, 2019Assignee: Arm LimitedInventors: Daniel Lewis Cross, Brian Alan Nagel
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Patent number: 10215806Abstract: The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Further the disclosure provides an approach to access the TCA of a device when the device exists in a daisy-chain arrangement with other devices, such as in a customer's system. Additional embodiments are also provided and described in the disclosure.Type: GrantFiled: November 28, 2017Date of Patent: February 26, 2019Assignee: Texas Instruments IncorporatedInventor: Lee D. Whetsel
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Patent number: 10215807Abstract: The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Further the disclosure provides an approach to access the TCA of a device when the device exists in a daisy-chain arrangement with other devices, such as in a customer's system. Additional embodiments are also provided and described in the disclosure.Type: GrantFiled: February 9, 2018Date of Patent: February 26, 2019Assignee: Texas Instruments IncorporatedInventor: Lee D. Whetsel
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Patent number: 10110226Abstract: Exemplary method, computer-accessible medium, and test configuration can be provided for testing at least one flip-flop. For example, the exemplary test configuration can include at least one scan-out channel having a plurality of regions and a plurality of compactors associated with the plurality of regions. Further, exemplary method, computer-accessible medium, and test configuration can be provided for testing at least on flip-flop that in which at least one scan-out channel having a plurality of regions, a plurality of compactors, and associating the plurality of compactors with the plurality of regions can be provided.Type: GrantFiled: February 8, 2012Date of Patent: October 23, 2018Assignee: NEW YORK UNIVERSITYInventor: Ozgur Sinanoglu
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Patent number: 10036777Abstract: An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP of another IC. The Off Chip TAP interface can be selected by a TAP Linking Module on the IC.Type: GrantFiled: January 10, 2017Date of Patent: July 31, 2018Assignee: Texas Instruments IncorporatedInventor: Lee D. Whetsel
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Patent number: 10024914Abstract: A method and system of testing an integrated circuit (IC), using a multiple input shift register (MISR) with supporting hardware for diagnosing failure locations in an IC with built-in self-test (BIST) logic, including an On-Product MISR. The system includes BIST logic of a circuit under test (CUT) and a tester including an isolation hash table (IHT) that translates signature fail data of the MISR to a failure location of a latch in the CUT. Signature fail data, and consequently, failure locations in the CUT, are obtained by standard testing of the CUT, testing of selected single channels of the CUT, and data insertion functions to the selected single channels of the CUT to obtain compressed MISR signature changes that, when translated, provide failure locations in the CUT.Type: GrantFiled: June 29, 2016Date of Patent: July 17, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Steven M. Douskey, Amanda R. Kaufer, Leah Marie Pfeifer Pastel
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Patent number: 10018675Abstract: A programmable integrated circuit may implement a safety function in a first region and a non-safety function in a second region of the programmable integrated circuit. The safety function may require that periodic tests verify the integrity of the programmable integrated circuit during safety test intervals. For this purpose, the programmable integrated circuit may halt the operation of the safety function, partially reconfigure the first region by loading a test function, and execute the test function, while the non-safety function in the second region continues to operate. In the event that the test function executed successfully without finding any defects, the programmable integrated circuit may partially reconfigure the first region by re-loading the safety function. Additional tests may be performed if the test function detected problems with the integrity of the programmable integrated circuit.Type: GrantFiled: March 14, 2014Date of Patent: July 10, 2018Assignee: Altera CorporationInventors: Adam Titley, Roger May
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Patent number: 9966957Abstract: Embodiments of the present disclosure provide a shift register and a driving method thereof, a gate driving circuit and a display device. The shift register includes a control signal generation module, a first low level pulse generation module, a second low level pulse generation module, and a high level pulse generation module. The control signal generation module generates a first control signal and a second control signal. The first low level pulse generation module receives the first control signal and the second control signal and generate a first low level pulse signal. The second low level pulse generation module receives the first control signal and the second control signal and generate a second low level pulse signal. The high level pulse generation module receives the first control signal and generates a high level pulse signal. This shift register reduces the number of circuit elements.Type: GrantFiled: October 13, 2016Date of Patent: May 8, 2018Assignee: BOE TECHNOLOGY GROUP CO., LTD.Inventors: Can Zheng, Song Song
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Patent number: 9903912Abstract: A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection logic selects various of the components to be members of a scan chain under the direction of a host computer. The override selection logic detects a change in the scan chain and, as a result, blocks the entire scan chain from progressing.Type: GrantFiled: February 17, 2017Date of Patent: February 27, 2018Assignee: Texas Instruments IncorporatedInventors: Gary L. Swoboda, Robert A. McGowan
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Patent number: 9891282Abstract: Described is a signature accumulator with a first set of logic devices, a second set of logic devices, and a memory device. The first set of logic devices includes compaction logic that couples an N-bit input bus to a K-bit first intermediate bus. The second set of logic devices includes commutative arithmetic operation logic that couples both the K-bit first intermediate bus and a K-bit signature bus to a K-bit second intermediate bus. The memory storage device includes a storage element that couples the K-bit second intermediate bus to the K-bit signature bus. The K-bit signature bus is also coupled to a valid-data input signal path.Type: GrantFiled: December 24, 2015Date of Patent: February 13, 2018Assignee: Intel CorporationInventors: Lakshminarayana Pappu, Robert P. Adler, Suketu U. Bhatt, Robert De Gruijl, Kah Meng Yeem
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Patent number: 9797946Abstract: Embodiments of the invention provide a scan test system for an integrated circuit comprising multiple processing elements. The system comprises at least one scan input component and at least one scan clock component. Each scan input component is configured to provide a scan input to at least two processing elements. Each scan clock component is configured to provide a scan clock signal to at least two processing elements. The system further comprises at least one scan select component for selectively enabling a scan of at least one processing element. Each processing element is configured to scan in a scan input and scan out a scan output when said the processing element is scan-enabled. The system further comprises an exclusive-OR tree comprising multiple exclusive-OR logic gates. The said exclusive-OR tree generates a parity value representing a parity of all scan outputs scanned out from all scan-enabled processing elements.Type: GrantFiled: November 19, 2015Date of Patent: October 24, 2017Assignee: International Business Machines CorporationInventors: Rodrigo Alvarez-Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla, Dharmendra S. Modha, Jun Sawada
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Patent number: 9778316Abstract: Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.Type: GrantFiled: February 1, 2016Date of Patent: October 3, 2017Assignee: Mentor Graphics CorporationInventors: Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Mark Kassab, Wu-Tung Cheng
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Patent number: 9671463Abstract: A falling edge controller includes a controller having an inverted TCK (Test Clock) input, a TMS (Test Mode Select) input, a shift register control output, an update register control output, and a shift output; a shift register having a TDI (Test Data In) input, a shift register control input coupled to the shift register control output, address inputs, a select input, address and select outputs, and a TDO (Test Data Out) output; an update register having address and select inputs coupled to the address and select outputs, an update register control input coupled to the update register control output, address outputs coupled to the address inputs, and a select output coupled to the select input; and address circuitry having address inputs coupled to the address outputs, and having an enable output.Type: GrantFiled: June 10, 2016Date of Patent: June 6, 2017Assignee: Texas Instuments IncorporatedInventor: Lee D. Whetsel
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Patent number: 9632140Abstract: An integrated circuit is configured to receive a test clock input and includes circuitry configured to generate test clocks from the test clock input, and test circuitry configured to use the test clocks in a test mode.Type: GrantFiled: December 18, 2014Date of Patent: April 25, 2017Assignee: STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Anirudha Kulkarni, Jasvir Singh
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Patent number: 9612283Abstract: A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection logic selects various of the components to be members of a scan chain under the direction of a host computer. The override selection logic detects a change in the scan chain and, as a result, blocks the entire scan chain from progressing.Type: GrantFiled: June 16, 2016Date of Patent: April 4, 2017Assignee: Texas Instruments IncorporatedInventors: Gary L. Swoboda, Robert A. McGowan
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Patent number: 9557382Abstract: An integrated circuit (IC) chip includes a first circuit block, a second circuit block, an inter-block circuit and a control circuit. The first circuit block is configured to form a first scan chain to set states of flip-flops in the first circuit block. The second circuit block is configured to form a second scan chain to set states of flip-flops in the second circuit block. The inter-block circuit interfaces the first circuit block and the second circuit block. The control circuit is configured to load a first portion and a second portion of a test pattern separately to the first scan chain and the second scan chain to set states of flip-flops in the first circuit block and the second circuit block, enable a test of the inter-block circuit to capture a test result, and unload the test result from the first scan chain and the second scan chain.Type: GrantFiled: December 23, 2013Date of Patent: January 31, 2017Assignee: Marvell Israel (M.I.S.L) Ltd.Inventor: Alexander Gurtovnik
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Patent number: 9535123Abstract: A scan chain may be formed throughout an integrated circuit in which the scan chain includes at least a first segment and a second segment. A first portion of a test pattern is scanned into the first segment by clocking a first scan cell of the first segment with an even clock while clocking a remainder of the plurality of scan cells in the first segment with an odd clock, in which the odd clock is out of phase with the even clock, in which the even clock and odd clock have a rate equal to a scan rate of the test pattern divided by an integer N. A second portion of the test pattern is scanned into the second segment by clocking the plurality of scan cells in the second segment with the odd clock, such that the second portion of the test pattern is not scanned into the first segment.Type: GrantFiled: December 31, 2015Date of Patent: January 3, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Rajesh Kumar Mittal, Wilson Pradeep, Vivek Singhal
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Patent number: 9529047Abstract: IC device comprising a plurality of functional components arranged into self-test cells. The IC device is configurable into a first self-test configuration comprising a first set of self-test partitions. Each self-test partition within the first set comprising at least one self-test cell. Functional components of the self-test cell(s) of each self-test partition within the first set are arranged to be configured into at least one scan-chain for said self-test partition when the IC device is configured into the first self-test configuration. The IC device is configurable into a second self-test configuration comprising a second set of self-test partitions. Each self-test partition within the second set comprising at least one self-test cell. Functional components of the self-test cell(s) of each self-test partition within the second set are arranged to be configured into at least one scan-chain for said self-test partition when the IC device is configured into the second self-test configuration.Type: GrantFiled: August 26, 2014Date of Patent: December 27, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Markus Regner, Heiko Ahrens, Vladimir Vorisek
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Patent number: 9506985Abstract: An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.Type: GrantFiled: March 21, 2016Date of Patent: November 29, 2016Assignee: Texas Instruments IncorporatedInventor: Lee D. Whetsel
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Patent number: 9470754Abstract: Systems and methods disclosed herein provide for utilizing extra variables in the decompression equation set of an ATPG process for test patterns requiring an excess number of care bits than can be supported efficiently by the current hardware. An elastic interface is utilized between a tester and a decompressor network (e.g., sequential and combinational decompressors) in order to expand the test pattern length and/or the number of input variables. The systems and methods also provide care bits in early scan cycles of the ATPG process for sequential decompressors starting from a fixed state.Type: GrantFiled: June 11, 2015Date of Patent: October 18, 2016Assignee: Cadence Design Systems, Inc.Inventors: Vivek Chickermane, Krishna Vijaya Chakravadhanula, Brian Edward Foutz, Steev Wilcox, Paul Alexander Cunningham, David George Scott, Louis Christopher Milano, Dale Edward Meehl
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Method for using sequential decompression logic for VLSI test in a physically efficient construction
Patent number: 9470756Abstract: Methods, systems, and integrated circuits for decompressing a set of scan input data in a Design for Test (DFT) application, in which implementation may include determining a number of scan inputs to applied circuit from automated test equipment (ATE). Based on the number of scan inputs, another aspect of implementation may involve generating a 2-dimensional grid on the integrated circuit (IC). Another implementation aspect may involve decompressing the scan inputs from the ATE according to decompression logic that is sequentially distributed such that the grid can locally apply the last stage of the decompression logic. In accordance with aspects of the method, the physical structure of an IC decompression logic is more accessible to individual scan chains and reduces congestion on board the IC.Type: GrantFiled: June 12, 2015Date of Patent: October 18, 2016Assignee: Cadence Design Systems, Inc.Inventors: Steev Wilcox, Brian Edward Foutz, Krishna Vijaya Chakravadhanula, Vivek Chickermane, Paul Alexander Cunningham -
Patent number: 9417287Abstract: Operating a scan chain of a test circuit of an integrated circuit to have either a single fanout or multiple fanout to a compressor. The test circuit receives a fanout control signal for configuring the fanout of the scan chain. If the fanout control signal indicates configuring of the scan chain with a single fanout, the output of the scan chain is sent to one input of a compressor. If the fanout control signal indicates configuring of the scan chain with multiple fanout, the output of the scan chain is sent to multiple inputs of the compressor.Type: GrantFiled: April 16, 2014Date of Patent: August 16, 2016Assignee: Synopsys, Inc.Inventors: Anshuman Chandra, Subramanian B. Chebiyam, Jyotirmoy Saikia, Parthajit Bhattacharya, Rohit Kapur
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Patent number: 9372229Abstract: Functional circuits and cores of circuits are tested on integrated circuits using scan paths. Using parallel scan distributor and collector circuits for these scan paths improves test access of circuits and cores embedded within ICs and reduces the IC's power consumption during scan testing. A controller for the distributor and collector circuits includes a test control register, a test control state machine and a multiplexer. These test circuits can be connected in a hierarchy or in parallel. A conventional test access port or TAP can be modified to work with the disclosed test circuits.Type: GrantFiled: July 27, 2015Date of Patent: June 21, 2016Assignee: Texas Instruments IncorporatedInventor: Lee D. Whetsel
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Patent number: 9322875Abstract: Testing of an electrical device is achieved by providing a test access mechanism within the device that can receive scan frames from an external tester. The received scan frames contain stimulus data to be applied to circuitry within the device to be tested, a command for enabling a test control operation, and a frame marker bit to indicate the end of the scan frame pattern. The inputting of scan frames can occur continuously and simultaneous with a commanded test control operation.Type: GrantFiled: June 25, 2014Date of Patent: April 26, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Lee D. Whetsel
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Patent number: 9279848Abstract: Disclosed is a test apparatus including: test target sections each having a connector to connect a Device Under the Test (DUT); measuring sections that include measuring devices that have same measuring item respectively; a switch section that switches connection between the test target section and the measuring section under direction of a controller; wherein the controller selects one of the algorithms of connection, 1) searching vacancy of the measuring sections and directs the switch section to make a path between the test target section and the measuring section of vacancy, 2) holding the path that former selected.Type: GrantFiled: August 22, 2014Date of Patent: March 8, 2016Assignee: Sumitomo Electric Device Innovations, Inc.Inventors: Haruyoshi Ono, Isao Baba
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Patent number: 9250287Abstract: Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.Type: GrantFiled: December 15, 2014Date of Patent: February 2, 2016Assignee: Mentor Graphics CorporationInventors: Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
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Patent number: 9222974Abstract: A system and method for testing an integrated circuit using methodologies to reduce voltage drop during ATPG and LBIST testing. In one embodiment, delay elements may be added to a clock circuit used to generate the various clock signals that trigger the switching of the various electronic components. In another embodiment, logic circuitry may be added to a clock generation circuit to isolate clock domains in order to enable a clock signal in each clock domain in a specific pattern. In yet another embodiment, capture phases for LBIST testing may be made to be asynchrounous within each capture phase, such that data capture for one LBIST partition may be timed different from other capture phases for other LBIST partitions. Finally, a further embodiment ATPG circuitry may also be partitioned such that logic circuitry only enables one (or less than all) ATPG partition at a time.Type: GrantFiled: January 10, 2014Date of Patent: December 29, 2015Assignee: STMicroelectronics International N.V.Inventors: V Srinivasan, Satinder Singh Malhi, Tripti Gupta
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Patent number: 9222978Abstract: Aspects of the invention relate to techniques of using two-dimensional scan architecture for testing and diagnosis. A two-dimensional scan cell network may be constructed by coupling input for each scan cell to outputs for two or more other scan cells and/or primary inputs through a multiplexer. To test and diagnose the two-dimensional scan cell network, the two-dimensional scan cell network may be loaded with chain patterns and unloaded with corresponding chain test data along two or more sets of scan paths. Based on the chain test data, one or more defective scan cells or defective scan cell candidates may be determined.Type: GrantFiled: March 9, 2012Date of Patent: December 29, 2015Assignee: Mentor Graphics CorporationInventors: Yu Huang, Wu-Tung Cheng, Ruifeng Guo, Manish Sharma, Liyang Lai
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Patent number: 9213061Abstract: An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than conventional JTAG interfaces on an integrated circuit where the availability of pins is limited. The interface may be used for a variety of serial communication operations such as, but not limited to, serial communication related integrated circuit test, emulation, debug, and/or trace operations.Type: GrantFiled: September 24, 2014Date of Patent: December 15, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Lee D. Whetsel
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Patent number: 9188643Abstract: Aspects of the invention provide for a flexible performance screen ring oscillator (PSRO) integrated within a scan chain. In one embodiment, a circuit structure to create the flexible PSRO includes: a plurality of programmable scan chain elements; and a forward test scan chain path through the plurality of scan chain elements; wherein each of the programmable scan chain elements includes additional circuitry for a backward path, such that the backward path and the forward test scan chain path are combined to create the PSRO.Type: GrantFiled: November 13, 2012Date of Patent: November 17, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Margaret R. Charlebois, Christopher D. Hanudel, Robert D. Herzl, David W. Milton, Clarence R. Ogilvie, Paul M. Schanely, Tad J. Wilder
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Patent number: 9183924Abstract: Methods of operating nonvolatile memory devices may include identifying one or more multi-bit nonvolatile memory cells in a nonvolatile memory device that have undergone unintentional programming from an erased state to an at least partially programmed state. Errors generated during an operation to program a first plurality of multi-bit nonvolatile memory cells may be detected by performing a plurality of reading operations to generate error detection data and then decoding the error detection data to identify specific cells having errors. A programmed first plurality of multi-bit nonvolatile memory cells and a force-bit data vector, which was modified during the program operation, may be read to support error detection. This data, along with data read from a page buffer associated with the first plurality of multi-bit nonvolatile memory cells, may then be decoded to identify which of the first plurality of multi-bit nonvolatile memory cells are unintentionally programmed cells.Type: GrantFiled: May 15, 2015Date of Patent: November 10, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-Sang Lee, Moosung Kim, Kihwan Choi
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Patent number: 9164146Abstract: The disclosure describes a novel method and apparatus for providing a shadow access port within a device. The shadow access port is accessed to perform operations in the device by reusing the TDI, TMS, TCK and TDO signals that are used to operate a test access port within the device. The presence and operation of the shadow access port is transparent to the presence and operation of the test access port. According to the disclosure, the shadow access port operates on the falling edge of the TCK signal while the test access port conventionally operates on the rising edge of the TCK signal.Type: GrantFiled: November 17, 2014Date of Patent: October 20, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Lee D. Whetsel
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Patent number: 9110142Abstract: Embodiments include systems that include at least one integrated circuit (IC) and methods for their testing. Each IC includes an input interconnect to receive an input signal, a test enable interconnect to receive a test enable signal, and a controller (e.g., a TAP controller) for performing testing of the integrated circuit based on values in at least one register (values corresponding to the input signal). Each IC also includes an input port and a multiplexer coupled to the first input interconnect, the at least one register, and the input port. The multiplexer is controllable to pass the input signal to the input port in response to non-assertion of the test enable signal, and to pass the input signal to the at least one register in response to assertion of the test enable signal. When the system includes multiple controllers, each controller may implement a different opcode-to-instruction mapping.Type: GrantFiled: September 30, 2011Date of Patent: August 18, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Michael E. Stanley, Joseph S. Vaccaro
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Patent number: 9103879Abstract: An apparatus and method is provided for switching input pins to scan channels to increase test coverage. In one embodiment, a scan system connects a small number of input pins to several scan channels so that the input pins may be selectively switched. The input pins may transmit independent test vectors to test a large number of test areas on a semiconductor chip. The scan system may include a switching device such as a multiplexer (MUX).Type: GrantFiled: February 27, 2013Date of Patent: August 11, 2015Assignee: International Business Machines CorporationInventors: Steven M. Douskey, Ryan A. Fitch, Michael J. Hamilton, Amanda R. Kaufer
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Patent number: 9097763Abstract: Plural scan test paths (401) are provided to reduce power consumed during testing such as combinational logic (101). A state machine (408) operates according to plural shift states (500) to control each scan path in capturing data from response outputs of the combinational logic and then shifting one bit at a time to reduce the capacitive and constant state power consumed by shifting the scan paths.Type: GrantFiled: October 17, 2013Date of Patent: August 4, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Lee D. Whetsel
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Patent number: 9091729Abstract: Electronic scan circuitry includes a decompressor (510), a plurality of scan chains (520.i) fed by the decompressor (510), a scan circuit (502, 504) coupled to the plurality of scan chains (520.i) to scan them in and out, a masking circuit (590) fed by the scan chains (520.i), and a scannable masking qualification circuit (550, 560, 580) coupled to the masking circuit (590), the masking qualification circuit (550, 560, 580) scannable by scan-in of bits by the decompressor (510) along with scan-in of the scan chains (520.i), and the scannable masking qualification circuit (550, 560, 580) operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit (590). Other scan circuitry, processes, circuits, devices and systems are also disclosed.Type: GrantFiled: September 16, 2014Date of Patent: July 28, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Prakash Narayanan, Arvind Jain, Sundarrajan Subramanian, Rubin A. Parekhji
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Patent number: 9088522Abstract: Disclosed are representative embodiments of methods, apparatus, and systems for test scheduling for testing a plurality of cores in a system on circuit. Test data are encoded to derive compressed test patterns that require small numbers of core input channels. Core input/output channel requirement information for each of the compressed test patterns is determined accordingly. The compressed patterns are grouped into test pattern classes. The formation of the test pattern classes is followed by allocation circuit input and output channels and test application time slots that may comprise merging complementary test pattern classes into clusters that can work with a particular test access mechanism. The test access mechanism may be designed independent of the test data.Type: GrantFiled: January 17, 2012Date of Patent: July 21, 2015Assignee: Mentor Graphics CorporationInventors: Janusz Rajski, Mark A Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Jakub Janicki, Jerzy Tyszer, Avijit Dutta
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Patent number: RE47864Abstract: Performing series equivalent scans spanning a plurality of scan technologies in a complex scan topology may be performed by performing shift operations in the complex scan topology while only one branch of the complex scan topology connectivity is enabled, and performing capture and update operations in parallel while scan topology connectivity of two or more of the plurality of scan technologies is enabled.Type: GrantFiled: July 19, 2013Date of Patent: February 18, 2020Assignee: Texas Instruments IncorporatedInventor: Gary L. Swoboda