Abstract: A new built-in self-test circuit device for testing an embedded memory array is achieved. The device comprises a pattern generator unit that executes a testing sequence to automatically write and read locations in an embedded memory. A comparison unit compares data read from the embedded memory and expected data provided by the pattern generator. An error signal is turned ON by the comparison unit when the data read does not match the data provided. An error release unit generates an error stop signal. The error stop signal is turned ON when the error signal is turned ON. The pattern generator unit testing sequence is stopped when the error stop signal is turned ON and is re-started when the error stop signal is turned OFF. The error stop signal is turned OFF when an external device asserts an error release signal.

Abstract: A method of manufacturing a device having embedded memory including a plurality of memory cells. During manufacturing test, a first test stress is applied to selected cells of the plurality of memory cells with a built-in self test. At least one weak memory cell is identified. The at least one weak memory cell is repaired. A second test stress is applied to the selected cells and the repaired cells with the built-in self test.

Abstract: A method for authorizing the rendering of a digital recording. A first section and a last section of a track is first identified. A watermark is then decoded from the first and last sections of the track. It is then determined if at least one reserved bit is marked in the watermark in each of the first and last sections of the track. If so, it is determined if the sequence IDs of sections interposed between the first and last sections of the track are in sequential order. If both conditions are met, the rendering is authorized.

Abstract: A circuit configuration for testing a circuit using a test device for providing a test mode, where test procedures are performed sequentially. The test procedures involve comparing actual data that are output by the circuit under test with prescribed nominal data in the test device. A combinational logic device for logically combining the sequentially output test results is provided such that result data indicate fault free operation of the circuit under test only if the actual data which are output match the prescribed nominal data in all of the sequentially performed test procedures. The result data is output via an addressing and control unit in the circuit under test.

Abstract: A failure analysis system of a logic LSI incorporates software therein. The analysis system includes a function to record the terminal signal information of said logic LSI in synchronization with a clock and a function to reproduce said recorded terminal signal information in synchronization with the clock. The analysis system further includes a function to compare said reproduced terminal signal information with the terminal signal information of a normal logic LSI.

Abstract: A virtual environment browser (64) holds a number of clip-in files (70, 72, 74) defining guide characters—locally generated visual aids to navigation that appear within a generated image of a virtual environment and follow a user's input (80) navigational commands to provide an advance cue as to the effects of an input command. Where the virtual environment data is supplied from a remote source (62) and includes (78) an indication of a preferred mode for navigating that environment, for example, flying or walking, the browser (64) detects this indication and automatically selects the appropriate guide character. Scaling (84) of the guide character to match the scale of the virtual environment, or such as to render the guide character unobtrusive, may also be provided.

Abstract: One embodiment of the present invention provides a technique for detecting anomalies during operation of a test computer system. Initially, a golden system and the test system are equipped with the same hardware configuration, wherein the golden system has gone through extensive qualification testing and is presumed to be operating correctly. Next, a deterministic load is executed on the golden system, and values for performance parameters from the golden system are monitored while the deterministic load is executing. Similarly, the deterministic load is also executed on the test system, and values for performance parameters from the test system are monitored while the deterministic load is executing. Next, pairwise differences are computed between values for performance parameters received from the test system and values for performance parameters received from the golden system.

Abstract: In a test system, a test method, and a program for use in verifying states in a target, a predetermined state is previously defined as an intermediate state among states which can be taken by the target. On causing a transition to occur in the target from a previous state to a next following state, the transition is caused to occur in the target from a previous state to the intermediate state. Then, the target makes the transition from the intermediate state to the next following state. For this purpose, the test system stores intermediate state transition procedures from the previous state to the intermediate one and a self-state transition procedure from the intermediate state to the next following state.

Abstract: The invention provides a test device for testing circuit units (101a–101n) to be tested, having connecting units (106a–106n) for connecting the circuit units (101a–101n) to be tested to the test device, a test system (100) and an output unit (108) for outputting test result data, the test device having a determining unit (103) for determining those of the measurement data (110a–101n) which correspond for a predeterminable number of circuit units (101a–101n) to be tested, and for defining the corresponding measurement data (110a–110n) as the expected data (111); and comparison units (104a–104n) for comparing the measurement data (110a–110n) generated by the circuit units (101a–101n) to be tested in a manner dependent on the test data (112) written in with the expected data (111) in order to obtain comparison data (115a–115n).

Abstract: An apparatus and a method for testing memory of a computing device, and more specifically to testing a Central Processing Unit (CPU), a system memory, and a combination thereof. The computing system includes one or more CPUs, a system memory, input and output devices. Among other features, the apparatus and method described herein can remove either a defective CPU or a defective portion of system memory from the computing device. An exemplary apparatus and method also reports to a computer user whether any CPU or system memory is defective as well as specifically identifying the defective computing component. The apparatus and method also detects a first defect related to a first corrupted portion of an instruction of a test program code and a second defect related to a second corrupted portion of the instruction.

Abstract: A testing system or method compares read data from one or more dies in a semiconductor wafer with the original data written onto the one or more dies The testing system includes one or more write registers connected to one or more dies on the semiconductor wafer. One or more comparators are connected to the dies and the write registers. The comparator generates a result in response to the original data and the read data.

Abstract: Methods and systems for reducing the volume of test data associated with built in self testing (BIST) test methodologies (e.g., logical BIST, array BIST, etc.) and pattern structures are provided. Embodiments of the present invention store a limited number of “dynamic” test parameters for each test sequence that have changed relative to a previous test sequence.

Abstract: A signature circuit, i.e., a random-number generating circuit, is provided in a memory test apparatus. Also, a signature circuit is provided in each of devices-under-test. This configuration allows the large number of semiconductor integrated-circuit devices to be tested at one time with a high efficiency. This condition realizes a tremendous reduction in the test cost.

Abstract: Circuit implementations and test methods enable the testing of lookup table (LUT) input paths, “stuck at” memory cell values, and carry chains. One method includes storing a first bit pattern in each LUT, configuring the carry chain to perform a wide AND function of the LUT outputs, and cycling the inputs of each LUT while comparing the carry chain output to an expected value and reporting the PLD faulty if a difference is detected. The carry chain is configured to perform a wide OR function, and the cycling step is repeated. The bit pattern within each LUT is changed to the complement of the first bit pattern by providing a series of shift commands or by otherwise storing new values in the LUT, and the configuring and cycling steps are repeated. The invention also provides PLD circuit implementations that can be used to perform the described methods.

Abstract: An integrated circuit device includes a data buffer, coupled to an external connector, providing a data signal on the external connector. A test buffer, coupled to the data buffer, receives the data signal and provides a testing output signal to a delay circuit. The delay circuit receives the testing output signal at a first clock rate internal to the integrated circuit device and compares test data in the testing output signal to expected test signal values. The delay circuit provides a result to an external connector at a second clock rate that is slower than the first clock rate.

Abstract: A semiconductor device carries out a test utilizing contact with a probe needle without being affected by narrowing of the pitch at which output pads are arranged. The device is equipped with test circuits provided between a plurality of output buffers via which signals are output and output pads corresponding thereto. The test circuit includes output switches caused to sequentially make connections by a controller in test and interpad switches involved in making connections of the output pads with a test pad by the controller in test. In test, probe needles are brought into contact with the test pad. The output pads are not used in test, and can be arranged at a narrowed pitch. Thus, the chip area can be reduced and are therefore so that the pitch for the output pads can be narrowed and the chip area can be decreased.

Abstract: A method for design validation of complex IC with use of a combination of electronic design automation (EDA) tools and a design test station at high speed and low cost. The EDA tools and device simulator are linked to the event based test system to execute the original design simulation vectors and testbench and make modifications in the testbench and event based test vectors until satisfactory results are obtained. The event based test vectors are test vectors in an event format in which an event is any change in a signal which is described by its timing and the event based test system is a test system for testing an IC by utilizing the event based test vectors. Because EDA tools are linked with the event based test system, these modifications are captured to generate a final testbench that provides satisfactory results.

Abstract: The program-controlled unit, during the execution of the program, can switch itself to a state in which selected elements that can be connected to form scan chains or all of the elements can no longer change their state, according to a predetermined result. If these elements are then connected to form a scan chain and read out, the data obtained as a result can be used to identify and/or analyze any errors existing in the program-controlled unit rapidly and reliably.

Abstract: The present invention provides an apparatus and a method for testing one or more electrical components. The apparatus and method execute similar portions of a test segment on a known device, i.e., a device for which it has been determined that the test segment executes successfully, and on a device-under-test (DUT), i.e., a device for which it has been determined that the test segment does not execute successfully. The results of the tests are compared to determine if the test passed or failed. The test segment is executed iteratively on the known device and the DUT, increasing or decreasing the amount of the test segment that is executed each pass until the failing instruction is identified.

Abstract: A signal-analyzing unit has a sampling path and a reference path both receiving a digital test signal. The sampling path has a first comparator for comparing the test signal against a first threshold value and providing a first comparison signal, and a first sampling device receiving as input the first comparison signal and a first timing signal. The reference path has a second comparator for comparing the test signal against a second threshold value and providing a second comparison signal, and a second sampling device for receiving as input the second comparison signal and a second timing signal. An analysis unit receives and analyzes the output of the sampling and reference paths.

Abstract: A technique of logically processing bit maps and character maps describing the attributes and values of computer variable ranges and a variable being tested to determine if a match exists between the variable and one or more ranges. Bit maps define the attributes of each character position of variables and ranges; character maps define which character positions are constrained to a fixed character for each of the ranges. This quick and efficient method of logical processing of maps replaces the known method of examining each character position of a variable individually.

Abstract: Method and apparatus are described for duty cycle determination and adjustment. More particularly, an output signal is sampled and provided to duty cycle check circuitry which characterizes the duty cycle of the sampled output signal. This characterization may be provided to a wafer prober or integrated circuit tester to determine whether duty cycle is within an acceptance range. Alternatively, the duty cycle indicator signal may be provided to drive adjustment circuitry. In response to duty cycle not being within an acceptance range, drive adjust circuitry provides a drive adjustment signal to adjust duty cycle at an output buffer by turning on one or more p-channel drive transistors, one or more n-channel drive transistors, or a combination of both. Moreover, wells may be biased responsive to a detected duty cycle in order to correct the duty cycle.

Abstract: A method of generating a truncated scan test pattern for an integrated circuit design includes steps of: (a) receiving as input an integrated circuit design; (b) estimating a number of transition delay fault test patterns and a corresponding number of top-off stuck-at fault patterns to achieve maximum stuck-at fault and transition delay fault coverage; (c) truncating the estimated number of transition delay fault patterns to generate a truncated set of transition delay fault patterns so that the truncated set of transition delay fault patterns and the corresponding number of top-off stuck-at fault patterns achieve maximum stuck-at fault and transition delay fault coverage within a selected scan memory limit; and (d) generating as output the truncated set of transition delay fault patterns and the corresponding number of top-off stuck-at fault patterns.

Abstract: A method for functional verification of hardware design. First, a first memory region storing a test pattern and a second memory region storing interrupt instructions are provided. Then, the test pattern stored in the first memory is hardware-simulated. If an external interrupt is received during the simulation of the test pattern, the second memory region is accessed and the interrupt instructions are hardware-simulated. Thereafter, the simulated result of the interrupt instructions is self-tested to obtain a first verification result, and the hardware design is verified according to the first verification result.

Abstract: A digital bus monitor used to observe data on a bus (14, 16, 18) connecting multiple integrated circuits (10, 12) comprises a memory buffer (30), bypass register (34), test port (38) and output control circuits (42, 46) controlled by an event qualifying module (EQM) (32). In response to a matching condition the EOM (32) may perform a variety of tests on incoming data while the integrated circuits (10, 12) continue to operate at speed. A plurality of digital bus monitors (20, 22) may be cascaded for observation and test of variable width data buses and variable width signature analysis.

Abstract: A logic circuit comprising a flip-flop chain circuit which is utilized in a scan test of a combinational circuit, the flip-flop chain circuit including a plurality of flip-flops each of which is provided with a selector.

Abstract: A nonvolatile semiconductor memory device has a special test mode and circuitry for counting its own fail bits. During the test mode, test data is stored in the memory, and also in a special expected data buffer. The test data stored in the memory cells are then compared to that stored in the expected data buffer. Where there is no correspondence, fail bits are detected. The lack of correspondence is registered, counted, and output to a data output buffer block.

Abstract: A digital bus monitor used to observe data on a bus (14, 16, 18) connecting multiple integrated circuits (10, 12) comprises a memory buffer (30), bypass register (34), test port (38) and output control circuits (42, 46) controlled by an event qualifying module (EQM) (32). In response to a matching condition the EQM (32) may perform a variety of tests on incoming data while the integrated circuits (10, 12) continue to operate at speed. A plurality of digital bus monitors (20, 22) may be cascaded for observation and test of variable width data buses and variable width signature analysis.

Abstract: A digital bus monitor used to observe data on a bus (14, 16, 18) connecting multiple integrated circuits (10, 12) comprises a memory buffer (30), bypass register (34), test port (38) and output control circuits (42, 46) controlled by an event qualifying module (EQM) (32). In response to a matching condition the EQM (32) may perform a variety of tests on incoming data while the integrated circuits (10, 12) continue to operate at speed. A plurality of digital bus monitors (20, 22) may be cascaded for observation and test of variable width data buses and variable width signature analysis.

Abstract: An architecture that provides stimulus data and verifies the response of multiple electronic circuits substantially in parallel for optimized testing, debugging, or programmable configuration of the circuits. The architecture includes a test bus, a primary test controller connected to the bus, and a plurality of local test controllers connected to the bus, in which each local test controller is coupleable to a respective circuit. The primary test controller sends stimulus data and expected response data over the bus to the respective local test controllers to perform parallel testing, debugging or programmable configuration of the circuits. Each local test controller applies the stimulus data and verifies the circuit response against the expected response data. Further, each local test controller stores the result of the verification for later retrieval by the primary test controller.

Abstract: Method and apparatus are disclosed for checking the resistance of antifuse elements in an integrated circuit. A voltage based on the resistance of an antifuse element is compared to a voltage based on a known resistance, and an output signal is generated whose binary value indicates whether the resistance of the antifuse element is higher or lower than the known value of resistance. The method and apparatus are useful in verifying the programming of antifuse elements.

Abstract: A method of recording test information to identify a location of errors in Integrated Circuits (ICs) includes scanning a plurality of ICs with an input signal, each IC having a plurality of data locations and comparing an output response at each data location with an expected value for the data location. The method also includes storing an address in a buffer for each data location where the response at the data location does not equal the expected value corresponding to the data location.

Abstract: The invention relates to a method and an installation for fast location of a fault in an integrated circuit. A sequence of NRZ location vectors is created, the abnormal location vectors are determined, for which the value of the electrical consumption current at rest IDDQ of the circuit is abnormal, at least one set of images is produced with an abnormal location vector, and at least one abnormal vector image is compared with a reference image.

Abstract: A memory test circuit includes a collar for coupling to a memory device for switching an address bus and a data bus of the memory device between an external circuit and the collar in response to a switching signal; and a controller coupled to the collar for generating the switching signal, a test vector, and control signals between the controller and the collar on as few as seven control lines for testing the memory device with the test vector. Multiple memory devices of various sizes may be tested with the same controller concurrently.

Abstract: The present disclosure describes a technique for debugging an integrated circuit having a parallel scan-chain architecture. Blocking circuits are introduced at the inputs and/or outputs of scan-chain branches. The blocking circuits allow the inputs to and/or the outputs from the scan-chain branches to be selectively blocked. This allows individual scan-chain branches to be isolated and debugged.

Abstract: A test pattern generation and comparison circuit creates test pattern stimulus signals for and evaluates response signals from logic or memory such as random access memory (RAM). It utilizes both parallel and serial interfaces to the logic/memory under test. The test pattern generation and comparison circuit further provides a method for testing logic and memory utilizing built-in self test (BIST) techniques. The method uses a programmable logic/memory commands which are translated into physical logic signals and timings for the logic or memory under test. The results of the test pattern generated and applied to the logic or memory are compared to expected results. The result of the comparison is a pass/fail designation. In addition, the comparison of the expected test results with the actual test results provides information on the exact location of the failure.

Abstract: A memory system includes a memory controller and a bank of memory devices. The memory controller controls the memory devices through packets of control data and a master clock signal. Each of the memory devices includes an adjustable output timing vernier that can be adjusted in response to commands from the memory controller. The vernier output controls timing of output data relative to the master clock signal. As each memory device transmits data to the memory controller, the memory device also transmits an echo clock signal coincident with the data. The memory controller receives the echo clock signal and compares the echo clock signal to the master clock signal to identify shifts in timing of the echo clock signal. If the echo clock signal shifts by more than one vernier increment from the master clock signal, the master controller issues a command to the memory device to adjust the output vernier to correct the timing drift of the echo clock signal.

Abstract: An apparatus and method of disconnecting or disabling an input/output terminal of an integrated circuit after packaging. Each input/output terminal of the integrated circuit includes a disabling device coupled thereto between the input/output terminal and the output driver of the respective input/output terminal. A DRAM module is disclosed having a plurality of partially good DRAM devices wherein the known bad input/output terminals are permanently disconnected using a disabling device, both the known good and known bad input/output terminals being coupled to conductive traces of a carrier substrate.

Abstract: A method of testing a semiconductor device having a memory is disclosed. The method includes selecting a portion of the memory; testing the selected portion of the memory; designating the selected portion of the memory as a designated memory in response to an acceptable testing result; and storing data in the designated portion of the memory for retrieval at a later time. Provision for soft repair of the selected memory is made. Test data can be compressed before being stored in the designated memory.

Abstract: A hardware verification method includes obtaining a set of packets to be driven by a device under test and obtaining a set of timing and relation criteria which determines a sequence in which the packets should be driven by the device under test. The method further includes starting multiple drive loops, each drive loop picking up a packet and forcing the device under test to drive the packet. The method further includes starting multiple expect loops, each expect loop determining when to expect a packet driven by the device under test and picking up the expected packet when it arrives. For each drive loop, the method confirms that the timing and relation criteria are satisfied prior to allowing the drive loop to force the device under test. For each expect loop, the method checks if the expected packet arrives within a specified time period and raises an error flag if the expected packet does not arrive within the specified time period.

Abstract: The functionality of a programmable memory built-in self-test (BIST) arrangement for testing an embedded memory structure of an integrated circuit is extended to system level testing to ascertain operability of the system after the integrated circuits and boards including them have been placed in service in larger systems, by generating default test signals which are loaded in an instruction store module when test instructions are not provided from an external tester. This additional utility of the BIST arrangement, increases efficiency of chip space utilization and improves the system level test. Loading of test instructions from an external tester during chip manufacture and/or board assembly is unaffected.

Abstract: Disclosed is a system for inferring faulty locations in a combinational logic circuit by tracing a fault propagation path from a faulty terminal through repetition of logic decisions and implications. The system infers a logic state by repeating logic state decisions and implications and comparing the logic state with an expected value, which corresponds to a normally operating logic state, thereby inferring a fault propagation path in the logic circuit.

Abstract: A method and apparatus for providing a system-on-a-chip comprising a processor and a configurable system logic (CSL) including a plurality of banks arranged in an array coupled to the processor. The system on a chip further includes a built-in self test (BIST) mechanism coupled to the CSL to perform tests on the CSL to verify that the banks and interconnections between the banks are functioning properly.

Abstract: A receiver circuit for a tester for electronic devices is provided. The receiver circuit includes a clock receiver that is adapted to receive a source synchronous clock signal from a device under test. The receiver circuit further includes a data receiver that is responsive to the clock circuit. The data receiver is adapted to receive at least one differential data signal from the device under test. The receiver circuit also includes a trigger receiver that is responsive to the clock circuit. The trigger receiver is adapted to receive a trigger signal from the device under test. Finally, the receiver circuit includes a control circuit that is coupled to the trigger receiver. The control circuit is adapted to generate a start alignment capture signal based on the received trigger signal to initiate capture of data received at the data receiver for comparison with expected values.

Abstract: A method tests an electronic component, especially a memory chip, which is connected to a computer system. Initially, test patterns and AC-/DC-parameters are read into the computer system. Then, the computer system generates an input test pattern for the electronic component. Afterwards, a simulation process is performed processing the input test pattern by the electronic component and measuring the current flowing in the electronic component. Ultimately, the method produces a statement concerning the functionality of the tested electronic component. Program instructions for causing a computer system to perform the above-described method for testing an electronic component can be stored in a computer program, a computer readable medium, a computer memory, a read-only memory, an electrical carrier signal, and a carrier, especially a data carrier. A computer system runs the computer program embodying the method.

Abstract: An SRAM efficient ATE system that performs high speed nested loops without constraints on loop size or modularity and that loops and/or branches from any vector in a multiple vector accessed word to any vector in another multiple vector accessed word without incurring any time displacement. In one embodiment, the maximum required vector rate is less than or equal the average sustained data rate of the SDRAM and is less than or equal to the maximum access rate of the dual port SRAM's memory B. The output of the SDRAM's memory A consists of one control word and one vector (nV=1). The I/O port widths of the SRAM's memory B are the same. In another embodiment, the maximum required vector rate is greater than the average sustained data rate of the SDRAM's memory A, but is equal to or less than the maximum access rate of the SRAM's memory B. The output of the SDRAM's memory A consists of multiple control words and vectors. The input port of the SRAM's memory B is some multiple of the output port width.

Abstract: A range recognizer applies acquired data to the inputs of a plurality of boundary comparators simultaneously, treating an entire range of values for the data as a single continuum which is partitioned by a series of internal boundaries that are monitonically increasing. Each boundary comparator compares the value of the data with its unique boundary value and provides the results to a single range encoder logic to generate a single binary word as an encoded result indicative of the comparison for the entire range. An upper boundary result of one boundary comparator is combined with a lower boundary result of an adjacent higher boundary comparator prior to input to the single range encoder logic. The result is a reduction In the number of output pins required on an integrated circuit (IC) for reporting the encoded result for a corresponding plurality of range recognizers.

Abstract: Testing of an electronic component (1) in which a signal (S1) is sent to a cell (3) of the component, and the output signal (S2) of this component is studied so as to define whether the component is acceptable or not. If the component is acceptable the test is performed again by sending a signal (S1′) similar to the first signal but with a shorter duration (T2). A search is then made for an output signal (S2′) to be compared with a compressed expected pattern. If this test, which is performed more rapidly, is valid, it can be planned, if necessary, to use this faster input signal on following components to be tested.

Abstract: A system and method for time slicing deterministic patterns for reseeding in logic built-in self-test (BIST). The known properties of a linear feedback shift register (LFSR) and an associated set of channels are used in conjunction with a desired deterministic test pattern to create one or more seeds which can be used by the LFSR to generate the test pattern. The test pattern is divided into a number of segments, with each segment having a specific number of “care” bits. The number of shifts required to fill a segment using a particular seed is stored along with the seed as a seed lifetime. During testing, each deterministic test pattern is generated by loading a seed into the LFSR and cycling the LFSR in accordance with the lifetime of the seed. The seed lifetimes may have different values, and multiple seeds may be used in the generation of a single test pattern, or a single seed may be used to generate care bits of multiple test patterns.

Abstract: Systems for performing time domain measurements of a device under test (DUT) are provided. One such system includes a normalization system that receives information corresponding to a model of a test system used for providing differential input signals to a DUT, receives information corresponding to first and second differential input signals provided to the DUT, receives information corresponding to first and second reflected waveforms corresponding to the DUT response to the first and second differential input signals, and computes first and second normalized waveforms using at least a first inverse transfer function of the test system, the first and second normalized waveforms including fewer test system error components than the first and second reflected waveforms, respectively. Methods, computer-readable media and other systems also are provided.