Abstract: The invention relates to a method for monitoring the execution of a program in a microcomputer of an electronic device, especially a sensor circuit for motor vehicles. According to the inventive method, the program processes input data and produces output data, copies a program in addition to the program which is executed, said copy being stored in an address area in the micro-computer other than the program, using the input data provided for the program. The output data of the copy is compared to the data of the program and an error message is produced if the programs are not consistent.

Abstract: Since fault detection is not conducted for the address other than the noted address or the expected value other than the noted expected value in the RAM test, generation of a fault can be discriminated easily for the predetermined noted address or noted expected value when a fault is detected. Moreover, since the noted address is set as a single address but as the predetermined address range, when a fault is generated after the test for the relevant address range, the total number of times of test can be controlled by conducting the screening test for the address range where a fault is generated.

Abstract: A unit test extending system and method use a unit test extender engine and a test pattern to extend a unit test written to validate code under test. The unit test has a first function configured to return a single hard coded value to the code under test. A test pattern database stores test patterns for different hard coded value data types. The unit test extender engine identifies a data type of the hard coded value of the first function in the unit test and retrieves one of the test patterns from the test pattern database. The engine then automatically calls the first function in the unit test a plurality of times, each time returning a different one of a plurality of different values in the retrieved test pattern in order to automatically extend the unit test.

Abstract: We describe, in exemplary embodiments, an on-chip Functional Built-In Self Test (“FBIST”) mechanism for testing integrated circuits with internal memory state and complex transaction based interfaces. Such interfaces include system-on-chip applications, memory chip applications, and input/output (“IO”) protocol adapter chips.

Abstract: A method to reduce logic built in self test manufacturing test time of integrated circuits, comprising: loading a plurality of test seeds in bulk into a locally accessible on-chip memory array locally disposed on an integrated circuit, each of the plurality of test seeds is associated with a set of LBIST control information; sending the plurality of test seeds from the locally accessible on-chip memory array repetitively into a pseudo-random pattern generator one at a time during an LBIST operation being under the control from the set of LBIST control information; generating random bit streams serially into a plurality of parallel shift registers of the integrated circuit through the use of the plurality of test seeds; and performing a logic built-in self test on a plurality of logic blocks in the integrated circuit to detect defects within the integrated circuit.

Abstract: An extracting unit extracts unprocessed capturing destination in a circuit. A tracing unit traces an output branch point from a capturing destination and a determining unit determines an estimated failure site and a non-failure site in the circuit. A detecting unit narrows down an estimated failure site using a fail address. It is determined whether an identifying unit has identified a failure site. If the failure site has not been identified, a delay failure simulation is performed and a comparing unit compares the comparison result of the tester measurement and the result in the delay failure simulation to determine consistency between the results. The identifying unit identifies the failure site based on the consistency.

Abstract: The on-chip data transmission controller comprises a data comparison unit for comparing current data with previous data and issuing an inversion flag if the number of data bits phase-transited is larger than a preset number, a first data inversion unit for inverting a phase of the current data when the inversion flag is activated and providing inverted data onto a data bus, and a second data inversion unit for inverting a phase of the data transmitted via the data bus when the inversion flag is activated and outputting inverted data. Through this controller, an on-chip noise that largely occurs as the number of data to be transmitted increases can be reduced, by decreasing transition number of data inputted via the GIO line, in case of using a multi step pre-patch structure to improve an operation speed of a memory device.

Abstract: Methods and systems provide for early and simplified testing for defects in the interconnects of a programmable logic device (PLD) and in associated software tools. Data that describes the interconnects are read from a database for the PLD. For each interconnect, a respective test design is automatically generated with the test design replacing a portion of a coupling between an input pad and an output pad in an archetypal test design with a coupling that includes the interconnect. A respective configuration is automatically generated for the PLD from each test design. A respective operation of the PLD programmed with each configuration is simulated, and each operation of the PLD for is checked inconsistency with an expected result. In response to any inconsistency, an indication of the inconsistency is displayed to a user.

Abstract: A microprocessor simulation method, which is built upon the underlying hardware design of the microprocessor, stop normal functions of a simulation testcase, start the scan clocks, and record a first “snap shot” of the scan ring data at an initial time. The hardware logic then rotates (shifts) the scan ring using the current scan data, and when the scan clock stops (where the stop of the scan clock is controlled based on the number of latches on the scan ring), another “snap shot” of scan ring data is taken. The “snap shots” are compared and if both of the “snap shots” are identical the functional scan is successful. But if the functional scan verification fails to rotate the scan chain correctly, that is, if some of the latches do not match in the two “snap shots,” it becomes necessary to locate the broken spot within the large number of scan latches.

Abstract: A data storage system includes a storage processor that is configured to perform load and store operations on a storage array on behalf of external devices. The data storage system also includes a controller that isolates communication between the external devices when coupled to the storage array via the storage processor. The controller further maintains a set of registers that store information associated with the data storage system and allows the storage processor to access the register via an I2C bus. The system utilizes an error detection procedure to allow detection of errors in the data transmitted between the controller and the storage processor. During operation, a checksum value is transmitted between the controller and the storage processor using the I2C bus during a register write or read procedure. The controller and the storage processor utilize the checksum value in an error detection procedure to detect the data errors resulting in transmission of the data by the I2C bus.

Abstract: An integrated circuit with a multiplexer system and a control circuit is described. The multiplexer system has an output terminal connected to an output pin of the integrated circuit and input terminals connected to internal nodes of the integrated circuit. In a normal mode the control circuit generates the control signals so that any one of the internal nodes is connected to the output pin so that the integrated circuit can function flexibly. In a test mode so that a different internal node is connected to the output pin in each cycle of a test clock signal.

Abstract: An integrated scannable interface for testing memory. The interface includes a selection device for selecting a signal from at least two input signals responsive to an activation signal, a first storage device coupled to the output of the selection device for storing the signal responsive to a first enable signal and generating an output signal for the memory. The first storage device is connected at the input node of the memory, and a second storage device is coupled at its input to the first storage device for storing the output signal responsive to a second enable signal and generating a test signal for testing the memory. The output signal is observed for debugging faults between the integrated scannable interface and the memory and for debugging faults between the first and second storage devices.

Abstract: Method and system for testing an integrated circuit and more particularly, for determining timing associated with an input or output of an embedded circuit, in an integrated circuit for testing are described. A bit is adjustably delayed with a first adjustable delay to provide a delayed bit. The delayed bit is provided to a bus, such as an input bus for example, of the embedded circuit as a second vector. A third vector is output from the embedded circuit responsive to the second vector. A fourth vector is obtained having second multiple bits. The fourth vector is compared with the third vector to determine a period of delay associated with at least approximately a maximum operating frequency of the embedded circuit.

Abstract: An apparatus for automatic testing of a PS/2 interface includes a micro controller unit, a PS/2 port, and a plurality of LEDs. The micro controller unit is coupled with both a data pin and a clock pin of the PS/2 interface. The LEDs coupled to the micro controller unit simulate functions of a keyboard. A related method for testing the PS/2 interface is also provided.

Abstract: In order to further develop a circuit arrangement (100), in particular an active shield, as well as a method for identifying at least one attack on the circuit arrangement (100), wherein test data are generated, the test data are transmitted via at least one group of data lines (50) being designed for carrying data signals in the form of regular data and/or in the form of the test data, the transmitted test data are received, the received test data are compared with expected test data, and any discrepancy between the received test data and the expected test data is ascertained or determined, in such way that less power is required for examining, in particular for identifying, if the circuit arrangement (100) has been attacked, it is proposed that part of the group of data lines (50) is selected to carry new or most recent test data having been generated.

Abstract: A method for testing functional boundary logic at an asynchronous clock boundary of an integrated circuit device is provided. With the method, each clock domain has its own scan paths that do not cross domain boundaries. By eliminating the scanning across the boundaries, the requirement to have two clock grids in the asynchronously clocked domains may be eliminated. As a result, circuit area and design time with regard to the clock distribution design are reduced. In addition, removing the second clock grid, i.e. the high speed core or system clock, in the asynchronously clocked domains removes the requirement to have a multiplexing scheme for selection of clocking signals in the asynchronous domain. In addition to the above, the system and method provide boundary built-in-self-test logic for testing the functional crossing logic of boundaries between the clock domains in a functional mode of operation.

Abstract: The present invention provides an apparatus and a computer program product for applying external clock and data patterns for TTP-LBIST. A simulation model for the logic under test is set up in a simulator. Next, a user sets up an external LBIST block, which comprises pre-verified internal clock and data pattern logic, and connects this block to the logic in the simulation model. The internal clock and data pattern logic provides the input patterns used in OPCG modes of LBIST. This internal clock and data pattern logic is already verified through the design effort. Therefore, the internal pattern generators become the external pattern generators in the simulation model. The external LBIST block applies the external clock and data patterns, and subsequently, the user receives and processes these output patterns to determine if the logic operates correctly.

Abstract: A method for testing a connection between an audio receiving device and a motherboard is disclosed. The method includes the steps of: preparing a data storage medium containing an original audio data file; playing the data storage medium on an audio playing device with audio signals generated thereof, the audio playing device being connected to the audio receiving device; receiving the audio signals by the audio receiving device; transmitting the audio signals to the motherboard via the connection between the audio receiving device and the motherboard; outputting the audio signals from an output port; receiving the audio signals by an input port; recording the audio signals as a recorded audio data file; comparing the two audio data file; and reporting a test result indicating that the connection is in good condition if the two audio data files are identical.

Abstract: Integrated circuits such as programmable logic device integrated circuits are provided that have memory arrays. The memory arrays can be tested using configurable built in self test circuitry. The built in self test circuitry may have test control register circuitry and configurable state machine logic. The state machine logic may perform at-speed tests on a memory array and may provide test results to external equipment for analysis. A tester may be used to provide test control settings to the test control register circuitry. The test control settings may include march element settings for a march sequence. During testing, the configurable state machine logic may use the march element settings to generate march sequences. March sequences that have been generated in this way may be used in testing the memory array.

Abstract: Systems and methods for performing logic built-in self-tests (LBISTs) to detect “at-speed” errors in a digital circuit. In one embodiment, an input bit pattern is propagated through target logic of the digital circuit and captured in scan chains at a normal operating speed to produce a first output bit pattern. This is repeated with the first input bit pattern at a lower test speed to produce a second output bit pattern. Differences between the first and second output bit patterns are then detected to determine whether operation of the digital circuit at the normal operating speed causes errors that are not generated at the lower test speed.

Abstract: A scan test method of an integrated circuit including a combinational circuit and flip-flops forming a scan chain is disclosed. The method first sets an initial test value to the flip-flops forming the scan chain by serial scan input. Then, it repeats a capture operation and a feedback shift operation. The capture operation captures an output of the combinational circuit, to which a value set to a flip-flop has been applied, by another flip-flop. The feedback shift operation feeds an output of the scan chain back to an input side of the scan chain for re-input during a shift operation in the scan chain. Finally, it compares an output of the scan chain with an expected value.

Abstract: A semiconductor integrated circuit (LSI) in which control information for determining a voltage or a width of a pulse produced itself can easily be set in parallel with other LSIs, and set information can be corrected easily. From an external evaluation device, a voltage of an expected value is supplied in overlapping manner to a plurality of LSIs each having a CPU and a flash memory. Each LSI incorporates a comparison circuit comparing an expected voltage value and a boosted voltage generated in itself. The CPU refers to a comparison result and optimizes control data in a data register for changing a boosted voltage. The CPU controls the comparison circuit and the data register and performs trimming in a self-completion manner, thereby making, trimming on a plurality of LSIs easily in a parallel manner and a total test time reduced.

Abstract: An embedded electronic system built-in self-test controller architecture that facilitates testing and debugging of electronic circuits and in-system configuration of programmable devices. The system BIST controller architecture includes an embedded system BIST controller, an embedded memory circuit, an embedded IEEE 1149.1 bus, and an external controller connector. The system BIST controller is coupled to the memory circuit and the IEEE 1149.1 bus, and coupleable to an external test controller via the external controller connector. The external test controller can communicate over the IEEE 1149.1 bus to program the memory and/or the system BIST controller circuitry, thereby enabling scan vectors to be debugged by the external test controller and then downloaded into the memory for subsequent application to a unit under test by the system BIST controller.

Abstract: In a test and debug environment using a JTAG protocol to test a target processing unit, apparatus for multi-value polling permits a poll unit, associated with the scan controller, to determine whether one of several possible signal groups is present in the received data stream. The test and debug unit generates a series of numbers, each number corresponding to a preselected signal groups. The corresponding field in the received data stream is decoded to provide a series of output signals, each output signal corresponding to one group. The output signals of the decoder are compared to corresponding numbers of the expected value. When a signal from the decoder unit is found to correspond to one of the selected data number, the poll operation is a success.

Abstract: A test card system for use in product development includes a device under test (DUT). The DUT comprises: a mount plane; a power input port coupled to the mount plane; a JTAG input port coupled to the mount plane; a clock signal distribution network coupled to the JTAG input port; a plurality of latches coupled to the clock signal distribution network and the power input port; and an output port coupled to the plurality of latches. A test card (TC) couples to the DUT, comprising: a JTAG interface coupled to the DUT JTAG input port and configured to provide test data to the DUT; a clock module coupled to the DUT clock signal distribution network and configured to generate a clock signal; and an analysis module coupled to the DUT output port and configured to receive data from the DUT.

Abstract: A semiconductor test system includes: pin electronics (“PE”) cards each being operable to: a) apply a test pattern to device under tests (“DUTs”) each connected to the PE cards; b) capture patterns outputted in response to the test pattern from the DUTs; c) compare the patterns with an expected value pattern; and d) determine whether or not the patterns correspond with the expected value pattern, and a fail control card being operable to: e) aggregate fail information about the DUTs inputted through the PE cards every the DUTs; and f) transfer the fail information to the PE cards.

Abstract: A method for testing semiconductor chips is disclosed. In one embodiment, a chip to be tested which has a test logic, at least one test mode is set, the test modes are executed in the chip and test results or the status of the test modes are output from the chip. The method includes providing a chip having at least one first register set having a plurality of registers and at least one second register set having a plurality of registers, at least one register of the first register set and at least one register of the second register set being 1:1 logically combined with one another. A first serial bit string is stored, the bit sequence of which can be assigned to at least one test mode, in the first register set. A bit sequence is transmitted for application of the logical combination between the first register set and the second register set to the first bit string stored in the first register set. The test results are read out by means of a serial second bit string.

Abstract: An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944) circuits. The scan paths apply stimulus test data to functional circuits (702) on the integrated circuit and receive response test data from the functional circuits. A scan distributor circuit (800) receives serial test data from a peripheral bond pad (802) and distributes it to each parallel scan path. A scan collector circuit (844) collects test data from the parallel scan paths and applies it to a peripheral bond pad (866). This enables more parallel scan paths of shorter length to connect to the functional circuits. The scan distributor and collector circuits can be respectively connected in series to provide parallel connections to more parallel scan paths. Additionally multiplexer circuits (886,890) can selectively connect pairs of scan distributor and collector circuits together.

Abstract: A method for testing semiconductor chips having a test logic unit includes: providing a chip having n different register sets, each of which has m different registers that are subdivided into m register groups each having n registers, each register group respectively having only one individual register from a register set, the m register groups being uniquely identifiable using m headers; programming the m different register groups by filling them with m first bit strings, each bit string being respectively assignable to a state of n test modes; transmitting at least one header to select a register group and the state of the n test modes and executing the state of n test modes stored in the selected register group; and using a serial second bit string to read out test results or the status of the test modes.

Abstract: A test object can be selectively included in a test run based on predicting the behavior of the test object. In one embodiment, the present invention includes predicting how likely the test object is to produce a failure in a test run and deciding whether to include the test object in the test run based on the predicted likelihood. This likelihood of producing a failure may be based on any number of circumstances. For example, these circumstances may include the history of prior failures and/or the length of time since the test object was last included in a test run.

Abstract: A testing system or method compares read data from one or more dies in a semiconductor wafer with the original data written onto the one or more dies. The testing system includes one or more write registers connected to one or more dies on the semiconductor wafer. One or more comparators are connected to the dies and the write registers. The comparator generates a result in response to the original data and the read data.

Abstract: There is provided a test apparatus for testing a memory-under-test for storing data strings to which an error correcting code has been added, having a logical comparator for comparing each data contained in the data string read out of the memory-under-test with an expected value generated in advance, a data error counting section for counting a number of data inconsistent with the expected value, a plurality of registers, provided corresponding to each of a plurality of classes, for storing an upper limit value of a number of errors contained in the data -under-test to be classified into the class, comparing sections for comparing each of the plurality of upper limit values stored in the plurality of registers with the counted value of the data error counting section and a classifying section for classifying the memory-under-test into the class corresponding to the register storing the upper limit value which is greater than the counted value.

Abstract: A semiconductor integrated circuit (LSI) in which control information for determining a voltage or a width of a pulse produced itself can easily be set in parallel with other LSIs, and set information can be corrected easily. From an external evaluation device, a voltage of an expected value is supplied in overlapping manner to a plurality of LSIs each having a CPU and a flash memory. Each LSI incorporates a comparison circuit comparing an expected voltage value and a boosted voltage generated in itself. The CPU refers to a comparison result and optimizes control data in a data register for changing a boosted voltage. The CPU controls the comparison circuit and the data register and performs trimming in a self-completion manner, thereby making, trimming on a plurality of LSIs easily in a parallel manner and a total test time reduced.

Abstract: Exemplary techniques for verifying a hardware design are described. In a described embodiment, a method comprises compiling an error verification object corresponding to an error verification command to verify a portion of a hardware design of a device under test. The error verification object is compiled in accordance with data provided by an error scripting module. The error scripting module has access to hardware-specific data corresponding to the hardware design of the device under test. The compiled object is sent to the device under test and a response to the compiled object is received from the device under test. The received response from the device under test is parsed in accordance with data provided by the error scripting module.

Abstract: A test circuit and programmable voltage divider that may be used in the test circuit. The programmable voltage divider develops a voltage difference signal that may be digitally selected. The test circuit may be used to test and characterize sense amplifiers. The programmable voltage divider develops a signal with a selected polarity and magnitude that is provided to a sense amplifier being tested. The sense amplifier is set and its output latched. The latch contents are checked against an expected value. The difference voltage may be changed and the path retested to find passing and failing points.

Abstract: A serial point to point link that communicatively couples an integrated circuit (IC) device to another IC device is initialized by transferring a training sequence of symbols over the link. Registers of the IC device are programmed, to set a symbol data pattern and configure a lane transmitter for the link. A start bit in a register of the IC device is programmed, to request that the link be placed in a measurement mode. In this mode, the IC device instructs the other IC device to enter a loopback mode for the link. The IC device transmits a sequence of test symbols over the link and evaluates a loopback version of the sequence for errors. The sequence of test symbols have a data pattern, and are transmitted, as configured by the registers. Other embodiments are also described and claimed.

Abstract: A verifier for remotely checking integrity of a device connected via a network, includes a calculator which fills free areas in a memory of the device with random numbers and generates a local check code; an interface which transmits integrity check parameters that are used by the device to generate a remote check code, to the device, and receiving the remote check code from the device; a determiner which detects a remote check code generation time and compares the detected remote check code generation time with a presorted remote check code generation expectation time; and a controller which confirms the integrity of the memory of the device when the remote check code generation time does not exceed the remote check code generation expectation time according to a result of the determination and the local check code matches the remote check code.

Abstract: A method of mitigating logic upsets includes providing an input to each of a plurality of programmable logic components, processing the input in each programmable logic component, determining an output from each programmable logic component, providing the output from each programmable logic component to a fixed logic component, examining the outputs, and determining a validated output from among the outputs. An architecture for mitigating logic upsets includes an input, a plurality of programmable logic components, and a fixed logic component. The input is provided to each of the programmable logic components. Each programmable logic components includes an encryption algorithm and a first majority voting logic, and processes the respective input to determine a respective output. The fixed logic component includes a second majority voting logic. The fixed logic component receives each respective output from the programmable logic components, examines the outputs, and determines a validated output.

Abstract: A read-only memory (ROM) and a related method for controlling operations of the ROM are disclosed. A built-in self-test (BIST) circuit of the ROM verifies system data stored in a system area of a plurality of memory cells of the ROM according to verification data stored in a verification area of the memory cells of the ROM.

Abstract: A semiconductor integrated circuit has a scan path that includes, between the output of the first logic section and the input of the functional block, a parallel path and a serial shift path for serially transferring data, and that includes first selectors for connecting the output of the first logic section or the serial shift path to the input of the functional block, and flip-flops for storing the data. The semiconductor integrated circuit further includes second selectors connected into the serial shift path of the scan path, for connecting the output of the functional block or the serial shift path to the input of the second logic section. Test data is provided from the serial shift path of the scan path to the functional block via the second selectors, and data output from the functional block is output via the second selectors after switching the second selectors.

Abstract: There is provided a testing apparatus including: a pattern generator that generates an address signal and a data signal to be supplied to a plurality of memories under test and an expectation signal; a plurality of logic comparators that generate fail data when an output signal output from the plurality of memories under test and the expectation signal are not identical with each other; a plurality of fail memories that store the fail data generated from the plurality of logic comparators; a plurality of memory controllers that generate bad address information showing a bad address in the memory under test based on the fail data stored on the plurality of fail memories; a plurality of universal buffer memories that store the bad address information generated from the plurality of memory controllers; and a plurality of bad information writing sections that concurrently write bad information into the bad address in the plurality of memories under test, which is shown by the bad address information stored on the

Abstract: A semiconductor test circuit includes an input terminal, a controller, a setting circuit, a command generator, a transmission path switching circuit and a comparator. The input terminal receives a serial data including a command code and a control data. The controller receives a control signal and outputs an internal control signal based on the control signal. The setting circuit receives the serial data and outputs it in response to the internal control signal. The command generator generates an interface signal based on the serial data received from the setting circuit. The switching circuit has ports, receives the signal from one of the ports and outputs the received signal to another one of the ports in response to the internal control signal and the command code. The comparator compares the interface signal received from the command generator with the signal received from the switching circuit.

Abstract: A modulated voltage signal modulated at a predetermined frequency f0 is supplied to an integrated circuit under test to be tested set at an arbitrary stationary point, and an observation signal containing information on power supply current flowing through the integrated circuit under test at the stationary point. Then, a determination signal from which DC component is removed is extracted from the observation signal and supplied to a determination device. The determination device compares the size of spectral component of the determination signal at the predetermined frequency f0 between each measurement point and determines that an error exists in the integrated circuit under test if a difference is a predetermined value or greater.

Abstract: The invention relates to a test method for determining a wire configuration for a circuit carrier having at least one component arranged thereon, where internal lines in the component are connected to component connections in a prescribed order, and where the component connections are wired to connections on the circuit carrier. According to the method, a respective prescribed test signal is applied to each internal line of the component using a controllable test signal generator integrated in the component. Output signals applied to the connections of the circuit carrier are tapped off. Thereafter, the respective output signals tapped off are identified with the corresponding test signals applied to the internal lines of the component using an external test apparatus for determining the wire configuration between the component connections and circuit carrier connections.

Abstract: Programmable memory built-in self-test (MBIST) methods, apparatus, and systems are disclosed. Exemplary embodiments of the disclosed technology can be used, for example, to test one or more memories located on an integrated circuit during manufacturing testing.

Abstract: The invention provides a method for testing circuit units to be tested in a test apparatus, different identification units being assigned to the circuit units to be tested, the circuit units to be tested being connected to the test apparatus, a tester data stream including command blocks being output from the test apparatus, the tester data stream being compared with the identification units, the circuit unit to be tested, the identification unit of which matches the tester data stream output by the test apparatus, being activated and at least one command block for this circuit unit to be tested being processed in the circuit unit to be tested, whereupon the circuit unit to be tested is deactivated.

Abstract: A method for testing the (Bit) Error Ratio BER of a device against a maximal allowable (Bit) Error Ratio BERlimit with a early pass and/or early fail criterion, whereby the early pass and/or early fail criterion is allowed to be wrong only by a small probability D. ns bits of the output of the device are measured, thereby ne erroneous bits of the ns bits are detected. PDhigh and/or PDlow are obtained, whereby PDhigh is the worst possible likelihood distribution and PDlow is the best possible likelihood distribution containing the measured ne erroneous bits with the probablility D. The average numbers of erroneous bits NEhigh and NElow for PDhigh and PDlow are obtained. NEhigh and NElow are compared with NElimit=BERlimit×ns. If NElimit is higher than NEhigh or NElimit is lower than NElow the test is stopped.

Abstract: In one embodiment, the invention is directed to a general purpose performance counter (“GPPC”) connected to a bus carrying debug data. The GPPC includes an AND/OR circuit connected to receive the debug data; a counter circuit connected to receive from the AND/OR circuit an increment signal that, when activated, causes the counter circuit to increment a count; and a compare circuit for activating a match/threshold signal to the AND/OR circuit responsive to a selected block of the debug data having a first relationship to a compare value, wherein the AND/OR circuit activates the increment signal responsive to a selected combination of bits of an events signal being set.

Abstract: A system and method in which a plurality of dice on a semiconductor wafer are interconnected to enable efficient testing thereof. In certain embodiments a plurality of dice are interconnected in a manner that enables test data to be communicated from a tester system to a plurality of dice for concurrent testing of such plurality of dice. Depending on the amount of interconnection, all or a portion of each of the plurality of dice may be tested concurrently. In certain embodiments, a plurality of dice are interconnected in a manner that enables test data to be communicated from one die to at least one other die. In certain embodiments, a plurality of dice are interconnected in a manner that enables such dice to be tested concurrently while maintaining a repeatable pattern at the reticle level for fabricating such dice.

Abstract: A test apparatus for testing a device under test 15 is provided. The test apparatus includes a driver 122 for applying a test signal to the device under test, a comparator 128 for comparing a result signal outputted by the device under test 15 corresponding to the applied test signal with a predetermined reference voltage and a setting voltage output section 110 for setting the voltage of the test signal to a predetermined voltage value to cause the driver 122 to terminate the transmission path of the result signal when the test apparatus reads from the device under test 15.