Abstract: An analog built-in self-test (BIST) methodology based on the IEEE 1149.4 mixed signal test bus standard. The on-chip generated triangular stimuli are transmitted to the analog circuit under test (CUT) through the analog test buses, and their test responses are quantized by the dual comparators. The quantized results are then fed into a pair of counters to record the sampled counts for comparison in the decision circuit. A pass/fail indication is then generated in the decision circuit to indicate success or failure of the CUT after the BIST operation is complete.

Abstract: The invention relates to a method and a circuit for digital-to-analog conversion, in which an interleaved pulse-width modulation signal (VPWM) is low-pass-filtered.

Abstract: An automatic testing system. A sampling and converting device obtains a plurality of electronic parameters from a tested device and transforms them into a plurality of digital signals. A microprocessor receives the digital signals and performs various short-circuit tests, over-current tests and over-voltage tests in a specific sequence.

Abstract: A pulse generation circuit including a pulse formation circuit for generating normal and dummy pulses according to second delay value data, a data calculation circuit for calculating first delay value data at a timing at which the pulses are generated from the pulse formation circuit according to pattern data having information for determining whether to generate pulses from the pulse formation circuit, a dummy pulse control circuit for controlling generation of a dummy pulse in a no-pulse-generation cycle from the pulse formation circuit according to the second delay value data obtained by detecting the no-pulse-generation cycle from the first delay value data, and a logical gate circuit for eliminating the dummy pulses generated from the pulse formation circuit.

Abstract: Systems and methods for digital-based, standards-compatible, testing of analog circuits embedded inside integrated circuits. In this regard, one such system can be broadly described by a test stimulus generator that transmits a binary-level test-stimulus signal into an analog circuit located inside an integrated circuit; a converter that converts an analog output signal from the analog circuit into a digital output signal; a boundary-scan register chain that transmits the digital output signal out of the integrated circuit, and a test equipment that receives the digital output signal using the IEEE 1149.1 boundary-scan standard and analyzes the digital output signal to compute one or more specifications of the analog circuit located inside the integrated circuit.

Abstract: A clock generating unit generates a clock signal having a predetermined frequency. A pattern generating unit outputs a data signal having a predetermined pattern in which one frame is configured from a predetermined bit length, so as to be synchronized with the clock signal. A waveform information acquiring unit receives the data signal as a data signal to be measured, and receives the clock signal, and acquires information of waveform in the same time domain of the data signal to be measured and the clock signal. An averaging processing unit carries out averaging processing on an acquired waveform. A phase difference detecting unit detects a phase difference of the data signal to be measured and the clock signal, for each bit, based on an averaged waveform information. A frequency band limiting processing unit carries out predetermined frequency band limiting processing on the per-bit phase difference information.

Abstract: A method and system for identifying an inaccurate model of a hardware circuit includes the steps of simulating a digital model and an analogue model of the circuit to provide first and second sets of simulation results respectively. For each result in the first and second sets of simulation an integer value is determined which represents that result. The integer values are stored in first and second sets of comparison results respectively and the sets of comparison results are compared. An output signal indicating that at least one of the models is inaccurate is produced if the comparison results contradict.

Abstract: A pin electronics circuit for automatic test equipment includes first and second sampling circuits for sampling first and second legs of a differential signal produced by a DUT (Device Under Test). Timing signals activate the first and second sampling circuits to sample the legs of the differential signal at precisely defined instants of time to produce first and second collections of samples. To deskew the legs of a differential signal with respect to each other, corresponding features within the first and second collections are identified and a difference is taken between them. The differential skew can then be applied to correct measurements of differential signals.

Abstract: An apparatus for testing an integrated circuit that includes analog nodes is disclosed. In one aspect, an integrated circuit comprises testing circuitry and core logic circuitry. A memory in the testing circuitry stores data identifying analog nodes in the core logic circuitry and tolerance values associated with the analog nodes. A condition checker compares actual test values with the associated tolerance values. A main control unit controls the testing circuitry and synchronizes testing of the core logic circuitry. In another aspect, the testing circuitry includes a host computer interface useful for communicating with a host computer. A data memory in the testing circuitry is used for storing diagnostic data. The contents of the data memory may then be uploaded to a host computer. Test stimuli may be transmitted to the integrated circuit from a location outside the integrated circuit to perform testing.

Abstract: Systems and methods for testing data lines to determine signal degradation in the data lines. A system includes a signal generator for generating a test pattern and for transferring the test pattern through the data lines. The system also includes an analyzer communicatively connected to the data lines to determine degradation of the test pattern in the data lines. The signal generator generates and transfers a first test pattern through the data lines. The first test pattern includes a first portion having a first polarity and a second portion having a second polarity. The signal generator then generates and transfers a second test pattern through the data lines in response to transferring the first test pattern. The test patterns may be repeated one or more times to determine cross talk caused by inductive coupling between data lines and additive reflections.

Abstract: An analog/digital characteristics testing device comprises: a plurality of measurement circuits for measuring an analog/digital characteristic of one or more ICs to be tested in accordance with a test condition data; and a setting unit for setting a different test condition data to each measurement circuit.

Abstract: There are disposed an output sequence control section, and output waveform data generation section for one system, and an analog waveform generation section includes four systems of ports 40, attenuators 43b for individually adjusting gains of analog test signals outputted via the respective ports, and digital/analog converters 45 for individually adjusting offset voltages of the analog test signals. Accordingly, when a plurality of LSIs to be tested are concurrently tested, the analog test signals optimized for each LSI to be tested are generated with a simple circuit configuration without complicating the circuit configuration of a performance board.

Abstract: A memory subsystem package has a memory controller interface ASIC (application specific integrated circuit) and a plurality of memory modules. The ASIC has a bi-directional serial protocol i2C communication bus to off chip drivers for monitoring temperature and for adjusting the environment surrounding the package by controlling fans using fan switches and variable voltage controls. In addition there is provided an Alternating Current Built in Self Test (AC BIST) with variable data receiver voltage reference for performing high-speed AC memory subsystem self-test for that ASIC enabling writing of pseudo-random patterns to memory, reading them back and comparing the expected results at hardware speeds. Vref can be made to vary across its allowable range during AC self test to provide improved coverage. The system monitors vddq during normal system operation using an ADC. The system varies Vref as a function of Vddq, using a combination of a DAC and ADC.

Abstract: An integrated circuit (IC) includes a first lead, a second lead and a sensor element that provides a sensed signal. The IC also includes a test signal generator that provides a test signal, a signal processing unit, and a switching device that selectively applies the sensed signal or the test signal to the signal processing unit in response to a command signal, wherein the signal processing unit provides processed data. In response to a test command input signal, the IC generates the command signal, wherein when the test input signal is active the command signal is set to command the switching device to input the test signal to the signal processing unit. A check sum calculator receives the processed data and provides a signal indicative of a check sum value on the second lead when the command signal is set to command the switching device to input the test signal to the signal processing unit.

Abstract: An on-board self test system for an electrical power monitoring device includes a test signal circuit in an electronic circuit of the monitoring device, and responsive to a programmable test input signal for producing an analog signal simulating an electrical power waveform, and a programmable memory in an electronic circuit of the monitoring device and operatively coupled with the test signal circuit for storing and reproducing upon command, one or more of the programmable test input signals.

Abstract: A test device for electrically testing an electronic device (DUT) 100 comprises a pattern memory 13A, a pattern generator 13, a first filter 20B, and a pin electronic assembly 19. The pattern memory 13A stores data defining test patterns to be supplied to the DUT 100. The pattern generator 13 generates a plurality of test patterns to be input to a plurality of input pins of the DUT using digital signals based on the data stored in the pattern memory 13A. The first filter converts at least one of the plurality of test patterns to analog signals. The pin electronic assembly 19 supplies the plurality of test patterns including the analog signal test pattern to the DUT 100.

Abstract: An anlog boundary scan compliant integrated circuit system carries out a test more reliably and cuts down on power dissipated during normal operation. To perform a test of whether or not an interconnect is connected normally between integrated circuits, multiple logic circuits with mutually different input threshold voltages are provided to detect the logical level of a potential at a terminal, thereby improving the reliability of the test. Potential fixers and power isolators are optionally provided. During normal operation, the power fixers fix the output potentials of the logic circuits, while the power isolators electrically isolate the logic circuits from the ground. As a result, no current flows through the logic circuits or other circuits in succeeding stages while no tests are carried out.

Abstract: A system and method for providing for on-chip configuration, control and testing of mixed signal circuitry within an integrated circuit. A dual signal interface conveys the serial data and clock signals used for controlling the enablement, disablement and operational modes of the synchronous circuitry responsible for such on-chip configuration, control and testing, thereby minimizing the amount of overhead, in terms of interface terminals needed, for providing such capability.

Abstract: A circuit comprising a phase detector/correction circuit, at least one column of memory cells, a control circuit and a sense amplifier. The control circuit may be configured to read a sequence from the memory cells in a predetermined order and present a first output signal. The sense amplifier may be configured to present a periodic signal in response to the first output signal.

Abstract: A method for testing sequential circuit designs in which an exhaustive sequence of test vectors is applied to the input nodes of edge-sensitive components of a simulated sequential circuit. The test vector values are selected from a group including a logic “1” (high), a logic “0” (low), a “floating” value (i.e., between logic “1” and logic “0”) and a randomly generated (“don't care”) value. While a predetermined combination of values is applied to all other input nodes of the simulated circuit, the sequence of test vector values is applied to a selected input node that produces all possible transitions between the test vector values. The predetermined combination of values applied to all other input nodes is then incrementally changed, and the test vector value sequence is repeated.

Abstract: A transient analysis device in which a simulation executing unit uses a first net list produced by a net list producing unit to measure a settling time of an analog/digital mixed circuit to be analyzed, after a dummy pulse parameter setting unit sets a parameter of a dummy pulse based on the measurement result, the net list producing unit converts, into a net list, a transfer function of a new circuit obtained as a result of the addition of a dummy pulse generation circuit for generating a dummy pulse whose parameter has been set to the analog/digital mixed circuit, and the simulation executing unit executes transient analysis processing by using a second net list produced with respect to the new circuit.

Abstract: A method that uses effective widths of NMOS and PMOS devices in a digital circuit and their intrinsic junction and subthreshold leakage currents to produce a specification for IDDQ, the range of IDDQ, and the delta of IDDQ between pre- and post-overvoltage stress tests to screen out defective integrated circuits having excessive extrinsic current leakage. The present invention provides for a computer-implemented method that generates an indication of whether IDDQ values associated with integrated circuits that have been tested are within the IDDQ specification or not. This processing eliminates the need for time-intensive and costly burn-in testing on the integrated circuits.

Abstract: A tester circuit generating differential signals, single ended signals, or a fast transitioning signal to exercise inputs of a device under test is described. According to one embodiment, the tester circuit includes a first circuit configured to generate a first test signal on an input of the first driver. The tester circuit also includes a second circuit configured to generate a second test signal on an input of a second driver. Further, the tester circuit also includes select signals and select logic to determine the different testing modes of the device under test.

Abstract: A testing assembly, and an associated method, for testing an integrated circuit device. The testing assembly is capable of testing an integrated circuit device having a large number of input and output terminals formed of either single-ended terminals or differential terminals. Static testing, both functional and parametric, can be performed upon the integrated circuit device. Additionally, dynamic testing of the integrated circuit device, even integrated circuit devices operable at high frequencies, is possible through operation of the testing assembly. Test signals are applied by way of signal rails to the device undergoing testing. A test signal response indicator is coupled to observe responses to the test signals.