Including Test Pattern Generator Patents (Class 714/738)
  • Patent number: 11125818
    Abstract: A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE 1500 core test wrappers and provides high test data bandwidth to the wrappers from an external tester. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. The test architecture includes a selector circuit for selecting a core for testing. Additional features and embodiments of the device test architectures are also disclosed.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: September 21, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Lee D. Whetsel
  • Patent number: 11101015
    Abstract: A target vector representing a usage parameter corresponding to a test of a memory component is generated. A test sample is assigned to the target vector and a set of path variables are generated for the test sample. A test process of the test is executed using the test sample in accordance with the set of path variables to generate a test result. A failure associated with the test result is identified.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: August 24, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Aswin Thiruvengadam, Sivagnanam Parthasarathy, Preston Thomson
  • Patent number: 11073557
    Abstract: A circuit device is provided with a first codec including a first portion of a logic circuit and a second codec including a second portion of the logic circuit. The circuit device can also include a plurality of first scan chains coupled to the first codec and configured to shift a delayed test vector onto the first codec, wherein the delayed test vector is a test vector with a phase delay. A plurality of second scan chains can be coupled to the second codec and configured to shift the test vector onto the second codec.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: July 27, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Prakash Narayanan, Wilson Pradeep
  • Patent number: 11030832
    Abstract: An apparatus for generating a test case for a vehicle includes a communication device that receives vehicle data from an electronic device. The apparatus also includes a controller that converts the vehicle data to a state diagram, patterns the state diagram, and generates the test case based on the patterned state diagram.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: June 8, 2021
    Assignees: Hyundai Motor Company, Kia Motors Corporation
    Inventors: Hyo Sup Kang, Choel Min Park
  • Patent number: 11010285
    Abstract: Systems, methods, and computer-readable media are described for performing fault detection and localization using Combinatorial Test Design (CTD) techniques and generating a regression bucket of test cases that expose a detected fault in a System Under Test (SUT). The SUT may be a hardware system or a software system. Further, the fault detection and localization may be performed while adhering to architectural restrictions on the SUT.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: May 18, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Andrew Hicks, Dale E. Blue, Ryan Rawlins, Rachel Brill
  • Patent number: 11010294
    Abstract: A method of writing data utilizes a pipeline to process write operations of a first plurality of data words addressed to a memory bank. The method also comprises writing a second plurality of data words into an error buffer, wherein the second plurality of data words comprises data words that are awaiting write verification. Additionally, the method comprises searching for at least one data word that is awaiting write verification in the error buffer, wherein verify operations associated with the at least one data word occur in a same row as the write operation. Finally, the method comprises determining if an address associated with any of the at least one data word is proximal to an address for the write operation and preventing a verify operation associated with the at least one data word from occurring in a same cycle as the write operation.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: May 18, 2021
    Assignee: Spin Memory, Inc.
    Inventors: Benjamin Louie, Neal Berger, Lester Crudele
  • Patent number: 10942220
    Abstract: Disclosed herein are voltage driver circuits and methods of operating the same to provide a variable output voltage that is suitable for use in ATE to provide a large number of test signals with accurate voltage levels at high data rates using components that consume relatively low power. According to an aspect, a change in output current in a voltage driver related to changing output voltage may be offset by a stabilization current generated by a correction driver for the voltage driver, such that supply currents drawn from the supply voltages can remain substantially stable. The correction driver may be connected to one or more supply voltages, and programmed to output a stabilization current that offsets changes in supply currents arising from changing of the programmed output of the voltage driver circuit. Such a driver may enable a test system to more precisely test semiconductor devices.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: March 9, 2021
    Assignee: Teradyne, Inc.
    Inventors: Jan Paul Anthonie van der Wagt, Greg Warwar
  • Patent number: 10942660
    Abstract: A memory system includes a memory device including dies, each of the dies including planes, each of the planes including blocks, each of the blocks including pages; and a controller suitable for controlling the memory device, the controller comprising: a memory including a mapping table which includes map chunks generated through dividing map data into map chunks each of a unit size; a pattern determination engine suitable for determining patterns with respect to each of the map chunks received from the memory; and a compression engine suitable for determining whether to perform compression on the map chunks, based on pattern determination results for the map chunks determined by the pattern determination engine, and performing compression on those map chunks for which performing compression was determined.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: March 9, 2021
    Assignee: SK hynix Inc.
    Inventors: Yong Jin, Seung-Geol Baek
  • Patent number: 10877093
    Abstract: A scan chain may be formed throughout an integrated circuit in which the scan chain is coupled to a set of pins via bi-directional input/output (I/O) buffers. A test pattern may be received from an external tester using the set of I/O pins and buffers operating in parallel. The test pattern is scanned into the scan chain using a shift clock operating at a first rate. The test pattern is then provided to combinatorial logic circuitry coupled to the scan chain. A response pattern is captured in the scan chain and then scanned from the scan chain using a shift clock operating at a second rate that is slower than the first rate. The response pattern is provided to the external tester using the same set of I/O pins and buffers operating in parallel.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: December 29, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mudasir Shafat Kawoosa, Rajesh Kumar Mittal
  • Patent number: 10803003
    Abstract: A data recording system includes a host terminal and a data recorder. The host terminal defines a first module card to be corresponding to a first data channel and a first module card slot of the data recorder. The first module card is inserted into the first module card slot, and the data recorder stores a first type of data captured from the first data channel to the first module card. The host terminal has the data recorder stop capturing the first type of data, and defines a second module card to be corresponding to a second data channel and the first module card slot of the data recorder. The data recorder is shut down, and the first module card is dismounted from the first module card slot. The second module card is inserted into the first module card slot, and the data recorder is rebooted.
    Type: Grant
    Filed: December 8, 2019
    Date of Patent: October 13, 2020
    Assignees: Inventec (Pudong) Technology Corp., Inventec Corporation
    Inventors: Yu-Lin Chang, Kai-Yang Tung
  • Patent number: 10768230
    Abstract: Embodiments are directed to a computer implemented method and system for the testing, characterization and diagnostics of integrated circuits. A system might include a device under test, such as an integrated circuit, that includes an adaptive microcontroller. The method includes loading a testing program for execution by the adaptive microcontroller, causing the microcontroller to execute the testing program. Once results from the testing program are received, the testing program can be adaptively modified based on the results. The modified testing program can be run again. The testing program can modify parameters of the integrated circuit that are not externally accessible. Other embodiments are also disclosed.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: September 8, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert M. Casatuta, Mary P. Kusko, Gary W. Maier, Franco Motika, Phong T. Tran
  • Patent number: 10761131
    Abstract: Methods and computer-readable media for testing integrated circuit designs implement a physically efficient scan by optimally balancing and connecting scan segments in a 2-dimensional compression chain architecture. A compression architecture that provides an optimal and balanced configuration of scan segments in 2D compression grids to not only decrease test time, but also to maximize compression efficiency and limit wiring congestion for IC designs that contain complex scan segments facilitates efficient scanning of data by bisecting the elements into balanced partitions of the same target scan length. A segment padding algorithm, followed by a bisecting algorithm and ultimately an element swapping algorithm may be applied to optimally balance and connect scan segments in 2-D compression chains, optimizing an efficient compression architecture which minimizes scan testing resources and time.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: September 1, 2020
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Christos Papameletis, Brian Edward Foutz, Vivek Chickermane, Krishna Vijaya Chakravadhanula
  • Patent number: 10705254
    Abstract: A system and method is provided for restoring a 3D tomographic model of the Earth's subsurface geology from the present-day to a past restoration time. Whereas at the present time all faults represent active discontinuities, at a past restoration time some faults have not yet formed. Accordingly, the restored model divides the fault network into ?-active faults (discontinuous surfaces for faults that intersect the layer deposited at the past restoration time) and ?-inactive faults (continuous surfaces for faults that do not intersect the layer deposited at the past restoration time). A new 3D restoration transformation is also provided that uses linear geological constraints to process the restoration model in less time and generate more accurate geological images.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: July 7, 2020
    Assignees: Emerson Paradigm Holding LLC
    Inventors: Jean-Laurent Mallet, Anne-Laure Tertois
  • Patent number: 10672494
    Abstract: A memory device, includes: a memory array comprising a plurality of bit cells arranged along a plurality of rows and along a plurality of columns, respectively; and a control logic circuit coupled to the memory array, and configured to determine respective locations of a first plurality of diagonal bit cells of the memory array for testing one or more peripheral circuits coupled to the memory array, wherein the control logic circuit is further configured to determine respective locations of at least a second plurality of diagonal bit cells of the memory array for testing the one or more peripheral circuits, wherein a number of the plurality of rows is different than a number of the plurality of columns and the first plurality of diagonal bit cells span a first equal number of rows and columns and the second plurality of diagonal bit cells also span a second equal number of rows and columns.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: June 2, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Lien Linus Lu, Johnathan Tsung-Yung Chang
  • Patent number: 10620266
    Abstract: In one embodiment, a processor includes at least one core and an interface circuit to interface the at least one core to additional circuitry of the processor. In response to an in-field self test instruction, at least one core may save state to a low power memory, enter into a diagnostic sleep state and execute an in-field self test in the diagnostic sleep state in which the at least one core appears to be inactive. Other embodiments are described and claimed.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: April 14, 2020
    Assignee: Intel Corporation
    Inventors: Vedvyas Shanbhogue, Jeff Huxel, Wei Li, Sanjoy Mondal, Arvind Raman
  • Patent number: 10586014
    Abstract: A method for combining verification data may include using a processor, obtaining verification data and a verification model from each of a plurality of verification engines relating to different verification methods, the verification data relating to a plurality of verification tests that were conducted on a design under test (DUT) using the plurality of verification engines; using a processor, merging the verification models obtained from the plurality of verification engines into a merged verification model; using a processor, calculating a combined verification metric grade for a plurality of verification entities in the merged verification model using verification metric grades for each of the plurality of verification entities calculated from the verification data obtained from the plurality of engines and applying a combined verification metric grade rule; and outputting the combined verification metric grade via an output device.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: March 10, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Yael Kinderman, David Spatafore, Nili Segal, Yan Yagudayev, Vincent Reynolds
  • Patent number: 10551420
    Abstract: According to some embodiments, a tester tests one or more DUTs by utilizing one or more respective reference devices. The tester comprises one or more test sites and one or more test circuits operatively coupled to each of the test sites. Each test site is configured to: hold a reference device and a DUT, transmit a transmitted electromagnetic RF signal including a test data pattern to the DUT, and receive a received electromagnetic RF signal emitted from the DUT. The test circuits are configured to: receive a first electrical signal converted from the received electromagnetic RF signal, extract first data from the first electrical signal, determine a first error rate between the test data pattern and the first data, and generate a test result on the basis of the first error rate.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: February 4, 2020
    Assignee: Keyssa Systems, Inc.
    Inventors: Srikanth Gondi, Arunprasad Ramiya Mothilal
  • Patent number: 10520542
    Abstract: The system includes a positioning system for mounting the circuit board to be tested and for mounting a sensor assembly. A control system registers the position of the sensor assembly relative to the circuit board to be tested and for moving the sensor assembly about the circuit board. The sensor assembly detects noise or other emissions generated by the circuit elements on the board. The noise emissions are separate from the operating signals of the circuit. The spectrum analyzer receives the emissions from the sensor assembly and produces frequency spectrum data over a selected frequency range with amplitude information. A processing system then compares the frequency spectrum information with frequency spectrum information from boards known to be good and provides information as to any differences and whether they are in an acceptable tolerance range.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: December 31, 2019
    Assignee: Huntron, Inc.
    Inventor: Alan Howard
  • Patent number: 10503578
    Abstract: An on-chip TDDB degradation monitoring and failure early warning circuit for SoC. A control circuit module converts Q1 and Q0 signals into a switch state control signal and outputs the switch state control signal to a digital conversion module for TDDB performance degradation. A MOS transistor of a first MOS transistor circuit within the digital conversion module for TDDB performance degradation is in a stress state of a supply voltage, and a MOS transistor of a second MOS transistor circuit is in a non-stress state. The first and second MOS transistor circuits output a first frequency value and a second frequency value to the output selection module. The output selection module outputs the first frequency value from the digital conversion module to the counter B for recording, or outputs the second frequency value to the counter A for recording. The counter module determines the degradation level of TDDB performance.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: December 10, 2019
    Assignee: Fifth Electronics Research Institute of Ministry of Industry and Information Technology
    Inventors: Yiqiang Chen, Dengyun Lei, Yunfei En, Wenxiao Fang, Lichao Hao, Yun Huang, Bo Hou, Yudong Lu
  • Patent number: 10430101
    Abstract: A semiconductor memory device includes a NAND memory including a plurality of blocks, each of which is a unit of data erasing, and a controller. The controller is configured to select an initial value from a group of initial values, based on an address of the NAND memory in which data are to be written, set a value corresponding to the selected initial value to a linear feedback shift register circuit, randomize the data using an output value of the linear feedback shift register circuit, and write the randomized data to the address of the NAND memory. A size of each of the blocks S is smaller than 2n-1 bytes, n being a number of registers included in the linear feedback shift register circuit.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: October 1, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Tsuyoshi Atsumi, Yasuhiko Kurosawa
  • Patent number: 10417045
    Abstract: An apparatus and a method is provided that comprises at least one first processing unit configured to run at least one first computer program application capable of receiving and processing signals received from at least one interface or device connected to said first processing unit, at least one second processing unit configured to run at least a second computer program application capable of further processing at least some information processed in said first processing unit.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: September 17, 2019
    Assignee: Amer Sports Digital Services Oy
    Inventors: Erik Lindman, Jyrki Uusitalo, Timo Eriksson, Tomi Lehto, Tero Aurto
  • Patent number: 10404609
    Abstract: A method for testing a data packet signal transceiver device under test (DUT). Following initial signal communications with a DUT, timing of further transmissions by the DUT may be effectively controlled by transmitting congestive communication channel signals to cause the DUT to detect apparent communication channel activity and in response thereto delay its own signal transmissions.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: September 3, 2019
    Assignee: LitePoint Corporation
    Inventors: Chen Cao, Christian Volf Olgaard, Ruizu Wang
  • Patent number: 10372853
    Abstract: A method and circuit for implementing enhanced diagnostics with intelligent pattern combination in automatic test pattern generation (ATPG), and a design structure on which the subject circuit resides are provided. A random fault is selected in the design. A test pattern is generated and applied the test pattern to a design under test to test the selected random fault. The test is re-simulated to determine faults that are covered by the applied test pattern. A next iteration of test pattern generation includes selecting a fault that is based upon the previous test pattern generation for generating new test patterns.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: August 6, 2019
    Assignee: International Business Machines Corporation
    Inventors: Steven M. Douskey, Michael J. Hamilton, Amanda R. Kaufer, Phillip A. Senum
  • Patent number: 10366648
    Abstract: A semiconductor integrated circuit connected to another circuit via differential transmission lines of N channels (where N is a natural number), the circuit includes: N pairs of differential output pins each of which is connected to a differential transmission line of a corresponding channel; N differential transmitters each of which is configured to drive a differential transmission line of a corresponding channel; and an abnormality detection circuit configured to detect abnormality in the differential transmission lines. The abnormality detection circuit includes: N amplifiers configured to detect a potential difference between differential transmission lines of corresponding channels; N first comparators each of which is configured to compare an output voltage of a corresponding amplifier with a first threshold voltage; and a logic circuit configured to detect abnormality of a first mode in a differential transmission line of a corresponding channel based on an output from each of the N first comparators.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: July 30, 2019
    Assignee: ROHM CO., LTD.
    Inventor: Takashi Shimizu
  • Patent number: 10352996
    Abstract: A backplane testing system includes a test backplane coupled to a test device chassis and including a first connector system, a second connector system, and channels that connect the first connector system and the second connector system. A first test device in a first test device slot on the test device chassis engages the first connector system and provides a loop back circuit for the first connector system. A second test device in a second test device slot on the test device chassis engages the second connector system. The second test device sends a test signal through a channel on the test backplane such that the test signal is provided to the loop back circuit on the first test device and received back through the channel. The second test device analyzes the test signal that is received to determine a testing compliance of the channel on the test backplane.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: July 16, 2019
    Assignee: Dell Products L.P.
    Inventors: Umesh Chandra, Timothy Thinh Mai
  • Patent number: 10317569
    Abstract: A new gridding method is disclosed for forward stratigraphic modeling that allows for syndepositional and/or postdepositional fault movement. The new gridding algorithm may represent both the lateral move of structure block, and provide efficiency that is comparable to the structured grid for forward stratigraphy model accessing previous deposited sediments stored in the grid. Embodiments of the disclosed methods allow for structural moves by performing a set of simple operations on the grid. The operations are generally simple, and do not change the overall topology of the grid. Therefore the operation can be easily repeated and the overall topological structure of the grid remains largely unchanged for simple access by the forward stratigraphic model. Further details and advantages of various embodiments of the method are described in more herein.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: June 11, 2019
    Assignee: Chevron U.S.A. Inc.
    Inventors: Tao Sun, Martin Perlmutter, Michael James Pyrcz, Morgan Sullivan, Ashley Harris
  • Patent number: 10303579
    Abstract: A method for automatic debug session analysis for related work item discovery, is provided. The method includes recording metadata describing a particular debug session associated with a user for a respective work item. The method further includes associating the metadata recorded in the particular debug session with the respective work item. In response to the user working on a new issue, comparing the metadata saved with other work items. In response to identifying a work item with a predetermined level of similar metadata from debug sessions, notifying the user of a potential work item match. In response to not identifying a work item with a predetermined level of similar metadata from debug sessions, refraining from suggesting the new issue for future matches.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: May 28, 2019
    Assignee: International Business Machines Corporation
    Inventors: Daniel P. Craggs, Jeremiah S. Swan
  • Patent number: 10254129
    Abstract: A magnetic speed sensor may comprise a digital component configured to estimate a zero crossing event based on a plurality of sensor signal samples. The digital component may output, to a control unit, a speed signal that is based on the estimated zero crossing event.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: April 9, 2019
    Assignee: Infineon Technologies AG
    Inventors: Dirk Hammerschmidt, Muhammad Adnan
  • Patent number: 10184976
    Abstract: The present disclosure illustrates a testing circuit board with self-detection function and a self-detection method. A test for a to-be-tested circuit board is executed and a self-detection for a testing circuit board is performed by a JTAG chip. After the self-detection is passed, a first JTAG connection interface and a second JTAG connection interface are conducted by a controller, a multiplexer and a switch chip, to connect test circuit boards in series. Therefore, the efficiency of solving self-detection of JTAG chip with series connection conveniently and quickly may be achieved.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: January 22, 2019
    Assignee: INVENTEC (PUDONG) TECHNOLOGY CORPORATION
    Inventor: Ping Song
  • Patent number: 10169510
    Abstract: Techniques relate to dynamic complex fault model generation for diagnostics simulation and pattern generation. Inline fabrication parametric data is received, and the inline fabrication parametric data is a collection of physical measurements made on a device under test during a manufacturing fabrication of the device under test. A fault model of defects is generated according to the inline fabrication parametric data, where the fault model is based on a physical design of the device under test combined with the inline fabrication parametric data for the device under test. Test patterns are generated based on the fault model and the inline fabrication parametric data, such that the test patterns are configured to test the device under test in order to obtain results that are based on the inline fabrication parametric data. A simulation is run of the device under test using the results and the inline fabrication parametric data.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mary P. Kusko, Gary W. Maier, Franco Motika, Phong T. Tran
  • Patent number: 10114070
    Abstract: A substrate inspection apparatus can efficiently inspect electric characteristics of the semiconductor device. A prober 10 includes a probe card 15 having a multiple number of probe needles 17 to be brought into contact with electrodes of a semiconductor device formed on a wafer W; and a test box 14 electrically connected to the probe card 15. A card-side inspection circuit of the probe card 15 reproduces a circuit configuration on which the semiconductor device is to be mounted after separated from the wafer W, e.g., the circuit configuration of a function extension card, and a box-side inspection circuit 21 of the test box 14 reproduces a circuit configuration on which the semiconductor device is to be mounted, e.g., a part of the circuit configuration of the mother board.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: October 30, 2018
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Michio Murata, Shingo Morita, Kenichi Narikawa
  • Patent number: 10088526
    Abstract: A tester for integrated circuits on a silicon wafer includes an input/output connection for testing an integrated circuit. The tester comprises circuitry arranged for transferring a first data frame to the integrated circuit via the input/output connection, the first data frame including a time reference for the data included in the data frame, a field for validating the time reference and a data field including at least one test command and for receiving a second data frame via the input/output connection, the data in the second data frame received having a duration that is a multiple of the time reference.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: October 2, 2018
    Assignee: STARCHIP
    Inventors: Cyrille Lambert, S├ębastien Bayon, Alexandre Croguennec
  • Patent number: 10068786
    Abstract: At least some embodiments are directed to a system that comprises storage comprising a data structure that cross-references an identifier of a semiconductor wafer, a location of a die in the wafer, an identifier of a lead frame strip, a location of a lead frame in the lead frame strip, and results of a first test on the die. The system also comprises mechanical equipment configured to test packaged die. The system further comprises a processor, coupled to the storage and to the mechanical equipment, configured to perform a second test on a package containing the die and the lead frame using the mechanical equipment and the results of the first test.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: September 4, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Joseph Anthony Boduch, Sandia You Ni Chiu, Robert Daniel Orr, Michael Francis Pas
  • Patent number: 9977078
    Abstract: Circuits and methods for loopback testing are provided. A die incorporates a receiver (RX) to each transmitter (TX) as well as a TX to each RX. This architecture is applied to each bit so, e.g., a die that transmits or receives 32 data bits during operation would have 32 transceivers (one for each bit). Focusing on one of the transceivers, a loopback architecture includes a TX data path and an RX data path that are coupled to each other through an external contact, such as a via at the transceiver. The die further includes a transmit clock tree feeding the TX data path and a receive clock tree feeding the RX data path. The transmit clock tree feeds the receive clock tree through a conductive clock node that is exposed on a surface of the die. Some systems further include a variable delay in the clock path.
    Type: Grant
    Filed: July 23, 2014
    Date of Patent: May 22, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Alvin Leng Sun Loke, Thomas Clark Bryan, Reza Jalilizeinali, Tin Tin Wee, Stephen Robert Knol, LuVerne Ray Peterson
  • Patent number: 9967084
    Abstract: A controller for modifying a clock signal from a first clock, the controller comprising: a time comparison unit configured to estimate a time difference between a first signal associated with the first clock and a reference signal received at the controller, wherein the time comparison unit is configured to determine if the time difference is greater than or less than one clock period of the first clock; a first signal modifier configured to modify the clock signal by an integer number of clock periods; and a second signal modifier configured to modify the clock signal by a fraction of the clock period, wherein the controller is configured to select, for modifying the clock signal, the first signal modifier if the time difference is greater than one clock period or the second signal modifier if the time difference is less than one clock period.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: May 8, 2018
    Assignee: Imagination Technologies Limited
    Inventors: Ravichandra Giriyappa, Vinayak Prasad, Oana Rosu
  • Patent number: 9915702
    Abstract: Various aspects of the disclosed techniques relate to channel sharing techniques for testing circuits having non-identical cores. Compressed test patterns for a plurality of circuit blocks are generated for channel sharing. Each of the plurality of circuit blocks comprises a decompressor configured to decompress the compressed test patterns. Test data input channels are thus shared by the decompressors. Control data input channels are usually not shared by non-identical circuit blocks in the plurality of circuit blocks.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: March 13, 2018
    Assignee: Mentor Graphics Corporation
    Inventors: Yu Huang, Mark A. Kassab, Janusz Rajski, Wu-Tung Cheng, Jay Babak Jahangiri
  • Patent number: 9869718
    Abstract: A circuit and a method for testing for faults in a circuit path. The circuit comprises a memory, a collar flop connected in parallel with the memory, and a feedback path in communication with the output of the memory and the input of the collar flop. The method comprises applying a fault test vector to logic in the circuit path to produce a fault test vector response, propagating the vector or the response through a memory in the circuit path, and capturing the response in a collar flop.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: January 16, 2018
    Assignee: MICROSEMI SOLUTIONS (U.S.), INC.
    Inventors: Hanumantharaya H, Yasushi Takenaka
  • Patent number: 9860083
    Abstract: The present invention discloses a channel estimation method, apparatus, and device and a multichannel microwave communications system. According to the channel estimation method, a first vector group corresponding to a transmit end and a second vector group corresponding to a receive end are first obtained according to a transmit-receive array size; then a subchannel estimation procedure is performed multiple times according to the transmit-receive array size, the first vector group, and the second vector group, to obtain multiple corresponding subchannel estimated coefficients; and finally, a real channel matrix is determined according to the first vector group, the second vector group, and an estimation matrix consisting of the multiple subchannel estimated coefficients.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: January 2, 2018
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventor: Rui Lv
  • Patent number: 9852037
    Abstract: An approach for improving efficiency of cycle-reproducible debug in a multi-core environment is provided. The approach executes an exerciser image on one or more cores, wherein the exerciser image includes one or more different seeds. The approach determines a seed from the one or more different seeds that locates a fail-condition. Responsive to determining a seed from the one or more different seeds that locates the fail condition, the approach determines an upper bound and a lower bound of the fail-condition. The approach determines an exact cycle where the fail-condition occurs. The approach constructs a multi-cycle trace for the fail-condition.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: December 26, 2017
    Assignee: International Business Machines Corporation
    Inventors: James N. Klazynski, Amir Nahir
  • Patent number: 9842633
    Abstract: Various embodiments include apparatus and methods to track and/or correct timing signals. Timing signals generated from an interface can be compared to the timing signals returned to the interface. A timing delta from the comparison can be applied to calculate a correction value make adjustments that can include adjustment to a subsequent timing signal, adjustment to a reference voltage setting associated with the subsequent timing signal, other adjustments, or combinations thereof. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: December 12, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Gregory A. King
  • Patent number: 9689922
    Abstract: A computer implemented process is described for testing multiple electronic devices under test (DUTs). A design test pattern or command/instruction is generated with an electronic design automation tool (EDA). The generated design test pattern and command/instruction is sent directly to an automated test equipment apparatus (ATE) over a UNIX or scripting language based, and/or a network based, communication pipeline. The ATE converts the sent design test pattern to an instance of the test pattern directly executable by the ATE. The ATE apparatus inputs test signals to each of the multiple electronic DUTs based on the executable test pattern. The ATE apparatus then receives, from each of the multiple electronic DUTs, a test result based on the input test signals. The ATE returns the received test result, and a report of an action responsive to the command/instruction to the EDA tool, which may then process the test results and report.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: June 27, 2017
    Assignee: ADVANTEST CORPORATION
    Inventors: Jinlei Liu, Zu-liang Zhang, Shu Li
  • Patent number: 9678151
    Abstract: An approach for improving efficiency of cycle-reproducible debug in a multi-core environment is provided. The approach executes an exerciser image on one or more cores, wherein the exerciser image includes one or more different seeds. The approach determines a seed from the one or more different seeds that locates a fail-condition. Responsive to determining a seed from the one or more different seeds that locates the fail condition, the approach determines an upper bound and a lower bound of the fail-condition. The approach determines an exact cycle where the fail-condition occurs. The approach constructs a multi-cycle trace for the fail-condition.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: June 13, 2017
    Assignee: International Business Machines Corporation
    Inventors: James N. Klazynski, Amir Nahir
  • Patent number: 9653426
    Abstract: A method of manufacturing an array of semiconductor device packages includes placing a plurality of semiconductor chips on a temporary carrier, covering the plurality of semiconductor chips with an encapsulation material to form an encapsulation body, providing a plurality of microwave components each including at least one electrically conducting wall structure integrated in the encapsulation body, forming a plurality of electrical interconnects each configured to electrically couple a semiconductor chip and a microwave component, and separating the encapsulation body into single semiconductor device packages each including a semiconductor chip, a microwave component and an electrical interconnect.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: May 16, 2017
    Assignee: Infineon Technologies AG
    Inventors: Ernst Seler, Maciej Wojnowski, Walter Hartner, Josef Boeck
  • Patent number: 9654986
    Abstract: A system and method for testing wireless transceivers in a virtual wireless environment including emulating an RF environment, creating virtual spectrum users having selectable transmission parameters and physical characteristics and evaluating the operation of the wireless transceiver in the virtual wireless environment.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: May 16, 2017
    Assignee: Echo Ridge LLC
    Inventors: Joseph P. Kennedy, John P. Carlson
  • Patent number: 9599671
    Abstract: Exemplary method, computer-accessible medium, test architecture, and system can be provided for a partial-scan test of at least one integrated circuit. For example, it is possible to obtain a plurality of test cubes using a first combinational automatic test pattern generation (ATPG) and identify at least one flip-flop of the integrated circuit using the test cubes to convert to a non-scan flip-flop and facilitate the partial-scan test to utilize the cubes without a utilization of a sequential ATPG or a second combinational ATPG.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: March 21, 2017
    Assignee: New York University
    Inventor: Ozgur Sinanoglu
  • Patent number: 9568542
    Abstract: In an embodiment, a memory interface includes integrated circuitry to verify the integrity of the memory interface. The circuitry propagates a test pattern through different paths of the memory interface, and checks the result against a reference value to determine whether the components of the paths are operating within an acceptable tolerance. The memory interface can also communicate with ATE to initiate such tests and return the results to the ATE.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: February 14, 2017
    Assignee: Cavium, Inc.
    Inventor: David Lin
  • Patent number: 9552449
    Abstract: Techniques relate to dynamic complex fault model generation for diagnostics simulation and pattern generation. Inline fabrication parametric data is received, and the inline fabrication parametric data is a collection of physical measurements made on a device under test during a manufacturing fabrication of the device under test. A fault model of defects is generated according to the inline fabrication parametric data, where the fault model is based on a physical design of the device under test combined with the inline fabrication parametric data for the device under test. Test patterns are generated based on the fault model and the inline fabrication parametric data, such that the test patterns are configured to test the device under test in order to obtain results that are based on the inline fabrication parametric data. A simulation is run of the device under test using the results and the inline fabrication parametric data.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: January 24, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mary P. Kusko, Gary W. Maier, Franco Motika, Phong T. Tran
  • Patent number: 9551746
    Abstract: A backplane testing system includes a test backplane coupled to a test device chassis and including a first connector system, a second connector system, and channels that connect the first connector system and the second connector system. A first test device in a first test device slot on the test device chassis engages the first connector system and provides a loop back circuit for the first connector system. A second test device in a second test device slot on the test device chassis engages the second connector system. The second test device sends a test signal through a channel on the test backplane such that the test signal is provided to the loop back circuit on the first test device and received back through the channel. The second test device analyzes the test signal that is received to determine a testing compliance of the channel on the test backplane.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: January 24, 2017
    Assignee: Dell Products L.P.
    Inventors: Umesh Chandra, Timothy Thinh Mai
  • Patent number: 9513985
    Abstract: An approach for improving efficiency of cycle-reproducible debug in a multi-core environment is provided. The approach executes an exerciser image on one or more cores, wherein the exerciser image includes one or more different seeds. The approach determines a seed from the one or more different seeds that locates a fail-condition. Responsive to determining a seed from the one or more different seeds that locates the fail condition, the approach determines an upper bound and a lower bound of the fail-condition. The approach determines an exact cycle where the fail-condition occurs. The approach constructs a multi-cycle trace for the fail-condition.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: December 6, 2016
    Assignee: International Business Machines Corporation
    Inventors: James N. Klazynski, Amir Nahir
  • Patent number: 9404967
    Abstract: Implementations of the present disclosure involve an apparatus and/or method for mixing high speed and low speed clock signals during structural testing of a digital integrated circuit to improve the test precision and efficiency. In particular, the apparatus and/or method allow for a testing device to perform stuck-bit testing of the circuit by releasing one or more clock cycles of a low speed clock signal. Further, without having to reset the testing of the circuit, at-speed testing of the circuit may be conducted by the testing device. In one embodiment, at-speed testing occurs by activating a mode signal associated with the circuit design that instructs one or more clock cycles from an internal clock signal to the circuit to be released. The testing device may return to stuck-bit testing at a low speed clock signal, or continue with at-speed testing using the high speed internal clock signal.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: August 2, 2016
    Assignee: Oracle International Corporation
    Inventor: Ali Vahidsafa