Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for detecting utterances of a key phrase in an audio signal. One of the methods includes receiving, by a key phrase spotting system, an audio signal encoding one or more utterances; while continuing to receive the audio signal, generating, by the key phrase spotting system, an attention output using an attention mechanism that is configured to compute the attention output based on a series of encodings generated by an encoder comprising one or more neural network layers; generating, by the key phrase spotting system and using attention output, output that indicates whether the audio signal likely encodes the key phrase; and providing, by the key phrase spotting system, the output that indicates whether the audio signal likely encodes the key phrase.

Abstract: Disclosed is a processor chip that includes on-chip and off-chip software. The chip is optimized for hyperdimensional, fixed-point vector algebra to efficiently store, process, and retrieve information. A specialized on-chip data-embedding algorithm uses algebraic logic gates to convert off-chip normal data, such as images and spreadsheets, into discrete, abstract vector space where information is processed with off-chip software and on-chip accelerated computation via a desaturation method. Information is retrieved using an on-chip optimized decoding algorithm. Additional software provides an interface between a CPU and the processor chip to manage information processing instructions for efficient data transfer on- and off-chip in addition to providing intelligent processing that associates input information to allow for suggestive outputs.

Abstract: Embodiments of the present disclosure provide a test method and apparatus for a control chip, and an electronic device, which relate to the field of semiconductor device test technologies. The control chip includes a built-in self-test BIST circuit. The method is performed by the BIST circuit. The method includes: reading first test vectors stored in a first target memory chip; sending the first test vectors to the control chip; receiving first output information returned by the control chip in response to the first test vectors; and acquiring a first test result of the control chip based on the first output information and the first test vectors corresponding to the first output information. By means of the technical solutions provided in the embodiments of the present disclosure, so that a storage space for test vectors can be enlarged, and the test efficiency can be increased.

Abstract: Embodiments of the present disclosure provide a test method and apparatus for a control chip, an electronic device, relating to the field of semiconductor device test technology. The method includes: reading first test vectors stored in a first target memory chip; sending the first test vectors to the control chip; receiving first output information returned by the control chip in response to the first test vectors; and acquiring a first test result of the control chip based on the first output information and the first test vectors corresponding to the first output information. By means of the technical solutions provided in the embodiments of the present disclosure, a memory chip can be used for storing test vectors for a control chip, so that a storage space for test vectors can be enlarged, and the test efficiency can be increased.

Abstract: A semiconductor integrated circuit (IC) comprising a signal path combiner, comprising a plurality of input paths and an output path. The IC comprises a delay circuit having an input electrically connected to the output path, the delay circuit delaying an input signal by a variable delay time to output a delayed signal path. The IC may comprise a first storage circuit electrically connected to the output path and a second storage circuit electrically connected to the delayed signal path. The IC comprises a comparison circuit that compares outputs of the signal path combiner and the delayed signal, wherein the comparison circuit comprises a comparison output provided in a comparison data signal to at least one mitigation circuit.

Abstract: A method for generating a memory built-in self-test circuit includes steps of providing an editable file, wherein the editable file configured to be edited by a user to customize a memory test algorithm; performing a syntax parsing on the editable file to obtain the memory test data, wherein the memory test data being corresponding to the memory test algorithm; and generating the memory built-in self-test circuit based on the memory test data.

Abstract: A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed by components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.

Abstract: Some embodiments of the invention relate to generating correction information based on global or regional navigation satellite system (NSS) multiple-frequency signals observed at a network of reference stations, broadcasting the correction information, receiving the correction information at one or more monitoring stations, estimating ambiguities in the carrier phase of the NSS signals observed at the monitoring station(s) using the correction information received thereat, generating residuals, generating post-broadcast integrity information based thereon, and broadcasting the post-broadcast integrity information. Other embodiments relate to receiving and processing correction information and post-broadcast integrity information at NSS receivers or at devices which may have no NSS receiver, as well as to systems, NSS receivers, devices which may have no NSS receiver, processing centers, and computer programs.

Abstract: The present invention relates to a self-diagnostic apparatus capable of improving safety of a device under test (DUT) by analyzing a characteristic change of a DUT, such as a semiconductor, a circuit module, or a system, in a safe operating region over time and allowing a regular test and a periodic test to be performed even while the DUT is running.

Abstract: In some examples, a circuit includes a custom control data register (CCDR) circuit having a scan path. The CCDR circuit includes a shift register and an update register. The shift register is configured to receive scan data from a scan data input (CDR_SCAN_IN) on a first clock edge responsive to a scan enable signal (CDR_SCAN_EN) being enabled. The update register is configured to receive data from the shift register on a second clock edge after the first clock edge when the scan enable (CDR_SCAN_EN) is enabled. The update register data is asserted as a scan data output (CDR_SCAN_OUT). The second scan path includes the scan data input, the shift register, the update register, and the scan data output.

Abstract: A method for determining one or more tests suitable for verifying that a circuit conforms to a specification is presented. The specification has at least one state machine. Example circuits are asynchronous circuits. The method includes analysing the specification to automatically determine the one or more tests for circuit verification.

Abstract: A Register Transfer Level (RTL) representation is recovered from a netlist representing an integrated circuit (IC). The netlist is converted to a graph comprising nodes belonging to a set of node types and edges connecting the nodes. The set of node types includes an instance node type representing an electronic component and a wire node type representing signal transfer between components. The graph is converted to a standardized graph by replacing subgraphs of the graph with standardized subgraphs. An RTL representation of the standardized graph is generated by operations including building signal declarations in a hardware description language (HDL) from the wire nodes of the standardized graph and building signal assignments in the HDL from instance nodes of the standardized graph.

Abstract: An information handling system includes a transmitter that transmits data over a channel to a receiver. The transmitter operates to transmit a test sequence including a repeating sequence of a number of logic 1's and the number of logic 0's. The receiver operates to detect noise injected onto the channel based upon an output from a data eye sampler in response to the test sequence.

Abstract: Embodiments relate to a power monitoring circuit. The power monitoring circuit includes a divider circuit that generates a reference voltage that is inversely proportional to a regulator voltage. Moreover, the power monitoring circuit includes an integrator that generates an integrator voltage by integrating one or more regulator currents. The power monitoring circuit additionally includes a comparator for comparing the output of the divider circuit and the output of the integrator. The comparator of the power monitoring circuit generates an output signal in response to the integrator voltage being larger than the reference voltage.

Abstract: A method of additive manufacturing of a three-dimensional object. The method comprises: sequentially dispensing and solidifying a plurality of layers comprising (i) a stack of model layers arranged in a configured pattern corresponding to the shape of the object and being made of a modeling material, (ii) a sacrificial structure having a stack of sacrificial layers made of an elastomeric material, and (iii) a stack of intermediate layers made of a support material having an elastic modulus less than the elastomeric material and being between the stack of model layers and the sacrificial structure; and applying a peeling force to the sacrificial structure (e.g., in dry environment) to remove the sacrificial structure, and to expose the stack of model layers and/or the stack of intermediate layers beneath the sacrificial structure.

Abstract: Disclosed is a processor chip that includes on-chip and off-chip software. The chip is optimized for hyperdimensional, fixed-point vector algebra to efficiently store, process, and retrieve information. A specialized on-chip data-embedding algorithm uses algebraic logic gates to convert off-chip normal data, such as images and spreadsheets, into discrete, abstract vector space where information is processed with off-chip software and on-chip accelerated computation via a desaturation method. Information is retrieved using an on-chip optimized decoding algorithm. Additional software provides an interface between a CPU and the processor chip to manage information processing instructions for efficient data transfer on- and off-chip in addition to providing intelligent processing that associates input information to allow for suggestive outputs.

Abstract: A circuit device is provided with a first codec including a first portion of a logic circuit and a second codec including a second portion of the logic circuit. The circuit device can also include a plurality of first scan chains coupled to the first codec and configured to shift a delayed test vector onto the first codec, wherein the delayed test vector is a test vector with a phase delay. A plurality of second scan chains can be coupled to the second codec and configured to shift the test vector onto the second codec.

Abstract: Systems, methods, and machine-readable instructions stored on machine-readable media are disclosed for adjusting a time limit for a test based on one or more indications of availability. A test is executed, wherein the test includes a time limit. A determination is made that the time limit is exceeded. In response, the time limit is adjusted based on one or more indications of availability.

Abstract: Methods, apparatuses and electronic devices for testing a memory of a chip are provided. Specifically, the chip includes a plurality of operation modules, the operation module includes at least one operation unit, and the operation unit includes at least one memory. The method includes generating a first test vector for a first operation module of the operation modules, and testing the memory in the first operation module by using the generated first test vector independent of other operation modules of plurality of operation modules, where the other operation modules are different from the first operation module.

Abstract: A system or a device can include a processor core comprising one or more hardware processors; a processor memory to cache data; a memory link interface to couple the processor core with one or more attached memory units; and a platform firmware to determine that a device is connected to the processor core across the memory link interface; determine that the device comprises an attached memory; determine a range of at least a portion of the attached memory available for the processor core; map the range of the portion of the attached memory to the processor memory; and wherein the processor core is to use the range of the portion of the attached memory and the processor memory to cache data.

Abstract: Techniques are provided for phase coherent frequency synthesis. An embodiment includes a first phase accumulator to accumulate a frequency control word (FCW) at a clocked rate to produce a first digital phase signal representing phase data corresponding to phase points on a first sinusoidal waveform. The embodiment also includes a second phase accumulator to produce an incrementing reference count at the clocked rate and multiply it by the FCW to produce a second digital phase signal representing phase data corresponding to phase points on a second sinusoidal waveform. The multiplication is performed in response to change in the FCW. The embodiment further includes a multiplexer to select between the first and second digital phase signals based on completion of the multiplication. The embodiment also includes a phase-to-amplitude converter to generate digital amplitude data corresponding to the phase points on a sinusoidal waveform associated with the selected digital phase signal.

Abstract: A die-to-die repeater circuit includes a transmit circuit coupled to a die-to-die interconnect, the transmit circuit including at least one flip flop to function as a part of a linear feedback shift register (LFSR) to transmit a value across the die-to-die interconnect for design for test (DFT) to check proper operation of the die-to-die interconnect, and a receive circuit coupled to the die-to-die interconnect, the receive circuit including at least one flip flop to function as part of a multiple input shift register (MISR).

Abstract: Described herein is a system that includes a memory component and a processing device coupled to the memory component. The processing device identifies, in a test mode, a memory location of a memory component that is available to write test data, and detects a loss of power to the system while in the test mode. Responsive to detection of the loss of power, the processing device performs a continuous sequence of write operations to write the test data to the memory location using holdup energy until an amount of holdup energy is expended. After reboot of the system, the processing device determines a number of write operations successfully completed in the memory location by the continuous sequence of write operations before the amount of holdup energy is expended, and determines whether the number of write operations successfully completed satisfies a defect criterion.

Abstract: A method for testing mass-produced PCBs and other electronic components more efficiently, the method includes setting testing parameters based on historical test data and a target decision index, obtaining a first specified number of the target objects to have the full test, and calculating a first yield based on the current test result. The method determine whether the first yield is less than the first yield threshold yield, and obtaining a second specified number of the target objects from the remaining target objects to have the full test, and calculate a second yield when the first yield is larger than or equal to the first yield threshold value. The method further determine whether the second yield is less than the second yield threshold value according to a second comparing command and select some of the remaining target objects to have a sampling test.

Abstract: Provided are a method, computer-readable medium, and a system for determining rupture envelopes for a fault system. The method includes obtaining a representation that depicts one or more faults in a region of the earth as triangulated surfaces; selecting variables from among parameters comprising stress ratio, orientation of far field stress maximum principal stress, intermediate principal stress, minimum principal stress for the far field stress, and sliding friction and cohesion of the fault system; determining a strain energy of a triangular element based on a friction coefficient, a normal stress on the triangular element, and a cohesion for the variables; summing the strain energy of each triangle in the triangulated surfaces to yield an effective shear strain energy; extracting one or more iso-surfaces of the effective shear strain energy based on the summing; and creating rupture envelopes for specific values of the effective shear strain energy.

Abstract: A system for testing a circuit comprises scan chains, a controller, and hold-toggle circuitry. The hold-toggle circuitry is configured to allow, according to a control signal generated by the controller, some scan chains in the scan chains to operate in a full-toggle mode and some other scan chains in the scan chains to operate in a hold-toggle mode when a test pattern is being shifted into the scan chains. The control signal also contains information of a hold-toggle pattern for the scan chains operating in the hold-toggle mode. The hold-toggle pattern repeats multiple times when the test pattern is being shifted into the scan chains.

Abstract: A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE 1500 core test wrappers and provides high test data bandwidth to the wrappers from an external tester. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. The test architecture includes a selector circuit for selecting a core for testing. Additional features and embodiments of the device test architectures are also disclosed.

Abstract: A target vector representing a usage parameter corresponding to a test of a memory component is generated. A test sample is assigned to the target vector and a set of path variables are generated for the test sample. A test process of the test is executed using the test sample in accordance with the set of path variables to generate a test result. A failure associated with the test result is identified.

Abstract: A circuit device is provided with a first codec including a first portion of a logic circuit and a second codec including a second portion of the logic circuit. The circuit device can also include a plurality of first scan chains coupled to the first codec and configured to shift a delayed test vector onto the first codec, wherein the delayed test vector is a test vector with a phase delay. A plurality of second scan chains can be coupled to the second codec and configured to shift the test vector onto the second codec.

Abstract: An apparatus for generating a test case for a vehicle includes a communication device that receives vehicle data from an electronic device. The apparatus also includes a controller that converts the vehicle data to a state diagram, patterns the state diagram, and generates the test case based on the patterned state diagram.

Abstract: Systems, methods, and computer-readable media are described for performing fault detection and localization using Combinatorial Test Design (CTD) techniques and generating a regression bucket of test cases that expose a detected fault in a System Under Test (SUT). The SUT may be a hardware system or a software system. Further, the fault detection and localization may be performed while adhering to architectural restrictions on the SUT.

Abstract: A method of writing data utilizes a pipeline to process write operations of a first plurality of data words addressed to a memory bank. The method also comprises writing a second plurality of data words into an error buffer, wherein the second plurality of data words comprises data words that are awaiting write verification. Additionally, the method comprises searching for at least one data word that is awaiting write verification in the error buffer, wherein verify operations associated with the at least one data word occur in a same row as the write operation. Finally, the method comprises determining if an address associated with any of the at least one data word is proximal to an address for the write operation and preventing a verify operation associated with the at least one data word from occurring in a same cycle as the write operation.

Abstract: A memory system includes a memory device including dies, each of the dies including planes, each of the planes including blocks, each of the blocks including pages; and a controller suitable for controlling the memory device, the controller comprising: a memory including a mapping table which includes map chunks generated through dividing map data into map chunks each of a unit size; a pattern determination engine suitable for determining patterns with respect to each of the map chunks received from the memory; and a compression engine suitable for determining whether to perform compression on the map chunks, based on pattern determination results for the map chunks determined by the pattern determination engine, and performing compression on those map chunks for which performing compression was determined.

Abstract: Disclosed herein are voltage driver circuits and methods of operating the same to provide a variable output voltage that is suitable for use in ATE to provide a large number of test signals with accurate voltage levels at high data rates using components that consume relatively low power. According to an aspect, a change in output current in a voltage driver related to changing output voltage may be offset by a stabilization current generated by a correction driver for the voltage driver, such that supply currents drawn from the supply voltages can remain substantially stable. The correction driver may be connected to one or more supply voltages, and programmed to output a stabilization current that offsets changes in supply currents arising from changing of the programmed output of the voltage driver circuit. Such a driver may enable a test system to more precisely test semiconductor devices.

Abstract: A scan chain may be formed throughout an integrated circuit in which the scan chain is coupled to a set of pins via bi-directional input/output (I/O) buffers. A test pattern may be received from an external tester using the set of I/O pins and buffers operating in parallel. The test pattern is scanned into the scan chain using a shift clock operating at a first rate. The test pattern is then provided to combinatorial logic circuitry coupled to the scan chain. A response pattern is captured in the scan chain and then scanned from the scan chain using a shift clock operating at a second rate that is slower than the first rate. The response pattern is provided to the external tester using the same set of I/O pins and buffers operating in parallel.

Abstract: A data recording system includes a host terminal and a data recorder. The host terminal defines a first module card to be corresponding to a first data channel and a first module card slot of the data recorder. The first module card is inserted into the first module card slot, and the data recorder stores a first type of data captured from the first data channel to the first module card. The host terminal has the data recorder stop capturing the first type of data, and defines a second module card to be corresponding to a second data channel and the first module card slot of the data recorder. The data recorder is shut down, and the first module card is dismounted from the first module card slot. The second module card is inserted into the first module card slot, and the data recorder is rebooted.

Abstract: Embodiments are directed to a computer implemented method and system for the testing, characterization and diagnostics of integrated circuits. A system might include a device under test, such as an integrated circuit, that includes an adaptive microcontroller. The method includes loading a testing program for execution by the adaptive microcontroller, causing the microcontroller to execute the testing program. Once results from the testing program are received, the testing program can be adaptively modified based on the results. The modified testing program can be run again. The testing program can modify parameters of the integrated circuit that are not externally accessible. Other embodiments are also disclosed.

Abstract: Methods and computer-readable media for testing integrated circuit designs implement a physically efficient scan by optimally balancing and connecting scan segments in a 2-dimensional compression chain architecture. A compression architecture that provides an optimal and balanced configuration of scan segments in 2D compression grids to not only decrease test time, but also to maximize compression efficiency and limit wiring congestion for IC designs that contain complex scan segments facilitates efficient scanning of data by bisecting the elements into balanced partitions of the same target scan length. A segment padding algorithm, followed by a bisecting algorithm and ultimately an element swapping algorithm may be applied to optimally balance and connect scan segments in 2-D compression chains, optimizing an efficient compression architecture which minimizes scan testing resources and time.

Abstract: A system and method is provided for restoring a 3D tomographic model of the Earth's subsurface geology from the present-day to a past restoration time. Whereas at the present time all faults represent active discontinuities, at a past restoration time some faults have not yet formed. Accordingly, the restored model divides the fault network into ?-active faults (discontinuous surfaces for faults that intersect the layer deposited at the past restoration time) and ?-inactive faults (continuous surfaces for faults that do not intersect the layer deposited at the past restoration time). A new 3D restoration transformation is also provided that uses linear geological constraints to process the restoration model in less time and generate more accurate geological images.

Abstract: A memory device, includes: a memory array comprising a plurality of bit cells arranged along a plurality of rows and along a plurality of columns, respectively; and a control logic circuit coupled to the memory array, and configured to determine respective locations of a first plurality of diagonal bit cells of the memory array for testing one or more peripheral circuits coupled to the memory array, wherein the control logic circuit is further configured to determine respective locations of at least a second plurality of diagonal bit cells of the memory array for testing the one or more peripheral circuits, wherein a number of the plurality of rows is different than a number of the plurality of columns and the first plurality of diagonal bit cells span a first equal number of rows and columns and the second plurality of diagonal bit cells also span a second equal number of rows and columns.

Abstract: In one embodiment, a processor includes at least one core and an interface circuit to interface the at least one core to additional circuitry of the processor. In response to an in-field self test instruction, at least one core may save state to a low power memory, enter into a diagnostic sleep state and execute an in-field self test in the diagnostic sleep state in which the at least one core appears to be inactive. Other embodiments are described and claimed.

Abstract: A method for combining verification data may include using a processor, obtaining verification data and a verification model from each of a plurality of verification engines relating to different verification methods, the verification data relating to a plurality of verification tests that were conducted on a design under test (DUT) using the plurality of verification engines; using a processor, merging the verification models obtained from the plurality of verification engines into a merged verification model; using a processor, calculating a combined verification metric grade for a plurality of verification entities in the merged verification model using verification metric grades for each of the plurality of verification entities calculated from the verification data obtained from the plurality of engines and applying a combined verification metric grade rule; and outputting the combined verification metric grade via an output device.

Abstract: According to some embodiments, a tester tests one or more DUTs by utilizing one or more respective reference devices. The tester comprises one or more test sites and one or more test circuits operatively coupled to each of the test sites. Each test site is configured to: hold a reference device and a DUT, transmit a transmitted electromagnetic RF signal including a test data pattern to the DUT, and receive a received electromagnetic RF signal emitted from the DUT. The test circuits are configured to: receive a first electrical signal converted from the received electromagnetic RF signal, extract first data from the first electrical signal, determine a first error rate between the test data pattern and the first data, and generate a test result on the basis of the first error rate.

Abstract: The system includes a positioning system for mounting the circuit board to be tested and for mounting a sensor assembly. A control system registers the position of the sensor assembly relative to the circuit board to be tested and for moving the sensor assembly about the circuit board. The sensor assembly detects noise or other emissions generated by the circuit elements on the board. The noise emissions are separate from the operating signals of the circuit. The spectrum analyzer receives the emissions from the sensor assembly and produces frequency spectrum data over a selected frequency range with amplitude information. A processing system then compares the frequency spectrum information with frequency spectrum information from boards known to be good and provides information as to any differences and whether they are in an acceptable tolerance range.

Abstract: An on-chip TDDB degradation monitoring and failure early warning circuit for SoC. A control circuit module converts Q1 and Q0 signals into a switch state control signal and outputs the switch state control signal to a digital conversion module for TDDB performance degradation. A MOS transistor of a first MOS transistor circuit within the digital conversion module for TDDB performance degradation is in a stress state of a supply voltage, and a MOS transistor of a second MOS transistor circuit is in a non-stress state. The first and second MOS transistor circuits output a first frequency value and a second frequency value to the output selection module. The output selection module outputs the first frequency value from the digital conversion module to the counter B for recording, or outputs the second frequency value to the counter A for recording. The counter module determines the degradation level of TDDB performance.

Abstract: A semiconductor memory device includes a NAND memory including a plurality of blocks, each of which is a unit of data erasing, and a controller. The controller is configured to select an initial value from a group of initial values, based on an address of the NAND memory in which data are to be written, set a value corresponding to the selected initial value to a linear feedback shift register circuit, randomize the data using an output value of the linear feedback shift register circuit, and write the randomized data to the address of the NAND memory. A size of each of the blocks S is smaller than 2n-1 bytes, n being a number of registers included in the linear feedback shift register circuit.

Abstract: An apparatus and a method is provided that comprises at least one first processing unit configured to run at least one first computer program application capable of receiving and processing signals received from at least one interface or device connected to said first processing unit, at least one second processing unit configured to run at least a second computer program application capable of further processing at least some information processed in said first processing unit.

Abstract: A method for testing a data packet signal transceiver device under test (DUT). Following initial signal communications with a DUT, timing of further transmissions by the DUT may be effectively controlled by transmitting congestive communication channel signals to cause the DUT to detect apparent communication channel activity and in response thereto delay its own signal transmissions.

Abstract: A method and circuit for implementing enhanced diagnostics with intelligent pattern combination in automatic test pattern generation (ATPG), and a design structure on which the subject circuit resides are provided. A random fault is selected in the design. A test pattern is generated and applied the test pattern to a design under test to test the selected random fault. The test is re-simulated to determine faults that are covered by the applied test pattern. A next iteration of test pattern generation includes selecting a fault that is based upon the previous test pattern generation for generating new test patterns.

Abstract: A semiconductor integrated circuit connected to another circuit via differential transmission lines of N channels (where N is a natural number), the circuit includes: N pairs of differential output pins each of which is connected to a differential transmission line of a corresponding channel; N differential transmitters each of which is configured to drive a differential transmission line of a corresponding channel; and an abnormality detection circuit configured to detect abnormality in the differential transmission lines. The abnormality detection circuit includes: N amplifiers configured to detect a potential difference between differential transmission lines of corresponding channels; N first comparators each of which is configured to compare an output voltage of a corresponding amplifier with a first threshold voltage; and a logic circuit configured to detect abnormality of a first mode in a differential transmission line of a corresponding channel based on an output from each of the N first comparators.