Abstract: A test board for testing a memory signal includes a first surface and a second surface. The first surface of the test board comprises a raised region and a non-raised region. The raised region is provided with a first connection area connectable to a main board, and a level at which the raised is located is higher than a level at which the non raised region is located by a preset value. The second surface of the test board includes a test area and a second connection area connectable to a memory chip. The test board is provided with a first connection harness for connecting the test area to the first connection area and a second connection harness for connecting the test area to the second connection area, to enable the memory signal of the memory chip to be tested based on the test area.

Abstract: A memory chip test method includes: a mode register write command is sent to a memory chip to control a memory chip to enter a test mode of Write Clock to clock leveling (Wck2ck Leveling); a first preset time is set, and a read and write clock signal is sent to the memory chip after waiting for the first preset time; a predicted value of the Wck2ck Leveling is determined according to the first preset time and a system clock cycle; after sending the read and write clock signal and waiting for a second preset time, a test data output port of the memory chip is detected to obtain a test value; and the test value and the predicted value are compared to determine whether the memory chip is abnormal. A method for testing a Wck2ck Leveling function is provided.

Abstract: A power control device for use in an AC power grid for regulating an electrical power a load that is supplied by the AC power grid consumes. The power control device has a frequency sensing functional block for detecting a deviation of the grid frequency from a nominal grid frequency and a logic functional block for performing a load adjustment process during which the power the load consumption is reduced. The load adjustment process is based at least in part on the variation of the frequency of the AC power grid. The load adjustment process is design such that for a plurality of power control devices the individual response produce a grid-wide effect that compensates imbalance between power generation and load in fashion that may reduce unwanted distortion in the AC power grid, such as flicker.

Abstract: The present disclosure discloses a data processing method and related products, in which the data processing method includes: generating, by a general-purpose processor, a binary instruction according to device information of an AI processor, and generating an AI learning task according to the binary instruction; transmitting, by the general-purpose processor, the AI learning task to the cloud AI processor for running; receiving, by the general-purpose processor, a running result corresponding to the AI learning task; and determining, by the general-purpose processor, an offline running file according to the running result, where the offline running file is generated according to the device information of the AI processor and the binary instruction when the running result satisfies a preset requirement. By implementing the present disclosure, the debugging between the AI algorithm model and the AI processor can be achieved in advance.

Abstract: In association with unit and integration testing of a software application, a test conflict guard can detect whether test cases are independent and use distinct database data, or are related or dependent test cases that use the same database data. The test conflict guard can detect any related or dependent test cases in a group of test cases, which may cause testing errors if executed in different parallel threads. The test conflict guard can accordingly block test execution until the group of test cases are verified as independent test cases.

Abstract: Described herein are systems, methods, and other techniques for identifying redundant parameters and reducing parameters for testing a device. A set of test values and limits for a set of parameters are received. A set of simulated test values for the set of parameters are determined based on one or more probabilistic representations for the set of parameters. The one or more probabilistic representations are constructed based on the set of test values. A set of cumulative probabilities of passing for the set of parameters are calculated based on the set of simulated test values and the limits. A reduced set of parameters are determined from the set of parameters based on the set of cumulative probabilities of passing. The reduced set of parameters are deployed for testing the device.

Abstract: A test system can receive a test signal from a device under test (DUI) via a first signal path. A comparator circuit can receive the test signal and, in response, generate an intermediate output signal based on a magnitude relationship between the test signal a comparator reference signal. A compensation circuit can generate a correction signal that is complementary to a portion of the received test signal, such as to correct for loading effects of the first signal path. The test system can include an output circuit configured to provide a corrected differential output signal that is based on a combination of the intermediate output signal and the correction signal.

Abstract: Aspects of the disclosure relate to validating autonomous control software for operating a vehicle autonomously. For instance, the autonomous control software is run through a driving scenario to observe an outcome for the autonomous control software. A validation model is run through the driving scenario a plurality of times to observe an outcome for the model for each of the plurality of times. Whether the software passed the driving scenario is determined based on whether the outcome for the software indicates that a virtual vehicle under control of the software collided with another object during the single time. Whether the validation model passed the driving scenario is determined based on whether the outcome for the model indicates that a virtual vehicle under control of the model collided with another object in any one of the plurality of times. The software is validated based on the determinations.

Abstract: The present invention provides a chip test method, apparatus, device, and system. The chip test system may include: a test equipment, including n chip selection signal lines, m sets of first signal lines, and m*n sets of second signal lines; and m*n chip test sites, wherein each chip test site may be coupled to one of the n chip selection signal lines and one of the m sets of first signal lines, each of the m*n chip test sites may correspond to a unique combination of a chip selection signal line and a first signal line coupled thereto, and each chip test site may be correspondingly coupled to one of the m*n sets of second signal lines. According to an embodiment of the present invention, the limited pins of a test equipment may be used to implement individual control of multiple chips.

Abstract: Disclosed is a capability test method based on a joint test support platform. The method includes steps of describing an initial capability in a test, combining a capability to be developed based on the initial capability, and determining an evaluation strategy and a joint task background information of the test. Further, the method includes generating a logical shooting range for the joint test support platform according to the joint task background information, developing a test scenario according to the joint task background information and the logical shooting range, decomposing the test scenario, determining a test plan corresponding to the test scenario, executing the test according to the test plan, analyzing and evaluating a test result of the test, and generating one or more joint capability evaluation reports for the test.

Abstract: A processor is described that includes a plurality of compute units. One or more test pattern generators generates one or more test patterns and inputs the one or more test patterns into one or more of the plurality of compute units during testing, which testing includes processing of the one or more test patterns by one or more of the plurality of compute units. One or more control and sequencing logic units identifies an idle period during normal use of the processor in which a compute unit of the plurality of compute units is idle. The one or more control and sequencing units controls the test pattern generator to generate and input the one or more test patterns to the idle compute unit and controls the compute unit to process the one or more test patterns during the idle period. One or more comparators compares a result of testing with an expected result of testing to determine if the compute unit is functioning correctly.

Abstract: A method for testing a system under test (SUT) in an active environment to identify cause of a soft failure includes recording a first difference vector by executing a set of test cases on a baseline system and monitoring performance parameters of the baseline system before and after executing the test cases. Each performance record represents differences in the performance parameters of the baseline system from before and after the execution of a corresponding test case. The method further includes, similarly, recording a second difference vector by executing the test cases on the SUT and monitoring performance parameters of the SUT before and after executing the test cases. The method further includes identifying an outlier performance record from the second difference vector by comparing the difference vectors and further, determining a root cause of the soft failure by analyzing a test case corresponding to the outlier.

Abstract: A building management system for monitoring equipment status is provided. The building management system includes a processing circuit configured to generate one or more constants for a piece of building equipment based on thresholds and device specific templates. The constants are equation based relationships between a value and a threshold. The processing circuit is further configured to generate one or more sub-rules based on the one or more constants and one or more equipment points. The sub-rules are equation based relationships between the one or more constants and the one or more equipment points. The processing circuit is further configured to generate a rule based on the one or more sub-rules and the one or more equipment points. The rule is an equation based relationship between the one or more sub-rules and the one or more equipment points and indicates whether the piece of building equipment is experiencing a fault.

Abstract: An IC chip test engine selects an instrument of an IC design based on an instrument access script, wherein the selected instrument comprises an IP block and a test data register (TDR) logically arranged upstream from the IP block. The IC chip test engine can also identify a set of SIBs gating access to the selected instrument and select a scan chain for operating the set of SIBs to control access to the selected instrument. The IC chip test engine augments the scan chain with data to cause at least a furthest downstream SIB of the set of SIBs that gates access to the selected instrument to transition to an opened state. The IC chip test engine can generate a set of load vectors for the scan chain to load the TDR of the selected instrument with data to apply a respective test pattern to the IP block.

Abstract: An embodiment of a semiconductor package apparatus may include technology to map a collection of data into two or more mathematical graph representations of the data based on a configurable set of rules that one of preserves or enhances relationships or properties of the data, and organize the two or more graph representations into two or more clusters of data based on graph information entropy and one or more parameters. Other embodiments are disclosed and claimed.

Abstract: A programming session may be initiated to a vehicle ECU by an update device. A software update for the ECU may be authenticated by the update device using an authentication key. When an authentication result indicates successful authentication, the ECU software update is sent by the update device over the in-vehicle network to the ECU. The ECU may then flash a memory with the ECU software update. The authentication key may be obtained from the ECU. The update device may be a vehicle telematics control unit or a service tool coupled to a connector of the vehicle.

Abstract: A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device controls a test mode. The first semiconductor device outputs a chip identification and receives external data. The second semiconductor device includes a plurality of memory chips. At least one of the plurality of memory chips are activated based on the chip identification to store input data into each of the plurality of memory chips that have been activated while a write operation is performed in the test mode. At least two of the plurality of memory chips are activated based on the chip identification to output the stored input data as the external data while a read operation is performed in the test mode.

Abstract: Testing devices such as integrated circuits (IC) with integrated antennas configured for millimeter wave (mmW) transmission and/or reception. A DUT may be mounted to an interface in a measurement fixture (e.g., a socket, anechoic chamber, etc.). Power and data connections of the DUT may be tested over the interface, which may also provide connections (e.g., wired) for input/output signals, power, and control and may also provide positioning. Radio frequency (RF) characteristics of the DUT may be tested over-the-air using an array of antennas or probes in the radiating Fresnel zone of the DUT's antennas. Each of the antennas or probes of the array may incorporate a power detector (e.g., a diode) so that the RF radiating pattern may be measured using DC voltage measurements. Measured voltage measurements may be compared to an ideal signature, e.g., voltage measurements expected from an ideal or model DUT.

Abstract: An image forming apparatus includes: a controller that controls the image forming apparatus; a memory that stores noise levels produced by a plurality of devices constituting the image forming apparatus during operation of the devices; and a microphone that accepts a speech instruction for the image forming apparatus. The controller accepts a job, detects a speech level from the speech accepted by the microphone, compares the detected speech level with a noise level that corresponds to the job to be executed in the image forming apparatus and that has been read from the memory, and controls, based on a result of the comparison, which one of a process of accepting the speech instruction and a process of executing the job in the image forming apparatus should be preferentially performed.

Abstract: A measurement method, comprising acquiring, by a measurement apparatus, a plurality of at least three measurement segments, wherein each measurement segment is acquired at a corresponding measurement time, and wherein time information is gathered, wherein the time information allows to derive ratios of time differences between said measurement times; and playing back the plurality of at least three measurement segments, wherein each measurement segment is played back at a corresponding playback time, and wherein, using said time information, the playback times are chosen such that ratios of time differences between said playback times correspond to ratios of time differences between the corresponding measurement times.

Abstract: An image reading apparatus, including: an image reading unit configured to read an image of an original; an image reading controller configured to control the image reading unit; a signal transmission cable configured to connect the image reading unit and the image reading controller; a drive portion configured to move the image reading unit; and an image signal generation portion, provided in the image reading unit, configured to generate an image signal based on a predetermined pattern, wherein the image reading controller is configured to obtain, through the signal transmission cable, the image signal output from the image signal generation portion while causing the drive portion to move the image reading unit to change a bending state of the signal transmission cable, and to detect whether there is an abnormality in the signal transmission cable based on a pattern of the image signal obtained by the image reading controller.

Abstract: A method and system generates extended patterns from base patterns with an automatic pattern generation engine. The method and system tests the extended patterns with an automatic pattern testing engine. The patterns correspond to configurations for implementing cloud-based applications. The patterns are extendable to make additional extended patterns. Extended patterns carry the characteristics of the patterns from which they were extended. Updating a base pattern with new security measures causes a cascade effect that updates all extended patterns that descend from the base pattern.

Abstract: A data storage device can detect for a failure in decoding of an x-bit row address and/or a y-bit column of an (x+y)-bit address. The data storage device decodes the x-bit row address and/or the y-bit column address to provide wordlines (WLs) and/or bitlines (BLs) to access one or more cells from among a memory array of the data storage device. The data storage device compares one or more subsets of the WLs and/or of the BLs to each other to detect for the failure. The data storage device determines the failure is present in the decoding of the x-bit row address and/or the y-bit column of the (x+y)-bit address when one or more WL and/or BL from among the one or more subsets of the WLs and/or the BLs differ.

Abstract: A method of reconfiguring a current debug configuration of a debug unit connected to a peripheral circuit on an integrated circuit chip. The method comprises the debug unit collecting debug data of the peripheral circuit and outputting the debug data in a message stream. The debug unit receives a debug reconfiguration command. The debug unit transmits an indication of the current debug configuration, then reconfigures the current debug configuration to a new debug configuration in accordance with the debug reconfiguration command, then transmits an indication of the new debug configuration. The indication of the current debug configuration and the indication of the new debug configuration are transmitted adjacent to the debug data in the message stream.

Abstract: A method for detecting abnormalities in network element operation. The method includes monitoring at least a portion of the network element for abnormalities and making a determination that an abnormality exists, in response to the monitoring, and based on the determination, tracking the abnormality. An abnormality includes a measured performance that deviates from a nominal performance, but that does not cause erroneous behavior of the network element.

Abstract: One example includes a test system that includes a printed circuit board and a switching interposer board. The switching interposer board is comprised of a probe point, a first bus, a second bus, and a set of switches. Each switch includes a first terminal, a second terminal, and a third terminal, the first terminal being coupled to a respective pin of an integrated circuit device, the second terminal being coupled to the first bus, and the third terminal being coupled to the second bus. Each of the set of switches have a first state that selectively couples a pair of the pins of the integrated circuit device to each other through the first bus during a short test, and a second state that selectively couples at least one of the pins of the integrated circuit device to the probe point through the second bus during a voltage level spike test.

Abstract: A printer is disclosed, which comprises a frame, an image forming module, a controller, a light guide unit, and an optical detector. The image forming module is disposed opposite to the frame and forms a passage. The light guide unit is disposed in the frame and is connected to the controller. The optical detector comprises an illuminating part and a receiving part. The illuminating part illuminates a beam to the light guide d unit, and the receiving part is for receiving the light.

Abstract: A conversational agent capability assessment method, system, and computer program product, includes obtaining data to create at least one scenario for testing a conversational agent, performing a set of tests using a scenario of the at least one scenario created to assess a capability of the conversational agent, and comparing a result of the capability from the set of tests with an expected result of the scenario.

Abstract: A semiconductor device includes an adjusting circuit that transmits a control signal to a device to be controlled according to a transmission cycle synchronized with a reference clock. The device to be controlled has a first period during which the control signal is allowed to be supplied to the device to be controlled and a second period during which the supplying of the control signal to the device to be controlled is not preferable compared to that in the first period. The adjusting circuit is configured to, when a transmission timing of the control signal determined according to the transmission cycle is within the second period, adjust the transmission timing of the control signal so that the control signal will be transmitted in the first period.

Abstract: A vehicle may receive a software update to be installed to a vehicle electronic control unit (ECU). The vehicle ECU may download a software update received from a server to a first storage; generate a nonce value associated with the software update; send to the server, a swap authorization request including the generated nonce value; receive a swap authorization including the nonce value and a command-and-control signature from the server; validate the signature and the nonce value from the swap authorization; and reboot using the first storage instead of a second storage when the recovered nonce value matches the generated nonce value.

Abstract: An apparatus and method for detecting a cable fault which simultaneously apply a plurality of measurement frequencies mutually orthogonal to a cable and estimate reflection coefficients at the measurement frequencies using filters for filtering only the respective measurement frequencies to reduce a time taken to detect a cable fault.

Abstract: A disclosed configuration is for identifying at least one failure indicating scan test cell of a circuit-under-test, CUT, the CUT having a plurality of scan test cells, is provided. The configuration comprises generating a plurality of error signatures by means of a compactor of the CUT, wherein each of the error signatures of the plurality of error signatures consist of a respective sequence of bits comprising at least one failure indicating bit, assigning each error signature to at least a first, a second and a third signature type according to a total number of failure indicating bits of the respective error signature and mapping at least a predefined minimum number of error signatures to respective scan test cells of the plurality of scan test cells. For each error signature, a priority of the mapping is determined by the signature type the respective error signature has been assigned to.

Abstract: A method of detecting correlated operations in a common storage. The method comprises providing at least one input operation, each the input operation being designated to write uniquely identifiable data on a memory unit of an application, monitoring a plurality of output operations of the application, each the output operation includes data read from the memory unit, comparing between the at least one input operation and the plurality of output operations to identify at least one matching group of input and output operations wherein each member of the at least one matching group has correlated written or read data in a common correlated target address in the memory unit, and outputting an indication of the at least one matching group.

Abstract: An automation controller for next generation testing system includes a database including a plurality of scripts and modules, a business layer component, and an automation component. The automation component includes an automation agent and an automation worker. The business layer component is operable to determine a next script from the plurality of scripts and modules and send the next script to the automation component in response to a get next script request sent by the automation component. The automation agent is operable to send the get next script request to the business layer, receive the next script from the business layer, and send the next script to the automation worker for execution. The automation worker is operable to execute the next script or section thereof, obtain a result, send status updates, send proof of life notifications and the result of execution to the automation agent.

Abstract: Systems, apparatuses, and method for handling timeouts in a link state training sequence are described. All modules of a port undergoing link state training placed into an intermediate state prior to entry into the lowest power state.

Abstract: A circuit for efficiently testing digital shadow logic (504, 514) in isolation from an associated non-logic design structure (510) includes a width and delay matched bypass circuit (520) coupled to receive an n-bit input from shadow logic (504) and to generate therefrom an m-bit test output which is selectively connected to replace an m-bit output to the shadow logic (514) from the non-logic design structure (510) in a shadow logic test mode, thereby flexibly emulating the non-logic design structure to allowing separate isolated tests on the shadow logic and on the non-logic design structure.

Abstract: Testing a digital-to-analog converter (DAC), where the test is carried out iteratively for a plurality of digital test signal values, includes: providing the digital test signal to a DAC under test and to a servo; providing, by the DAC under test to a summer, an analog test signal, including converting the digital test signal to the analog test signal; providing, by the summer to an observation latch, a summed signal, including summing the analog test signal and an analog offset signal, the analog offset signal received from a second DAC; providing, by the observation latch to the servo, a sample of the summed signal; providing, by the servo to the second DAC in dependence upon the sample and the digital test signal, a digital offset signal, where the second DAC converts the digital offset signal to the analog offset signal; and storing, as a digital observation, the digital offset signal.

Abstract: A test system is provided. A printed circuit board (PCB) includes a plurality of traces and at least one test point. A central processing unit (CPU) socket including a plurality of first pins and a memory module slot including a plurality of second pins are disposed on the PCB. Each of the second pins is coupled to the corresponding first pin of the CPU socket via the corresponding trace. A CPU interposer board is inserted into the CPU socket, and a memory interposer board is inserted into the memory module slot. The traces form a test loop via the CPU interposer board and the memory interposer board. When an automatic test equipment (ATE) provides a test signal to the test loop via the test point, the ATE determines whether the test loop is normal according to a reflectometry result of the test signal.

Abstract: An embodiment of a method for automated test pattern generation (ATPG), a system for ATPG, and a memory configured for ATPG. For example, an embodiment of a memory includes a first test memory cell, a data-storage memory cell, and a test circuit configured to enable the test cell and to disable the data-storage cell during a test mode.

Abstract: A method of performing a dynamic built-in self-test (BIST). The method includes performing a first test of a circuit on a semiconductor chip. The first test includes a first switch factor. The circuit during the first test is monitored with one or more sensors. A first sensor value of one or more sensors monitoring the circuit is determined. It is also determined whether the first sensor value is within a range of a programmable constant. A second switch factor is determined in response to determining that the first sensor value outside the range of the programmable constant.

Abstract: A Voltage regulator includes a first input terminal configured to receive an input supply voltage, includes a second input terminal configured to receive a regulated output supply voltage as a function of the input supply voltage or to receive a test supply voltage and comprises a power transistor including an input terminal configured to receive the input supply voltage and including an output terminal configured to generate the regulated output supply voltage.

Abstract: According to at least one exemplary embodiment, a synchronous active high reset scan flip flop is provided. The synchronous active high reset scan flip flop may include a data input, a serial input, a test enable input, a reset input, a clock input, a device output. It may also include an AND gate configured to receive the serial input and the test enable input and a multiplexer configured to receive the data input and a first output signal received from the AND gate. The multiplexer is operable in response to the reset input which is used to reset the flip flop in function mode, and permit scan test in test mode. The synchronous active high reset scan flip flop may also include a storage element configured to receive a second output signal received from the multiplexer and operable in response to a clock signal received from the clock input.

Abstract: Systems and methods gather data for debugging a circuit-under-test. The system includes a trigger-and-capture circuit, a data compressor, a direct memory access controller, and a memory controller. The trigger-and-capture circuit is coupled to the circuit-under-test for receiving signals from the circuit-under-test. The trigger-and-capture circuit is configured to assert a trigger signal when the signals match a trigger condition. The data compressor is configured to loss-lessly compress the signals into compressed data. The direct memory access controller is configured to generate write and read requests. The write requests write the compressed data to a memory integrated circuit die, and the read requests read the compressed data from the memory integrated circuit die. The memory controller is configured to perform the write and read requests.

Abstract: A test pattern is sequentially selected from an original test pattern sequence constituted by a plurality of test patterns including a don't care bit. Power consumption in each of regions obtained by substantially equally dividing a layout region of a semiconductor integrated circuit in a case where a don't care value is specified in the selected test pattern and this selected test pattern is applied to the semiconductor integrated circuit is estimated. A searching is conducted for a don't care value of the selected test pattern which minimizes a variation in power consumption among the regions by repeatedly changing the don't care value and repeatedly estimating power consumption in the regions. A new test pattern sequence constituted by a plurality of test patterns including no don't care bit is generated by defining the don't care value obtained by the searching as a don't care value of the selected test pattern.

Abstract: An integrated circuit includes an LBIST controller operative to run a test program on at least one selection of core logic of the integrated circuit to test the operability of the at least one selection of core logic. The integrated circuit also includes a monitoring logic structure operative to detect at least one type of operation executed for the test program from at least one particular control signal activated by the LBIST controller for controlling the at least one selection of core logic to execute the test program from among at least one control signal for controlling operations on the at least one selection of core logic.

Abstract: Aspects of the invention relate to yield analysis techniques for generating root cause distribution information. Suspect information for a plurality of failing dies is first generated using a layout-aware diagnosis method. Based on the suspect information, potential root causes for the plurality of failing dies, and suspect feature weights and total feature weights for each of the potential root causes may then be determined. Next, the probability information of observing a particular suspect that is related to a particular root cause may be extracted. Finally, an expectation-maximization analysis may be conducted for generating the root cause distribution information based on the probability information and the suspect information. Heuristic information may be used to prevent the analysis from over-fitting.

Abstract: A data storage system configured to efficiently search and update system data is disclosed. In one embodiment, the data storage system can attempt to correct errors in retrieved data configured to index system data. Metadata stored along with user data in a memory location can be configured to indicate a logical address associated in a logical-to-physical location mapping with a physical address at which user data and metadata are stored. The data storage system can generate modified versions of logical address indicated by the metadata and determine whether such modified versions match the physical address in the logical-to-physical mapping. Modified versions of the logical address can be generated by flipping one or more bits in the logical address indicated by the metadata. Efficiency can be increased and improved performance can be attained.

Abstract: A testing system includes a circuit board, and an inserting unit. The circuit board includes a first serial interface and a serial chip connected to the first serial interface. The first serial interface connects a second serial interface of a motherboard to receive a first signal of the second serial interface. The inserting unit includes a first plug connected to a pin Transmit Data of the first serial interface. The first plug connects a testing device. When the first signal is transmitted to the first serial interface by the second serial interface, the serial chip receives the first signal and sends the first signal back to the first serial interface. The first plug sends a second signal of the pin Transmit Data to the testing device to be tested.

Abstract: Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.

Abstract: A multi-core processor having a cache, an interconnect system selectively connecting the cache to individual cores, and a interconnect control whereby selected cores are disabled.