Abstract: A circuit and method characterizes a sense amplifier, such as the type utilized in computer memory systems. The sense amplifier characterization circuit comprises a sense amplifier having one or more inputs and an output, a BIT line connected to one of the one or more inputs of the sense amplifier, a register connected to the output of the sense amplifier; and control logic connected to the BIT line. Optionally, the register is further connected to the control logic, and the register is a scan register connectable to a tester. Preferably, the sense amplifier is a differential sense amplifier, and the circuit further comprises a complement BIT line connected to one of the one or more inputs of the sense amplifier. The method produces one or more signals like an output of a memory cell, operates one or more sense amplifier to produce one or more output states on the basis of the one or more signals, and records the one or more output states.

Abstract: A method determines a random permutation of input lines that produced a permuted set of bits in a bitstream. In a source design, the method replaces a logic element whose input lines are permutable with a test function. The source design is processed by a design tool to generate the bitstream including the permuted set of bits. The test function is probed with test values, and the probe results are compared with the permuted set of bits to discover the permutation of the set of bits. The test values can include a message.

Abstract: Apparatus selects a state machine bit group from a plurality of state machine bit groups of a digital system for debugging the state machine connected to the selected bit group. The apparatus is adapted to output the bits of the selected bit group using existing output pins of the digital system, and includes a first multiplexer which is adapted to be connected to the plurality of state machine bit groups for outputting the selected state machine bit group. A second multiplexer is adapted to be connected to system signals and the selected state machine bit group from the first multiplexer, and outputs one of the system signals and the selected state machine bit group via the output pins of the system. A control circuit supplies a first select signal to the first multiplexer for selecting the selected state machine bit group output by the first multiplexer, and supplies a second select signal to the second multiplexer for selecting one of the selected bit group and the system signals.

Abstract: A method and apparatus for built in self test, BIST, of content addressable memory, CAM, and associated random access memory, RAM, is described. The method and apparatus may most beneficially be used for difficult to test situations such as embedded CAM or other memory types. There are no external memory read operations to determine the contents of a memory location, so little additional circuitry or overhead, such as separate read ports, is required on the embedded memory for implementation of the BIST. Only a number generator, a shift register and an OR gate with inputs from each of the CAM word match lines are added to the circuit in which the memory is embedded. The test uses a set of unique data patterns, each one spaced from the others by two bit locations, a walking inversion test, and a complement and reverse pattern test to determine what type of error and the error location.

Abstract: An integration test station for aircraft is provided in which the system is operable with multiple aircraft configurations. The integration test station permits aircraft component designs to be tested and verified in a simulated environment representing integration of the component into the aircraft.

Abstract: A memory tester tests a random access memory device under test (DUT) comprising addressable rows and columns of memory cells, and provides a host computer with enough information to determine how to efficiently allocate spare rows and columns for replacing rows and columns containing defective memory cells. During a test the memory tester writes a bit into each address of an error capture memory (ECM) to indicate whether a correspondingly addressed memory cell of the DUT is defective. The tester also counts of the number of memory cells of each row and column that are defective. After the test the counts are supplied to the host computer. When the host computer is unable to determine how to allocate the spare rows and columns from the counts alone, it requests the tester to process the data in the ECM to determine and supply the host computer with addresses of the defective memory cells.

Abstract: A system for testing a microprocessor having a core execution unit, an internal memory, and a data port may comprise a tester having a data port which is connected to the microprocessor data port. A test vector generator program is transferred from the tester to the internal memory of the microprocessor for testing the microprocessor when the test vector generator program is executed by the core execution unit. The test vector generator program generates test vectors which are also stored in the internal memory, and which may then be executed by the core execution unit.

Abstract: A method of testing embedded cores in an integrated circuit chip having a microprocessor core, a memory core and other functional cores therein. The method includes the steps of; forming a plurality of registers in the integrated circuit chip, testing the microprocessor core by executing its instructions multiple times with pseudo random data and evaluating the results by comparing simulation results, applying a test program to the microprocessor core to generate a memory test pattern by the microprocessor core, applying the memory test pattern to the memory core by the microprocessor core and evaluating the response of the memory core by the microprocessor core, and testing the other functional cores by applying a function specific test pattern thereto by the microprocessor core and evaluating the resultant output signals of the functional cores.

Abstract: An automated test and evaluation sampling system includes a fast pattern memory (130) and a slow pattern memory (137) storing first and second sets of tests states, respectively. Stimulus logic (131) is connected to the fast pattern memory to read the first set of test states at a first rate and stimulate a device under test (133) according to the first set of test states. Compare logic (135) is connected to the slow pattern memory to read the second set of test states at a second rate which is slower on average than the first rate and to compare the second set of test states with a sampled output signal from the device under test.

Abstract: A micro-controller integrated on a single substrate and which includes a read-only information memory for storing firmware, an address controller for performing address control, and an input port for inputting information supplied thereto from a source external to the substrate further incorporates a correcting information storage memory for receiving correcting information input thereto from the source external to the substrate through the input port and storing the correcting information upon an initialization of the micro-controller, wherein the correcting information is indicative of a modification for a defective information part stored in the read-only information storage memory, and a switching circuit for selectively switching the access by the address controller from the defective information part in the read-only information storage memory to the correcting information in the correcting information storage memory.

Abstract: A system and method is provided for verifying the functionality of a multimedia device. In one embodiment, the system includes a device under test and a computer configured to test the device by providing test bitstreams and sequences of user actions to the device. The computer uses bitstream profiles to describe, edit, and generate multimedia bitstreams. The profiles are used to describe in human-intelligible form the values of fields of interest in multimedia bitstreams. Since the fields of interest vary between verification tests, the profile form is subject to change. Bitstream profiles for verification of the multimedia device software may comprise instruction mnemonics and associated operands which specify the navigation instructions in the test bitstreams. A compiler may be provided for converting the profile into bitstream field values, and a combiner may be provided for combining the bitstream field values with an existing bitstream to generate test bitstreams for verification.

Abstract: An event based test system for storing event data in a compressed form to reduce the size of a memory and decompressing the data to produce the events for testing a device under test (DUT). The event based test system includes a clock count memory for storing clock count data of each event wherein the clock count data is formed of one or more data words depending on the value of the integral part data, a vernier data memory for storing vernier data of each event wherein the vernier data memory stores vernier data for two or more events in the same memory location, an address sequencer for generating address data for accessing the clock count memory and the vernier data memory, a decompressor for reproducing the clock count data from the clock count memory and the vernier data from the vernier data memory corresponding to each event.

Abstract: A semiconductor integrated circuit for suppressing power consumption is provided. In the case where an internal signal should be monitored from outside the circuit, an output control circuit outputs the same value as that of the internal signal from each of external terminals. In the case where the internal signal does not need to be monitored, e.g., in the same manner as ordinary user's use, the output control circuit outputs an invariable value from each of the external terminals. Thus, in the case where the internal signal does not need to be monitored, the invariable value is outputted. Consequently, power consumption can be suppressed.

Abstract: A method and apparatus are used to calibrate uncalibrated test equipment using reference devices. For each device, the calibrated test equipment is used to test the device to obtain a reference specification value. One of the devices is then selected, and an electrical identification from the selected device is retrieved. The electrical identification is associated with one of the reference specification values. A channel of the uncalibrated test equipment is used to test the selected device to obtain a measured specification value. The reference specification value associated with the electrical identification is compared with the measured specification value. Based on this comparison, the channel is calibrated.

Abstract: A pattern generator for use in a semiconductor test device provided with a random access memory which has large capacity and runs at high speed and is capable of generating random pattern data having large capacity and running at high speed. Parts of random pattern data previously stored in a sequential pattern memory are transferred to addresses of a random pattern memory which are specified by the difference calculated by an arithmetic circuit between address data outputted from a control circuit and address data outputted from an address generator, and the transferred random pattern data are outputted to a semiconductor to be tested through a selection circuit.

Abstract: An electronic circuit tester (e.g., for testing integrated circuit wafers or packaged integrated circuits) is provided. The tester is preferably based on a relatively inexpensive computer system such as a personal computer and includes at least one high-precision clock circuit that is programmable with respect to frequency and number of clock pulses. The high-precision clock circuit is connectable to the circuit being tested to permit certain timing-critical tests to be performed, even though a large number of other data channels in the tester are controlled by a relatively low speed clock circuit. The tester also includes analog circuitry that can be programmed to provide various analog signals suitable for performing parametric testing on an electronic device under test.

Abstract: An integrated circuit (IC) tester includes a set of digital and analog channels, each of which may be programmed to carry out a sequence of test activities at pins of an IC under test. The channels are interconnected by a trigger bus, and each channel may be programmed to respond to a detected event during a test by transmitting a particular trigger code to every other channel via the trigger bus. Each channel may be also programmed to respond to a particular trigger code arriving on the trigger bus by branching its sequence of test activities. Thus any channel detecting an event during a test can signal all other channels to immediately terminate a current sequence of test activities and branch to another set of test activities. Such a conditional branch capability enables the tester to automatically perform an "if/then" diagnostic test on an IC in which a test result detected at any point during the test determines the future course of the test.

Abstract: A method for fast static compaction in sequential circuits with finite output states by removing subsequences of test vectors from a vector test set. The method has the following steps: (1) relaxing the output states of the sequential circuits; (2) identifying a candidate subsequence of test vectors from the vector test set for removal; (3) temporarily removing the candidate subsequence of test vectors from the vector test set; (4) performing fault simulation on remaining test vectors from the vector test set; (5) examining fault simulation results against a set of removal criteria; (6) permanently removing the temporarily removed candidate subsequence if said set of removal criteria are met; (7) replacing the temporarily removed candidate subsequence if said set of removal criteria are not met; and (8) repeating steps (1) through (7) until all candidate subsequences of test vectors have been identified.

Abstract: An NLTS (non-linear transition shift) correction circuit for hard disk drives improves flexibility in modifying algorithm of the data pattern analysis utilized therein and NLTS correction precision thereof. The NLTS correction circuit of the present invention uses a data pattern analyzer including a CPU and a data pattern analysis program. Selector control signals produced by this analyzer are stored in a selector control signal buffer memory and are output to a selector in synchronization with the output from a data buffer memory. The pattern of data to be recorded can be analyzed while flexibly responding to the fluctuations in the characteristic of the recording medium by modifying the analyzing program. Moreover, the difference in the amount of delay between the delay lines can be calibrated by adding a circuit for calibrating the NLTS correction value, which includes a circuit that converts the duty cycle of the record data signal to voltage value.

Abstract: An apparatus for classifying a device as being a first device type or a second device type, includes a fixture for coupling at least one device to be identified to the system; and a processor coupled to the fixture.

Abstract: A test pattern generation apparatus and method for an SDRAM can easily generate a test pattern for a synchronous dynamic RAM (SDRAM) by having a specific wrap conversion circuit or an address conversion method. The wrap conversion circuit is provided to receive two types of address data from a pattern generator and converts the data through a specified logic circuit information. The test pattern generation method for the SDRAM is carried out by inputting column address data and wrap address data, and by generating output data which has been converted by a predetermined logic equation. The test pattern generation apparatus and method can also include an address inversion scramble for the converted output.

Abstract: A tractable architecture level coverage measure uses information about the coverage measures obtained by the data path blocks, control logic blocks and cache to obtain an overall measure of coverage. This technique is applicable to a variety of different designs using different fabrication processes. Moreover, it allows the use of extended length test vectors, for example, such as those using commercial software applications. Since the coverage measure does not rely on the traditional stuck at model, it is applicable to extended length test vectors that may be used with high performance systems.

Abstract: The present invention provides a method and apparatus for increasing the vector rate of an integrated circuit test system and simplifying the wiring of the tester to the device under test. The tester incorporates circuitry that allows the CPU to remap assignments of tester channels in the CPU address space during testing.

Abstract: A method for testing an IDE controller with random constraints, the method comprising: providing an IDE controller model having a primary and a secondary channel and a host interface; transmitting data patterns to a primary and a secondary device model; receiving the data patterns from the primary and secondary device models; arbitrating the transfer of the data patterns to and from the primary and secondary device models; and determining whether the data patterns returned from the primary and secondary device models match expected values.

Abstract: An apparatus for allowing a RAM array within an SRAM to be tested via scan ATPG is disclosed. A first clocked flip-flop has a data input latched high, a scan-in input latched high, a clock input coupled to a signal source generating a periodic waveform, a scan-enable input coupled to a scan enable signal, and an output. The first flip-flop inverts the data input at the output when the scan enable signal is low, and places the scan-in input signal at the output when the scan enable signal is high. A second clocked flip-flop has a data input coupled to the output of the first flip-flop, a scan-in input latched high, a clock input coupled to the signal source, a scan enable input coupled to the scan enable signal, and an output. The second flip-flop inverts the data input at the output when the scan enable signal is low, and places the scan-in input signal at the output when the scan enable signal is high.

Abstract: A test pattern generator for performing a block write function testing at high speed. The test pattern generator includes a data register which takes in data signal from a data generator by a first write signal from a control signal generator, an address selector which takes in specific bits from an address generated by an address generator, a mask data register file which takes the data signal in an area specified by a second write signal from the control signal generator, a write data register file which takes the data signal in an area specified by a third write signal from the control signal generator, and data formatter which outputs either an output data of the data register or of the data generator based on the above signals.

Abstract: It is to provide a test pattern generator that can easily generate expected value data for arbitrary initial values when testing a memory device having a function of write enable/disable control per bit. The pattern generator includes an XOR controller (131) which generates a control signal in response to instructions from an instruction memory (112), an AND gate which receives an output signal of the XOR controller (131) at its one terminal and an inverted output signal of a data generator B (15) at its other input terminal, and an exclusive OR gate (121) which receives an output of the AND gate (123) at its one input terminal and an output a data generator A (14) at the other input terminal.

Abstract: A method and apparatus are used to calibrate uncelebrated test equipment using reference devices. For each device, the calibrated test equipment is used to test the device to obtain a reference specification value. One of the devices is then selected, and an electrical identification from the selected device is retrieved. The electrical identification is associated with one of the reference specification values. A channel of the uncelebrated test equipment is used to test the selected device to obtain a measured specification value. The reference specification value associated with the electrical identification is compared with the measured specification value. Based on this comparison, the channel is calibrated.

Abstract: An address pattern generator for testing a semiconductor device, particularly, a synchronous DRAM (SDRAM) is disclosed. The address pattern generator can switch an interleave mode and a sequential mode of address generation for a SDRAM during a test process in real time and generates column addresses for the SDRAM by a Y address generation section alone. The address generator includes an address selector that selects and outputs from a lower Y address signal, a Z address signal, and an operation mode control signal, a conversion memory that outputs data based on a conversion table, a multiplexer that selects and outputs an output from the conversion memory and the lower Y address signal in accordance with a burst length control signal.