Abstract: Disclosed herein are synthetic anatomical models, and methods of making and using same, that are designed to enable simulated use testing by medical device companies, medical device designers, individual inventors, or any other entity interested in the performance of medical devices. These models are unique in possessing a level of complexity that allows them to be substituted for either a live animal, an animal cadaver, or a human cadaver in the testing of these devices. These models are further characterized by a similarity of geometry, individual component physical characteristics, and component-to-component interfacial properties with the appropriate target tissue and anatomy.

Abstract: A multi-processor chip has several processor cores that are simultaneously tested in parallel. The processor cores each have identical scan chains that produce identical test results absent defects. Expected test data is scanned from an external tester onto the chip and replicated to each processor core's scan chain. The expected test data is compared to scan chain outputs at each processor core. Any mismatches set a test-fail bit for that processor core. Each processor core has repairable scan chains and a separate critical scan chain. Failures in the critical scan chain in any processor core cause the whole chip to fail. Processor cores are disabled that have failures in their repairable scan chains, allowing the chip to be repairable by using the remaining processor cores. Critical scan chains include logic that drives to other blocks on the chip, while repairable scan chains have logic embedded deep within a processor core.

Abstract: An extractor extracts descriptions unexecuted in the logic simulation according to code coverage information for the circuit description. An examiner examines whether or not there is a possibility of executing the extracted unexecuted descriptions. A prohibited-input-checker generator generates a test pattern. The test pattern is to execute descriptions including unexecuted descriptions that there is a possibility of executing and excluding unexecuted descriptions that there is no possibility of executing as determined by the examiner. The prohibited-input-checker generator also generates a prohibited-input checker to check whether or not an input pattern of a logic simulation to be carried out is equal to an input pattern of the test pattern to execute the unexecuted description if the test bench is regarded as a prohibited input under a specification at a logic simulation using the test pattern to execute the unexecuted description.

Abstract: A memory BIST architecture provides an efficient communication interface between external agents, e.g., external tester and a memory BIST module. The memory BIST architecture reduces diagnostics efforts by dividing the search space and allowing the test and debug to be concentrated on the failing memory. The memory BIST architecture is divided into two levels, a memory BIST sequencer level and a satellite memory BIST module. The memory BIST sequencer level includes a set of registers that provide an interface between external agents attempting to communicate with the MBIST module and the Satellite MBIST module.

Abstract: A method and apparatus is provided which reduces the equipment and time requirements for hard disk drive performance testing during manufacturing. This invention executes self-contained performance testing code that resides within the drive's manufacturing firmware, rather than relying on external testers. The invention involves exercising the drive's enqueue, dequeue, and command execution firmware, as well as the physical process of reading and writing data by simulating the host interface in code. The invention enqueues commands that typify the desired workload, allows a command ordering algorithm to sort the commands for execution, and allows the drive side code to execute the commands just as if an external host interface were attached. The invention is advantageous because the performance testing can be done by only applying power to the drive. The present invention also lends itself to performance tuning that can be done in manufacturing, to reduce drive-to-drive performance variations.

Abstract: The configuration of a faulty line segment in a switch matrix of a programmable logic device is identified using read-back capture. Each original programmable interconnection point (“PIP”) in the line segment is tested by generating routes from a first logic port through the original line segment and PIP, through all PIPs, adjacent to the original PIP to the opposite logic port. Routes through all PIPs adjacent to the PIPs in the line segment from the first logic port to the second logic port, and from the second logic port to the first logic port, are tested to isolate the fault in the line segment.

Abstract: A test component and method of operation thereof are provided, the test component being arranged in a test environment to issue a test sequence over a bus to a device under test. A configuration file is provided to specify the behaviour of the test component, the configuration file comprising a plurality of regions with each region specifying attributes for use in determining the test sequence. The method of the present invention comprises the steps of: (a) when a test sequence is required to be issued, causing the test component to select, based on predetermined criteria, one of a number of regions provided by the configuration file; and (b) using the constraint attributes for that selected region to generate the test sequence to be issued on to the bus.

Abstract: Cross-monitoring sensor system and method in which a plurality of sensors each having a sensing element, circuitry for processing signals from the sensing element, an output interface for delivering processed signals, and an auxiliary input to which signals from another device can be input for processing and delivery by the output interface. Signals from each of the sensors are applied to the auxiliary input of another one of the sensors, and signals from the output interfaces of the sensors are compared to verify integrity of the system.

Abstract: A system and method for evaluating a multiprocessor system having multiple processors coupled via a system bus is disclosed. A test vector is executed on a processor under test. While the test vector is being executed, an instruction that causes a transaction to be issued on the system bus is executed on another processor, thereby stressing the first processor.

Abstract: There is provided a test apparatus that tests an electronic device. The test apparatus includes: a plurality of test modules operable to supply and receive signals to/from the electronic device; a plurality of return circuits operable to receive fail timing signals indicating timing at which a fail occurs on output patterns output from the electronic device, the return circuits being provided corresponding to the plurality of test modules; a plurality of summarizing units operable to receive the fail timing signals output from the plurality of return circuits and compute logical sum of one or more fail timing signals among the plurality of fail timing signals to output one bit signal; and a plurality of distributing units operable to distribute the computed results of corresponding ones of the summarizing units to the plurality of test modules, the distributing units being provided corresponding to the plurality of summarizing units.

Abstract: A circuit for parametric testing of an integrated circuit includes an integrated circuit having a plurality of input buffers and a plurality of XOR gates. The plurality of XOR gates have a first input that is connected to an output of one of the input buffers and having a second input that is connected to an output of a preceding XOR gate to form an XOR logic tree.

Abstract: Methods and apparatuses are provided that allow kernel mode data traffic and user mode data traffic to share a common network communication port. One apparatus includes user mode logic, kernel mode logic, and kernel mode to user mode interface logic. The interface logic is configured to receive data packets and selectively distribute the data packet to either the user mode or kernel mode logic. The interface logic includes “virtual” bridge logic and “virtual” miniport logic. The bridge logic determines if a received data packet is a user mode or kernel mode data packet. If it is a kernel mode data packet, then the bridge logic provides the data packet to the kernel mode logic. If it is a user mode data packet, then the bridge logic stores the data packet in memory for subsequent use by the user mode logic.

Abstract: Methods and apparatuses are provided that allow kernel mode data traffic and user mode data traffic to share a common network communication port. One apparatus includes user mode logic, kernel mode logic, and kernel mode to user mode interface logic. The interface logic is configured to receive data packets and selectively distribute the data packet to either the user mode or kernel mode logic. The interface logic includes “virtual” bridge logic and “virtual” miniport logic. The bridge logic determines if a received data packet is a user mode or kernel mode data packet. If it is a kernel mode data packet, then the bridge logic provides the data packet to the kernel mode logic. If it is a user mode data packet, then the bridge logic stores the data packet in memory for subsequent use by the user mode logic.

Abstract: Described are methods for implementing customer designs in programmable logic devices (PLDs). The defect tolerance of these methods makes them particularly useful with the adoption of “nanotechnology” and molecular-scale technology, or “molectronics.” Test methods identify alternative physical interconnect resources for each net required in the user design and, as need, reroute certain signal paths using the alternative resources. The test methods additionally limit testing to required resources so devices are not rejected as a result of testing performed on unused resources. The tests limit functional testing of used resources to those functions required in the user designs.

Abstract: An integrated circuit device receives a sequence of commands and enables a test mode of the integrated circuit device in response to the command sequence when all of the commands of the sequence are correct. The integrated circuit device disables the test mode upon receiving an incorrect command of the sequence.

Abstract: A digital logic test method for systematically testing a pipeline-structured integrated circuit chip is disclosed. The method includes the steps of: providing an integrated circuit chip capable of executing a plurality of instructions during a period of time, each of the instructions being executed according to a plurality of sequentially ordered operation segments, sorting the instructions, and designing a plurality of test patterns to test the integrated circuit according to the sorting result and STAGE test segments corresponding to the STAGE operation segments.

Abstract: A method for simulating a modular test system is disclosed. The method includes providing a controller, where the controller controls at least one vendor module and its corresponding device under test (DUT) model, creating a simulation framework for establishing standard interfaces between the at least one vendor module and its corresponding DUT model, configuring the simulation framework, and simulating the modular test system using the simulation framework.

Abstract: In one embodiment, a request to perform a calibration process for automated test equipment (ATE) is received. The request is associated with a calibration parameter set. After receiving the request, one or more signatures for calibration data corresponding to the calibration parameter set are derived, and a determination is made as to whether calibration data corresponding to the signature(s) has already been generated. Thereafter, an incremental set of calibration data is generated, with the generated calibration data i) corresponding to the signature(s), but ii) not having already been generated. In another embodiment, a request to perform a calibration process for ATE is received, and the request is associated with specified test setups. An incremental set of calibration data corresponding to the specified test setups is then generated.

Abstract: An integrated semiconductor memory operates in synchronization with a clock signal in a normal operating state and is switched from the normal operating state to a test operating state by applying a combination of control signals. During a first test cycle, selection transistors for memory cells are turned on by asynchronously actuating the semiconductor memory using a state change in a control signal. In a second test cycle, the memory content of at least one of the previously activated memory cells is read by synchronously actuating the semiconductor memory using a second signal combination of control signals. By shifting the timing of a signal edge which prompts the state change in the first test cycle close to the time at which the second signal combination is applied in the second test cycle, it is possible to test short reading times which are within one period of the clock signal.

Abstract: An integrated circuit, among other embodiments, includes an output circuit to provide a differential signal on first and second contacts during a first mode of operation, such as in a read or write mode of operation, and a single-ended signal on the first contact during a second mode of operation, such as a test mode of operation. A first variable resistor, responsive to a first control signal, is coupled to a first voltage source and the first contact. A second variable resistor, responsive to a second control signal, is coupled to a second voltage source and the second contact. A first transistor has a first electrode coupled to the first contact, a second electrode coupled to the current source and a gate to receive a first input signal. A second transistor has a first electrode coupled to the second contact, a second electrode coupled to the current source and a gate to receive a second input signal.

Abstract: A computerized method and system for testing a function of an information-processing system. This includes providing an architecture having a set of test commands, the test commands including a set of one or more stimulation commands and a set of one or more result-testing commands, and defining a set of test verbs out of combinations of the test commands. This allows the test programmer to define an overall test program that uses the test verbs in writing a test program that specifies an overall function that will extensively test a system-under-test. The methods further includes executing a program that includes a plurality of test verb instructions and outputting a result of the program. In some embodiments, the present invention provides a computer-readable media that includes instructions coded thereon that when executed on a suitably programmed computer executes one or more of the above methods.

Abstract: Devices and methods are provided for testing various types of smart cards including contact, contactless, and hybrid type (contact/contactless) smart cards. A test device includes a logic tester, a contactless interface unit, and a contact interface unit. The logic tester generates a test pattern that is transmitted to a smart card to test the smart card and compares a received response pattern with a response pattern to test a status of the smart card. The contactless interface unit enables a contactless test mode of operation and the contact interface unit enables a contact test mode of operation.

Abstract: An automatic test system, such as might be used to test semiconductor devices as part of their manufacture. The test system uses instruments to generate and measure test signals. The automatic test system has a hardware and software architecture that allows instruments to be added to the test system after it is manufactured. The software is segregated into instrument specific and instrument independent software. Predefined interfaces to the software components allow for easy integration of instruments into the test system and also easy reuse of the software as the physical implementation of the test system or the instruments changes from tester to tester in a product family.

Abstract: An apparatus and method for computing event timing for high speed event based test system. The event processing apparatus includes an event memory for storing event data of each event where the event data includes timing data for each event which is formed with an integer multiple of a clock period and a fraction of the clock period, an event summing logic for accumulating the timing data and producing the accumulated timing data in a parallel form, and an event generator for generating events specified by the event data based on the accumulated timing data received in the parallel form from the event summing logic. The events in the event data are specified as groups of events where each group of event is configured by one base event and at least one companion event.

Abstract: A programmable logic device (PLD) has the ability to test the configuration memory either independently or during configuration. The PLD may include a selector for selecting a particular column or row of the configuration memory array, and an input data storage device for storing configuration data required to be stored in the selected column or row, or test data for testing the selected column or row. The PLD may also include an output data storage device for storing the output from the selected column or row, and test logic that provides control signals for verifying the correct operation of the data lines of the configuration memory array without disturbing the data stored in the memory array.

Abstract: A method for performing testing of a simulated direct access storage device in a testing simulation environment is disclosed. The method provides a software representation of a plurality of hardware components within the simulated direct access storage device. The method also uses a control program module within the testing simulation environment, wherein the control program module interacts with the software representation of the plurality of hardware components, and a testing program for interacting with the control program module and the software representation of the plurality of hardware components. In response to detection of an occurrence of a pre-selected event within the simulated direct access storage device, one or more codes are sent from the testing program to the software representation of the plurality of hardware components and whether or not a response by the control program module to the one or more codes is correct is determined.

Abstract: A system for testing electronic device performance includes a test device and at least one target device coupled to the test. The test device determines when at least one test command is incompatible with the at least one target device and modifies the at least one incompatible test command such that the at least one incompatible test command is compatible with the at least one target device. The test device presents the at least one compatible test command to the at least one target device and determines a response of the at least one target device to the respective at least one compatible test command.

Abstract: A semiconductor device has a least one logic circuit and at least one memory macro cell having a plurality of memory cell array blocks each composed of a plurality of memory cells. Addresses for designating the memory cell array blocks in test are selected among external addresses by a switching signal. The semiconductor device may have a plurality of memory macro calls having a plurality of memory cell array blocks each composed of a plurality of memory cells. The memory macro cells are switched in configuration as having the same length of rows or columns between the memory macro cells in test. The configuration is different from a configuration of row and column for a regular operation.

Abstract: An X-Tree test apparatus for testing combinatorial logic circuits in a multiplexed digital system. The apparatus includes a plurality of contacts for electrical connection with pins on a device under test. A first driver drives a logic one signal, and a second driver drives a logic zero signal, both of which are used for testing the device. Multiplexing circuitry selectively connects the first driver and the second driver with each of the plurality of contacts and device pins. A receiver, connected with the device under test, measures a response from the logic circuit under test to the logic one and zero signals to determine if it functions as intended.

Abstract: A method for determining whether a physical layer device under test is defective may include establishing a closed communication path between a verified physical layer device and the physical layer device under test via an optical interface of the verified physical layer device and an optical interface of the physical layer device under test. Alternately, the electrical interface may also be used for testing. A packet generator may transmit test packets over the established closed communication path and at least a portion of the test packets from the physical layer device under test may be received by the verified physical layer device. Subsequently, the verified physical layer device may compare at least a portion of the received test packets with at least a portion of the generated test packets in order to determine whether the physical layer device is defective or operational.

Abstract: The method and the device generate digital signal patterns. Signal patterns or signal pattern groups are stored in a very small buffer register. The position of a following signal pattern or following signal pattern group is also stored in the form of a branch address, together with each signal pattern or each signal pattern group. A simple control logic circuit receives a control signal and determines whether the content of the currently addressed group is output continuously or the following group given by the branch address stored in the register is output after the currently selected group has been completely output. The novel method and device can advantageously be used for testing semiconductor memories and implemented in a cost-effective semiconductor circuit which is remote from a conventional test system.

Abstract: Apparatus and methods are described for a background microcontroller debugger. A method to debug a microcontroller includes sending a three level signal from a debug module, receiving the three level signal at a single pin on an MCU, sending a second three level signal from the single pin on the MCU, and receiving the second three level signal at the debug module. An apparatus to debug a microcontroller includes a tri-statable pad driver to transmit a three level signal, a reference voltage divider coupled to the tri-statable pad diver, a plurality of voltage comparators to receive the three level signal, a resistive voltage divider to maintain thresholds for the plurality of voltage comparators, and a plurality of logic elements coupled to the plurality of voltage comparators to receive the three level signal.

Abstract: An integrated circuit includes a trace analyzer to sample, process and store data carried along internal or external data path of the circuit. The trace analyzer may include a multiplexer, a sampler, a formatter and a memory controller. The trace analyzer samples data on a predetermined basis, processes it and caused the processed data to be stored in a memory.

Abstract: The problem of sequentially “squeezing” small fields of data in a larger data path in and out of a memory device can be solved in an algorithmically driven memory tester by defining sub-vectors to represent data in the small field, where a sequence of sub-vectors represents the data that would be represented by a full sized vector if such a full sized vector could be applied to the DUT. A programming construct in the programming language of the algorithmically driven memory tester allows sub-vectors to be defined, as well as an arbitrary mapping that each is to have. The arbitrary mapping is not static, but changes dynamically as different sub-vectors are encountered. Arbitrary dynamic mappings change as sub-vectors are processed, and may include the notion that, during the activity for a sub-vector, this (or these) bit(s) of a vector do not (presently) map to any pin at all of the DUT.

Abstract: The invention comprises, in various embodiments, a method for monitoring an internal test on a remote computer. The method includes reading a line from the remote computer with a processing unit. The line is capable of sending at least one result signal for the test. The method includes sending a fail signal from the processing unit to a reporting device when none of the new result signals are read during any time period of a preselected length.

Abstract: A library to be used in an ASIC design system includes information to be used for verification of test structures. The library includes information regarding the ability to combine test pins for verification of the test structure and information regarding the sharing of ports for verification of the test structure. A user of the ASIC design system can include custom test structures in the library for verification.

Abstract: In a method of measuring group delay (Tgd) of a device under test, an analog input signal having a predetermined period (T) is provided to the device under test so as to obtain a delayed output signal from the device under test. A phase difference is detected between first and second digital signals converted from the analog input signal and the delayed output signal, respectively. A current (I) corresponding to the phase difference flows through a circuit having a predetermined resistance (R) so as to result in a potential difference (?V). As such, the group delay (Tgd) of the device under test is determined as a function of the predetermined period (T), the current (I), the predetermined resistance (R), and the potential difference (?V). An apparatus for measuring the group delay (Tgd) of the device under test is also disclosed.

Abstract: An apparatus generally comprising a circuit and an interface device is disclosed. The circuit may be configured to (i) generate a plurality of test signals to simultaneously stimulate a device and a model of the device during a test and (ii) receive a plurality of model signals generated by the model in response to the test signals. The interface device may be configured to receive a plurality of device signals generated by the device in response the test signals.

Abstract: A method and device for testing multi-channel transceivers in an integrated circuit is provided. More specifically, the present invention relates to a method and device for implementing a built-in self-test for multi-channel transceivers. An exemplary embodiment of the present invention includes a test pattern generator, a multiplexer, a demultiplexer, and a test result evaluator. The test pattern generator generates a test pattern which is fed into each of the input channels of the multiplexer. The multiplexer multiplexes the data from all its input channels and then relays the data to the demultiplexer. The test result evaluator then individually checks the data at each of the output channels of the demultiplexer to determine whether the data received at each output channel is the same as the test pattern. In order to facilitate the checking process, signature analysis is utilized.

Abstract: The present invention is an apparatus for multi-level loopback test in a community network system and method therefor, in which a loopback test device is installed between an Ethernet switch in a community and a central office so that the loopback test device can be utilized by network management system in central office to perform a three-level loopback test on the community network system to easily obtain the information of whether there is a fault between central office and loopback test device, whether the connection of Ethernet switch is good, and whether loopback test device operates normally.

Abstract: Some embodiments of the invention enable debugging functionality for memory devices residing on a memory module that are buffered from the memory bus by a buffer chip. Some embodiments map connector signals from a tester coupled to the high speed interface between the buffer chip and the memory bus to an interface between the buffer chip and the memory devices. During test mode, some embodiments bypass the normal operational circuitry of the buffer chip and provide a direct connection to the memory devices. Other embodiments use the existing architecture of the buffer chip to convert high speed pins into low speed pins and map them to pins that are connected to the memory devices. Other embodiments are described in the claims.

Abstract: A method and apparatus for testing a device using transition timestamp are used to evaluate output signals from the device. The method comprises the steps of performing timing tests on a signal from the device; and independently carrying out bit-level tests on a signal from the device. The independent timing tests and bit-level tests can be performed in parallel. The bit-level tests and apparatus comprise iteratively measuring a coarse timestamp for a transition in the signal and comparing the measured coarse timestamp to an expected timestamp to determine whether the device meets specifications. Whether the device meets specifications depends on whether, during the comparison step, the presence of a bit-level fault is detected. The apparatus and method may comprise Skew Fault detection, Bit Fault detection, No Coverage Warning detection and/or Drift Fault detection. An automatic testing system for testing devices comprises subsystems that incorporate the apparatus and method.

Abstract: According to some embodiments, at speed application of test patterns associated with a wide tester interface are enabled on a low pin count tester. For example, an integrated circuit might include a processor core to exchange information via input and output paths (e.g., the paths might be associated with a bus external to the integrated circuit). The integrated circuit might also include a cache structure to store test information and a sequencer to transfer the test information from the cache structure. According to some embodiments, a multiplexer receives sets of signals from (i) at least a portion of the bus and (ii) the sequencer. Moreover, the multiplexer might provide one of the received sets of signals to the processor core via the input paths.

Abstract: A deskew circuit includes, for clock and every bit of data, a variable delay circuit between a receiver that receives data and a flip-flop that first latches the data, in which a detecting pattern to detect a stable region for receiving data is repeatedly sent before implementing a data transfer, a delay value with which the starting edge and ending edge of the data match the rising edge of the clock is found for the variable delay circuit, and a delay value with which the transfer data can be received in a stable manner is set based on the delay value of the variable delay circuit.

Abstract: A scan cell circuit for use in an integrated circuit chip is disclosed. The scan cell circuit includes a multiplexer receiving a first signal, a second signal and a selection signal, and outputting one of the first signal and the second signal in response to the selection signal, and a host circuit electrically connected to the multiplexer, receiving and processing an output of the multiplexer, and proceeding an optional output from a first output end and/or a second output end. When the multiplexer selects the second signal to be outputted in response to a specific state of the selection signal, the first signal output end is fixed at a constant level according to the specific state of the selection signal.

Abstract: A list of waveforms is received (the list being one that is to be driven to or received from a pin of a device under test, and each waveform in the list being associated with a weight). For each of at least two waveforms in the list, a number of test sample points lost by masking the waveform with a particular parent waveform in a child-parent waveform map is calculated. The number of lost test sample points is determined by 1) a difference in the number of test sample points in the waveform and the number of test sample points in the particular parent waveform, and 2) the weight associated with the waveform. In response to the calculations, a waveform masking is implemented such that the implemented waveform masking results in fewer lost test sample points than another waveform masking.

Abstract: An N2 algorithm for optimizing correlated events, applicable to the optimization of the detection of redundant tests and inefficient tests (RIT's), is disclosed. This algorithm represents a set of N tests with L defects as N L-dimensional correlation vectors. The N2 algorithm optimizes in terms of the minimum set of vectors, and the set of vectors that take the minimum time to detect the L defects. The minimum set optimization determines a set of vectors (tests) that contains the minimum number of vectors (tests) by analyzing the correlation among the N vectors. This minimum set optimization provides the minimum test set containing all defects in an algorithm that takes O(N2) operations. The minimum time optimization determines a sequence of vectors (tests) that will detect the defects in a minimum amount of time.

Abstract: A method for analyzing test data for objects on an IC or a wafer is provided. The test data is linked to available layout information about the object under test. Certain objects are selected based on the test data. A representation of the selected objects is placed on a map of the IC or on a map of the wafer. The representation should correspond to the physical location of the object on the IC or wafer. Preferably, the representation comprises one or more polygons that enclose all devices that make up the object.

Abstract: A method for testing a network switch chip having an expansion port configured for transferring data according to a prescribed expansion port protocol. The method includes outputting the expansion port frame data from the expansion port according to the prescribed expansion port protocol, converting the expansion port frame data from the prescribed expansion port protocol to a prescribed network protocol such as IEEE 802.3-based Media Independent Interface (MII) protocol, and outputting the converted data according to the prescribed MII protocol to a test device having an MII interface configured for receiving the data according to the prescribed MII protocol. The conversion of the data from the prescribed expansion port protocol to the prescribed MII protocol enables the use of the test device for validation of the expansion port, without the necessity of another network switch chip.

Abstract: A system and method for testing a group of related products or devices. According to one embodiment, the user may first manually create a base test sequence, and child test sequences may then be created based on the base test sequence. The user may include various steps in the base test sequence, such that the base test sequence includes steps that need to be common to most or all of the child test sequences. The user may also configure parameters or properties for each step in the base test sequence, such that the parameter configuration is what is required for most or all of the child test sequences. Initial child test sequences may then be automatically created as instances of the base test sequence. The user may then manually edit the instances of the base test sequence to produce the desired child test sequences, such that each child test sequence is configured to appropriately test a particular product to which the child test sequence corresponds.