Clock Or Synchronization Patents (Class 714/744)
  • Patent number: 10320385
    Abstract: Disclosed is a variable coding method for realizing chip reuse, comprising the following steps: using at least two identical integrated circuit chips, wherein each integrated circuit chip executes different control logic truth tables according to different gating signals; introducing at least one logical control signal as a gating signal; and controlling the logical control signal, so that each integrated circuit chip respectively executes a corresponding control logic truth table. Also disclosed is a communication terminal using the variable coding method for realizing chip reuse. Two or more completely identical integrated circuit chips can be used to realize different logical control functions, thereby simplifying the type of a chip for realizing a system function, and greatly reducing the development costs of an integrated circuit system and the management complexity of a mass production supply chain.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: June 11, 2019
    Assignee: Vanchip (Tianjin) Technology Co., Ltd.
    Inventor: Sheng Lin
  • Patent number: 10236045
    Abstract: A clock pattern generating method of a semiconductor memory device is provided. The method includes generating the same clock pattern through a plurality of detection clock output pins when an output selection control signal is in a first state and generating clock patterns different from each other through the plurality of detection clock output pins when the output selection control signal is in a second state different from the first state.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: March 19, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Su Yeon Doo, Seungjun Bae, Sihong Kim, Hosung Song
  • Patent number: 10073760
    Abstract: In a general aspect, a tracer is configured to instrument an application by injecting at least one interrupt instruction at a function entry point in a memory image of the application such that executable code of the application is not modified. The tracer is configured to collect information relating to execution of the application when the inserted at least one interrupt instruction is triggered during runtime of the application including tracing at least one operating system function used by the application at the function entry point. The tracer is configured to create an application signature based on the collected information. The application signature provides information about at least one system object accessed by the at least one operating system function.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: September 11, 2018
    Assignee: Indentify Software Ltd. (IL)
    Inventors: Valery Golender, Ido Ben Moshe, Shlomo Wygodny
  • Patent number: 9838165
    Abstract: A method of testing a data transmission and reception system comprises sending a test signal from a transmitter (14) of the system to a receiver (12) of the system, and analyzing the received signal. A duty cycle relationship is varied between the test signal and the timing signal used by the receiver of the system, and the effect of the duty cycle variation is analyzed. Varying the duty cycle relationship provides duty cycle distortion (DCD), and this can be considered as a form of embedded jitter insertion. This type of jitter can be measured relatively easily.
    Type: Grant
    Filed: July 12, 2006
    Date of Patent: December 5, 2017
    Assignee: NXP B.V.
    Inventors: Rodger F. Schuttert, Geertjan Joordens, Willem F. Slendebroek
  • Patent number: 9618579
    Abstract: In certain embodiments, an integrated circuit has scan-test circuitry that performs scan testing on circuitry under scan test (CUST) within the IC, where the scan-test circuitry is susceptible to a defect. In order to enable the defect to be corrected after it occurs, the scan-test circuitry includes a set of programmable circuitry connected to provide a signal to other circuitry (e.g., a scan chain) within the scan-test circuitry, where the set of programmable circuitry includes one or more configurable memory cells connected to control the programming of the set of programmable circuitry. The memory cell(s) can be configured to program the set of programmable circuitry to enable the scan testing to be performed without modification. The memory cell(s) can also be configured to program the set of programmable circuitry to modify the scan testing to correct the defect in the scan-test circuitry.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: April 11, 2017
    Assignee: Lattice Semiconductor Corporation
    Inventor: Kanad Chakraborty
  • Patent number: 9406360
    Abstract: A semiconductor device may include a first pad suitable for inputting a dock, a plurality of second pads suitable for inputting data through a plurality of first data paths, a third pad suitable for inputting a first strobe signal through a first strobe signal path, a data latch unit suitable for latching the data inputted through the first data paths in response to the first strobe signal inputted through the first strobe signal path, and a calibration control unit suitable for calibrating delay values of the plurality of first data paths and the first strobe signal path in a first calibration mode such that a plurality of first test signals passing through the respective first data paths and a second test signal passing through the first strobe path are in phase with the clock inputted from the first pad.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: August 2, 2016
    Assignee: SK Hynix Inc.
    Inventor: Choung-Ki Song
  • Patent number: 9367432
    Abstract: The present subject matter relates a testing system for an application. The system includes a test data generation module to generate test data for a program code. The test data generation module in turn includes a relational expression creation module that determines a relational expression corresponding to a set of parameters of the program code based on a rule indicating a format of a valid test data for the parameters. A boundary recognition module identifies a set of boundary values of the parameters based on the relational expression. Further, a solver module then generates valid test data and invalid test data for the parameters based on the boundary values.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: June 14, 2016
    Assignee: Tata Consultancy Services Limited
    Inventors: Moksha Suryakant Jivane, Nandita Babu, Sarang Kamlesh Barpatre, Jevanthi Priva C. K., Sushant Vale, Nikhil Patwardhan
  • Patent number: 9194916
    Abstract: The present disclosure generally provides for a method of prioritizing clock domains for testing an integrated circuit (IC) design. The method can include: assigning each of a plurality of multi-tested clock domains (MTCDs) and a plurality of test experiments (TEs) to one of a plurality of speed priority groups (SPGs), wherein the assigning includes: creating a new SPG having a priority value of n+1, wherein n represents the number of previously created SPGs; assigning a first MTCD corresponding to at least two of the plurality of TEs, the first MTCD not being previously assigned to an SPG, to the new SPG; and assigning each TE corresponding to the first MTCD, each of the assigned TEs not being previously assigned to an SPG, to the new SPG; and performing each of the plurality of TEs on the IC design in order from lowest priority value to highest priority value.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: November 24, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Douglas E. Sprague, Philip S. Stevens
  • Patent number: 9030339
    Abstract: A transmitting device includes a parallel data generation unit and a transmitting unit. The parallel data generation unit generates first serial data and second serial data from a data packet, converts the first serial data and second serial data respectively into first parallel data and second parallel data, transmits the first parallel data and second parallel data respectively through first and second parallel transmission paths, and performs the transmission of the first parallel data and the transmission of the second parallel data in parallel. The transmitting unit receives the first parallel data and second parallel data respectively through the first and second parallel transmission paths, re-converts the first parallel data and second parallel data respectively into the first serial data and second serial data, and transmits the first serial data and second serial data to a receiving device respectively through first and second serial transmission paths.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: May 12, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yusuke Fujita
  • Publication number: 20150128003
    Abstract: A test technique that may be implemented in an automated test system for testing semiconductor devices. The test technique may enable the fast detection of a signal transition, such as an edge, within a waveform and the timing of that event. Circuitry within a digital instrument that can be quickly and flexibly programmed may, at least in part, implement the test technique. That circuitry may be simply programmed with testing parameters, such that application of the technique may lead to faster test development and faster times. In operation, that circuitry receives parameters specifying parameters of a window over a waveform in which samples of the waveform will be taken to detect the signal transition. The circuitry may convert these parameters into control signals for other components in the test system, such as an edge generator or pin electronics, to take a programmed number of samples at desired times.
    Type: Application
    Filed: November 6, 2013
    Publication date: May 7, 2015
    Applicant: Teradyne, Inc.
    Inventors: Ronald A. Sartschev, Edward J. Seng, Marc Reuben Hutner
  • Patent number: 8976776
    Abstract: In operation, a transmitting device selects a synchronization pattern associated with the desired timeslot that is at least mutually exclusive from synchronization patterns associated with other timeslots on the same frequency in the system. Once selected, the transmitting device transmits a burst embedding the synchronization pattern that was selected, where appropriate. If the receiving device detects the synchronization pattern, it immediately synchronizes with the timeslot with confidence that it is synchronizing to the desired timeslot by using sets of synchronization patterns associated with the desired timeslot that are at least mutually exclusive from synchronization patterns associated with the other timeslots on the same frequency.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: March 10, 2015
    Assignee: Motorola Solutions, Inc.
    Inventors: David G. Wiatrowski, Dipendra M. Chowdhary, Thomas B. Bohn
  • Patent number: 8972811
    Abstract: A panel driving circuit that produces a panel test pattern and a method of testing a panel are provided. The driving circuit includes a pattern generation unit and a selection unit. The pattern generation unit responds to a system clock and produces pattern test data and pattern test signals. The selection unit responds to a test signal and selects and outputs either (a) the pattern test data and the pattern test signals that are outputted from the pattern generation unit, or (b) the pattern test data and pattern test signals that are directly applied from the outside. The driving circuit and the method of the panel test generates the panel test data, the horizontal synchronizing signal, the vertical synchronizing signal, and the data activating signal within the driving circuit using a system clock so that the testing of the panel can be carried out without using a separate test device.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: March 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-Sik Kang, Jae-Goo Lee
  • Patent number: 8959411
    Abstract: A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: February 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinichi Kanno, Hironori Uchikawa
  • Patent number: 8954813
    Abstract: According to one embodiment, two memory systems each including a memory and a controller are connected via a communication line. The controller includes a testing unit that performs a self-test process on the memory, a communication unit that communicates with the counterpart controller, and a status output unit. The communication unit performs a startup synchronization process which is performed before the self-test process and a termination synchronization process which is performed after the self-test process. The testing unit obtains a comprehensive test result from the test results of the two memory systems, and the status output unit of one memory system outputs the comprehensive test result.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: February 10, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Ohba, Nobuhiro Ono
  • Publication number: 20150012791
    Abstract: A parallel test device and method are disclosed, which relates to a technology for performing a multi-bit parallel test by compressing data. The parallel test device includes: a pad unit through which data input/output (I/O) operations are achieved; a plurality of input buffers configured to activate write data received from the pad unit in response to a buffer enable signal, and output the write data to a global input/output (GIO) line; a plurality of output drivers configured to activate read data received from the global I/O (GIO) line in response to a strobe delay signal, and output the read data to the pad unit; and a test controller configured to activate the buffer enable signal and the strobe delay signal during a test mode in a manner that the read data received from the plurality of output drivers is applied to the plurality of input buffers such that the read data is operated as the write data.
    Type: Application
    Filed: November 8, 2013
    Publication date: January 8, 2015
    Applicant: SK hynix Inc.
    Inventor: Min Chang KIM
  • Patent number: 8918689
    Abstract: An integrated circuit is configured to receive a test clock input and includes circuitry configured to generate test clocks from the test clock input, and test circuitry configured to use the test clocks in a test mode.
    Type: Grant
    Filed: August 30, 2010
    Date of Patent: December 23, 2014
    Assignee: STMicroelectronics International N.V.
    Inventors: Anirudha Kulkarni, Jasvir Singh
  • Patent number: 8892974
    Abstract: A method that dynamically adjusts link control parameters of a communications network. The communications network includes a transmitter coupled through a first data link to a receiver. The transmitter and receiver each have at least one associated link control parameter that affects the operation of that component. According to one method, data signals are transmitted over the first data link and the transmitted data signals are captured. The values of the captured data signals are compared to expected values for those signals, and the values of the link control parameters are adjusted to successfully capture the transmitted digital signals.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: November 18, 2014
    Assignee: Round Rock Research, LLC
    Inventors: Terry R. Lee, Joseph M. Jeddeloh
  • Patent number: 8887019
    Abstract: A method and system for providing on-product clocks for domains compatible with compression is disclosed. According to one embodiment, a base signal received from automated test equipment has a frequency for testing a plurality of clock domains and programming instruction for first and second clock domains of a plurality of clock domains. First and second clock signals are generated from the base clock signal based on the programming instruction. A first delay for the first clock signal and a second delay for the second clock signal are determined from the programming instruction. A test sequence is provided to test a first clock domain and a second clock domain. The test sequence comprises the first clock signal delayed by the first delay and the second clock signal delayed by the second delay. The first clock drives the first clock domain and the second clock derives the second clock domain.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: November 11, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Karishna Chakravadhanula, Brion Keller, Ramana Malneedi
  • Patent number: 8843794
    Abstract: Techniques and mechanisms for evaluating I/O buffer circuits. In an embodiment, test rounds are performed for a device including the I/O buffer circuits, each of the test rounds comprising a respective loop-back test for each of the I/O buffer circuits. Each of the test rounds corresponds to a different respective delay between a transmit clock signal and a receive clock signal. In another embodiment, a first test round indicates a failure condition for at least one I/O buffer circuit and a second test round indicates the failure condition for each of the I/O buffer circuits. Evaluation of the I/O buffer circuits determines whether the device satisfies a test condition, where the determining is based on a difference between the delay corresponding to the first test round and the delay corresponding to the second test round.
    Type: Grant
    Filed: September 24, 2012
    Date of Patent: September 23, 2014
    Assignee: Intel Corporation
    Inventors: Christopher J. Nelson, Tak M. Mak, David J. Zimmerman, Pete D. Vogt
  • Patent number: 8819511
    Abstract: Provided is an apparatus configured for testing a logic device. The apparatus includes a testing mechanism configured to output test patterns representative of logical structures within the logic device and a testable logic device having (i) input ports coupled to output ports of the automated testing mechanism and (ii) output ports coupled to input ports of the automated testing mechanism. The apparatus also includes a fusing mechanism configured to compensate for defects within the logic device responsive to a segregation of the type of defects identified.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: August 26, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Angel Socarras
  • Patent number: 8803714
    Abstract: A transmitting device includes a parallel data generation unit and a transmitting unit. The parallel data generation unit generates first serial data and second serial data from a data packet, converts the first serial data and second serial data respectively into first parallel data and second parallel data, transmits the first parallel data and second parallel data respectively through first and second parallel transmission paths, and performs the transmission of the first parallel data and the transmission of the second parallel data in parallel. The transmitting unit receives the first parallel data and second parallel data respectively through the first and second parallel transmission paths, re-converts the first parallel data and second parallel data respectively into the first serial data and second serial data, and transmits the first serial data and second serial data to a receiving device respectively through first and second serial transmission paths.
    Type: Grant
    Filed: April 3, 2013
    Date of Patent: August 12, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yusuke Fujita
  • Patent number: 8775888
    Abstract: Methods and structure for correlating multiple sets of test output signals in time are provided. The structure includes an integrated circuit comprising a block of circuitry that generates internal operational signals. The circuit also comprises a test multiplexer (MUX) hierarchy that selects subsets of the internal signals and applies the subsets to a testing element. A clock generator generates a clock signal for the selected signals. A test logic timer receives the clock signal and increments a counter value, and applies the counter value to the testing element. An event detector resets the counter value upon detection of an event, such that a first subset of the internal signals acquired from the test MUX hierarchy acquired responsive to detection of a first instance of the event may be correlated in time with a second subset of the internal signals acquired responsive to detection of a second instance of the event.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: July 8, 2014
    Assignee: LSI Corporation
    Inventors: Eugene Saghi, Jeffrey K. Whitt, Joshua P. Sinykin
  • Patent number: 8769363
    Abstract: Provided is a test apparatus comprising a plurality of pattern output sections. In a high-speed mode, each pattern output section outputs, as pattern data corresponding to at least one of a plurality of partial periods, the pattern data corresponding to an input pattern input to the pattern output section and the pattern data corresponding to input patterns input to other pattern output sections.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: July 1, 2014
    Assignee: Advantest Corporation
    Inventor: Toshiyuki Negishi
  • Patent number: 8754656
    Abstract: A high speed test circuit receives a tester clock from a tester and it conducts a test on a circuit under test. The high speed test circuit generates a high frequency clock according to the tester clock, so it is capable of operating in two frequencies. The high speed test circuit tests the circuit under test according to the high frequency clock, and it performs a low speed operation according to a low frequency clock, which is for example the tester clock.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: June 17, 2014
    Assignee: Piecemakers Technology, Incorporation
    Inventors: Tah-Kang Ting, Gyh-Bin Wang, Ming-Hung Wang, Chun-Peng Wu, Li-Chin Tien
  • Patent number: 8743715
    Abstract: A network switch includes first and second clock-and-data-recovery (CDR) circuits, a cross-bar switch to couple the first and second CDR circuits, and a first test pattern generation circuit electrically coupled with the first CDR circuit. The first test pattern generation circuit is configured to generate a test pattern and transmit the test pattern from the first CDR circuit to the second CDR circuit via the cross-bar switch. The network switch also includes a first test pattern checking circuit, electrically coupled with the second CDR circuit, to verify the test pattern received at the second CDR circuit.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: June 3, 2014
    Assignee: OnPath Technologies Inc.
    Inventors: Richard Alan Eddy, Larry Cantwell
  • Patent number: 8738979
    Abstract: Methods and structure for correlating internal operational signals routed via different paths of a test signal selection hierarchy. The structure includes a functional block of circuitry operable to generate internal operational signals and clock signals. The integrated circuit also comprises a test signal selection hierarchy operable to receive the internal operational signals and the clock signals and to selectively route the internal operational signals and the clock signals. Further, structure includes a control unit operable to receive the clock signals from the test signal selection hierarchy, to determine a delay between received clock signals routed via different signaling pathways of the test signal selection hierarchy. The control unit is further operable to program a delay line based upon the delay between the clock signals and based upon internal operational signals correlated with the clock signals.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: May 27, 2014
    Assignee: LSI Corporation
    Inventors: Paul J. Smith, Jeffrey K. Whitt, Eugene Saghi, Douglas J. Saxon, Joshua P. Sinykin
  • Patent number: 8732544
    Abstract: A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: May 20, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinichi Kanno, Hironori Uchikawa
  • Patent number: 8718123
    Abstract: A test apparatus that tests a device under test exchanging a data signal and a clock signal, the test apparatus comprising a test signal supplying section that supplies the device under test with a data signal and a clock signal, as a test signal; a data acquiring section that acquires the data signal output by the device under test, at a timing corresponding to the clock signal output by the device under test; a judging section that judges pass/fail of the device under test based on a comparison result of a comparison between the data signal acquired by the data acquiring section and an expected value; and an adjusting section that, when performing an adjustment, adjusts a delay amount of the clock signal used to generate the timing at which the data signal is acquired.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: May 6, 2014
    Assignee: Advantest Corporation
    Inventors: Kazumichi Yoshiba, Hiromi Oshima
  • Patent number: 8713386
    Abstract: A device for increasing chip testing efficiency includes a pattern generator, a reading unit, a logic operation circuit, and a judgment unit. The pattern generator is used for writing a logic voltage to each bank of a memory chip. The reading unit is used for reading logic voltages stored in all memory cells of each bank. The logic operation circuit is used for executing a first logic operation on the logic voltages stored in all memory cells of each bank to generate a plurality of first logic operation results corresponding to each bank, and executing a second logic operation on the plurality of first logic operation results to generate a second logic operation result corresponding to the memory chip. The judgment unit determines whether the memory chip passes the test according to the second logic operation result.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: April 29, 2014
    Assignee: Etron Technology, Inc.
    Inventors: Shi-Huei Liu, Sen-Fu Hong, Ho-Yin Chen
  • Patent number: 8700964
    Abstract: A test apparatus that tests a device under test, including (i) a master domain that includes a master period signal generating section, which generates a master period signal, where the master domain operates based on the master period signal and (ii) a slave domain that includes a slave period signal generating section, which generates a slave period signal, where the slave domain operates based on the slave period signal. The master period signal generating section receives a control signal and resumes generation of the master period signal, which is on hold, and the slave period signal generating section receives the control signal, initializes phase data of the slave period signal, and resumes generation of the slave period signal, which is on hold.
    Type: Grant
    Filed: February 16, 2011
    Date of Patent: April 15, 2014
    Assignee: Advantest Corporation
    Inventor: Tatsuya Yamada
  • Publication number: 20140101507
    Abstract: System and method for testing a high speed data path without generating a high speed bit clock, includes selecting a first high speed data path from a plurality of data paths for testing. Coherent clock data patterns are driven on one or more of remaining data paths of the plurality of data paths, wherein the coherent clock data patterns are in coherence with a low speed base clock. The first high speed data path is sampled by the coherent clock data patterns to generate a sampled first high speed data path, which is then tested at a speed of the low speed base clock.
    Type: Application
    Filed: December 13, 2013
    Publication date: April 10, 2014
    Inventors: Miao Li, Xiaohua Kong, Nam Van Dang, Cheng Zhong
  • Patent number: 8688404
    Abstract: Aspects of the disclosure provide an apparatus for enabling common time-stamping. The apparatus includes a first subsystem having a first timer and a second subsystem having a second timer of a same frequency as the first timer. The first subsystem is configured to time-stamp first events based on the first timer. The second subsystem is configured to time-stamp second events based on the second timer. The apparatus further includes a synchronization module configured to take a first snapshot of the first timer and take a second snapshot of the second timer. Then, based on a difference between the first snapshot and the second snapshot, the first events and the second events are commonly time-stamped.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: April 1, 2014
    Assignee: Marvell International Ltd.
    Inventor: Eli Levy
  • Patent number: 8683285
    Abstract: In a first embodiment of the present invention, a method for error-correcting in a parallel interconnect transmitting device is provided, the method comprising: detecting a frame transition in a transmission from the transmitting device to a parallel interconnect receiving device; tracking time between the frame transition and a transition of a response signal corresponding to the frame transition received from the receiving device; detecting an error in the transmission; and restarting a portion of the transmission in response to the error, wherein the size of the portion of the transmission to restart is based upon the tracked time between the frame transition and the transition of a response signal corresponding to the frame transition.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: March 25, 2014
    Assignee: PLX Technology, Inc.
    Inventor: Jack Regula
  • Patent number: 8666007
    Abstract: A memory controller receives data and phase-providing signals from a memory device. The phase-providing signal is not a clock signal, but is used by the memory controller to phase align a local data-sampling signal with the incoming data. The memory controller samples the data signal with the data-sampling signal. The memory controller can perform maintenance operations to update the phase relationship between the phase-providing and data-sampling signals.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: March 4, 2014
    Assignee: Rambus Inc.
    Inventors: Scott C. Best, Richard E. Warmke, David B. Roberts, Frank Lambrecht
  • Patent number: 8635040
    Abstract: A signal measuring device, comprises one set, or a plurality of sets, of measuring unit(s) measuring an object of measurement in synch with a driving clock signal for measurement and outputting result of measurement as first data, and a timing identification unit which, in accordance with a measurement-start command, outputs a value, which differs every period, as second data in synch with a reference signal having a prescribed period and a speed lower than that of the driving clock signal; and a storage unit collecting and successively storing the first data and the second data as one set in synch with the driving clock signal.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: January 21, 2014
    Assignee: NEC Corporation
    Inventors: Koichi Nose, Masayuki Mizuno, Atsufumi Shibayama
  • Patent number: 8607111
    Abstract: An integrated circuit tester is described that utilizes methods of programming parallel coupled Algorithmic Pattern Generators (APGs) to generate test vector sequences and part commands with sub-instruction repeats. This enables simpler test programming and ease of test conversion to new part speed grades, steppings, or part designs. In one embodiment, a sub-instruction repeat is utilized to enable adjustment of the timing of test vector sequences and part commands sent to an integrated circuit device under test (DUT) so that the test can be adjusted for new part speed grades and/or steppings. In another embodiment, a sub-instruction repeats are utilized to enable adjustment of the timing of a memory device inputs, memory commands and test vector sequences so that the test can be adjusted for new memory device speed grades.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: December 10, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Phillip Rasmussen, Charles Snodgrass
  • Patent number: 8601305
    Abstract: A power gating device may include a control unit that generates a first interrupt signal based on a mode change signal when a mode of a system is changed from a normal operation mode to a stand-by mode, and generates a second interrupt signal based on the mode change signal when the mode is changed from the stand-by mode to the normal operation mode, a memory unit that stores data of a function block based on the first interrupt signal, and restores the stored data to the function block based on the second interrupt signal, and a power source unit that provides a normal operation power to the function block and the memory unit based on a power down signal in the normal operation mode, and provides a stand-by power to the memory unit based on the power down signal in the stand-by mode.
    Type: Grant
    Filed: August 16, 2010
    Date of Patent: December 3, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ki-Jong Lee
  • Patent number: 8589715
    Abstract: A method and system for correcting timing errors due to thermal changes within a portable computing device are disclosed. The system and method may include calculating an estimate of frequency for a first clock compared to a second clock. The first clock may comprise a crystal oscillator while the second clock comprises a system clock. Next, a sleep state may be calculated for a hardware device, such as radio access technology (“RAT”) module, based on the estimate of frequency for the first clock. An error in the frequency of the first clock that may occur during the sleep state of the hardware device may be calculated. Subsequently, a magnitude of time that corresponds to an actual length of the sleep state relative to the second clock may be calculated so that an internal clock of the hardware devices may be synchronized with the second clock.
    Type: Grant
    Filed: May 10, 2011
    Date of Patent: November 19, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Troy R. Curtiss, Vamsee K. Somavarapu, Glenn A. Salaman, Stanley Tsai, Gregory R. Lie
  • Patent number: 8589109
    Abstract: In general, according to one embodiment, a semiconductor circuit test method is disclosed. The method can generate a basic format of a test pattern and store the basic format in a test device. The basic format includes at least one parameter and a test program for testing a test target semiconductor circuit. The method can set a predetermined value for the parameter to generate the test pattern including the test program and the parameter set to the predetermined value and supply the test pattern to the test target semiconductor circuit. The method can have store the test program in a first address of a storing module in the test target semiconductor circuit and store the parameter set to the predetermined value in a second address of the storing module. In addition, the method can execute the test program stored in the first address while referring to the parameter stored in the second address.
    Type: Grant
    Filed: March 9, 2011
    Date of Patent: November 19, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takako Mando
  • Patent number: 8578227
    Abstract: A test device for a system-on-chip includes a sequential logic circuit and a test circuit. The sequential logic circuit generates a test input signal by converting a serial input signal into a parallel format in response to a serial clock signal and a serial enable signal and generates a serial output signal by converting a test output signal into a serial format in response to the serial clock signal and the serial enable signal. The test circuit includes at least one delay unit that is separated from a logic circuit performing original functions of the system-on-chip, performs a delay test on the at least one delay unit using the test input signal in response to a system clock signal and a test enable signal, and provides the test output signal to the sequential logic circuit, where the test output signal representing a result of the delay test.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: November 5, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Jae Son, Yong-Jin Yoon, Uk-Rae Cho
  • Patent number: 8560903
    Abstract: An example method is provided and includes executing a functional test for an integrated circuit and observing a failure associated with the integrated circuit. The method also includes executing a functional scan mode in order to reproduce the failure associated with the integrated circuit. A functional state of the integrated circuit is locked when the failure occurs, and the functional state is subsequently recovered for a structure test for the integrated circuit. In more particular embodiments, particular states of the functional test are evaluated and compared against other states associated with a model circuit that did not experience any failure in order to identify a latest cycle of the integrated circuit that could trigger the failure and an earliest cycle of the integrated circuit that could observe the failure.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: October 15, 2013
    Assignee: Cisco Technology, Inc.
    Inventors: Zhiyuan Wang, Xinli Gu, Zhanglei Wang, Hongxia Fang
  • Patent number: 8560991
    Abstract: Embodiments provide systems, devices, methods, and machine-readable medium for automated debugging of a design under test in a verification environment as part of electronic design automation. Embodiments may automatically identify inputs that are relevant to a bug for a device under test. A failing test run may be taken and rerun several times with small changes in the inputs. If the test is passing, the mutated inputs may be important to reproduce the bug and may be marked as “suspicious”. The result of this process may be a list of suspicious inputs and a shorter and simpler test that still fails. The shorter test may be rerun and fields of the inputs recorded. New tests may be created with mutated fields. Mutated fields that result in passing tests may be considered suspicious fields. Suspicious inputs and fields may be presented to a user as part of an electronic design process.
    Type: Grant
    Filed: October 5, 2010
    Date of Patent: October 15, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventor: Shai Fuss
  • Patent number: 8555124
    Abstract: An apparatus and method are provided for detecting an approaching error condition within a data processing apparatus and includes a sequential storage structure arranged to latch an output signal generated by combinatorial circuitry dependent on a second clock signal. The sequential storage structure has a main storage element to latch a value of the output signal for provision to subsequent combinatorial circuitry. The sequential storage structure can be operated in either first or second modes of operation where, in the first mode, the predetermined timing window is ahead of a time at which the main storage element latches said value of the output signal enabling an approaching setup timing error to be detected. In the second mode, the predetermined timing window is after the time at which the main storage element latches said value of the output signal where an approaching hold timing error is detected.
    Type: Grant
    Filed: June 7, 2010
    Date of Patent: October 8, 2013
    Assignee: ARM Limited
    Inventors: Sachin Satish Idgunji, Shidhartha Das, David Michael Bull, Robert Campbell Aitken
  • Publication number: 20130262946
    Abstract: Methods and structure for correlating internal operational signals routed via different paths of a test signal selection hierarchy. The structure includes a functional block of circuitry operable to generate internal operational signals and clock signals. The integrated circuit also comprises a test signal selection hierarchy operable to receive the internal operational signals and the clock signals and to selectively route the internal operational signals and the clock signals. Further, structure includes a control unit operable to receive the clock signals from the test signal selection hierarchy, to determine a delay between received clock signals routed via different signaling pathways of the test signal selection hierarchy. The control unit is further operable to program a delay line based upon the delay between the clock signals and based upon internal operational signals correlated with the clock signals.
    Type: Application
    Filed: March 30, 2012
    Publication date: October 3, 2013
    Inventors: Paul J. Smith, Jeffrey K. Whitt, Eugene Saghi, Douglas J. Saxon, Joshua P. Sinykin
  • Publication number: 20130262945
    Abstract: Methods and structure for correlating multiple sets of test output signals in time are provided. The structure includes an integrated circuit comprising a block of circuitry that generates internal operational signals. The circuit also comprises a test multiplexer (MUX) hierarchy that selects subsets of the internal signals and applies the subsets to a testing element. A clock generator generates a clock signal for the selected signals. A test logic timer receives the clock signal and increments a counter value, and applies the counter value to the testing element. An event detector resets the counter value upon detection of an event, such that a first subset of the internal signals acquired from the test MUX hierarchy acquired responsive to detection of a first instance of the event may be correlated in time with a second subset of the internal signals acquired responsive to detection of a second instance of the event.
    Type: Application
    Filed: March 30, 2012
    Publication date: October 3, 2013
    Inventors: Eugene Saghi, Jeffrey K. Whitt, Joshua P. Sinykin
  • Patent number: 8515416
    Abstract: In a radio device such as a receiver or transceiver, a test operation can be performed to determine performance. A received signal can be processed to obtain demodulated samples, which can be provided to a logic to perform a logic operation on the samples to generate a logic output. A storage such as a counter or other mechanism is coupled to the logic to store a count of a number of the logic outputs having an error.
    Type: Grant
    Filed: April 29, 2011
    Date of Patent: August 20, 2013
    Assignee: Silicon Laboratories Inc
    Inventor: Hendricus De Ruijter
  • Patent number: 8502523
    Abstract: Provided is a test apparatus and a test method for substantially synchronizing phases of test signals for each of a plurality of clock domains. The test apparatus tests a device under test including a plurality of clock domains.
    Type: Grant
    Filed: February 9, 2011
    Date of Patent: August 6, 2013
    Assignee: Advantest Corporation
    Inventor: Tatsuya Yamada
  • Patent number: 8473797
    Abstract: Circuit for detecting malfunction of a primary clock in SoCs comprises a primary clock circuit having a GRAY code counter for generating a GRAY code sequence based on a number of clock pulses generated Primary clock. A secondary clock circuit is configured to output a secondary clock pulse on each saturation of a secondary clock counter. A clock gated register circuit is clocked by the secondary clock pulse, and is configured to store a plurality of values of the GRAY code sequence, and update the plurality of values of the GRAY code sequence on each saturation of the secondary clock counter. An error detection circuit is configured to output a detection signal for detecting the malfunction of primary clock based on a comparison of the updated plurality of values of the GRAY code sequence with at least one predetermined threshold associated with the malfunction of primary clock.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: June 25, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Chirag Sureshchandra Gupta, Saya Goud Langadi, Padmini Sampath
  • Patent number: 8468397
    Abstract: An error controlling system includes a plurality of error generation target circuits, a plurality of pseudo error generating devices each having a pseudo error content holding register that holds directed pseudo error content, each plurality of pseudo error generating device generates a pseudo error corresponding to a pseudo error content held in a respective pseudo error content holding register in at least one of data to be written to one of the plurality of error generation target circuits and data to be read from one of the plurality of error generation target circuits upon being directed to generate the pseudo error, and a pseudo error controlling device that directs the plurality of pseudo error generating devices to generate a pseudo error corresponding to a respective pseudo error content held in each of the pseudo error content holding register provided in each of the plurality of pseudo error generating devices.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: June 18, 2013
    Assignee: Fujitsu Limited
    Inventor: Iwao Yamazaki
  • Patent number: 8458546
    Abstract: In described embodiments, a transceiver supports two or more rates using an oversampling clock and data recovery (CDR) circuit sampling high rate data with a predetermined CDR sampling clock. A timing recovery circuit detects and accounts for extra or missing samples when oversampling lower rate data. An edge detector detects each actual data symbol edge and provides for an edge decision offset in a current instant's block of samples. An edge error is generated from the previous instant's actual and calculated edges; and an edge distance between actual edges of the current and previous instants is generated. Filtered edge distance and error are combined to generate a calculated edge position for the data symbol edge for the current instant. The edge decision offset is applied to the current calculated edge position to identify a sample value to generate a decision for the data symbol to detect the current data value.
    Type: Grant
    Filed: May 12, 2011
    Date of Patent: June 4, 2013
    Assignee: LSI Corporation
    Inventors: Mohammad Mobin, Matthew Tota, Gregory Winn