Abstract: A system and method for digital communication wherein a host provides a host clock and a clockless device transmits to the host a bit stream synchronized according to the clock at a data rate that is an integer multiple of the clock rate. A training mechanism using training data detects time skew between host clock and bit stream, and a digital skew compensation mechanism compensates, substantially in real time, for the skew and for variations in the skew that may occur with the passage of time, in accordance with a vote among at least three samples of a bit of the bit stream, subsequent sampling being retarded or advanced if, respectively, an early or late sample is in disagreement with the vote. Preferably, the compensation value is selected from at least four possible compensation values, and can be stored in a memory to hasten subsequent restarts of the system.

Abstract: Various exemplary embodiments provide methods and apparatuses for generating test conditions that efficiently detect delay faults while preventing overkill. According to an exemplary embodiment, i) test timing correcting block sets test timing faster than the actual operation timing of a logical circuit to be tested, ii) logical simulation block performs simulation by using delay times of signal paths corrected by adding minimum slack margin, and iii) when the simulation indicates that an end-side flip-flop cannot acquire data after an expected transition of logical value, masking block generates mask data that masks data held in the end-side flip-flop.

Abstract: A semiconductor integrated circuit includes a clock generator for generating a second clock signal having a frequency that varies over time by using a first clock signal having a fixed frequency, a test circuit for generating a digital signal according to a difference between a first frequency corresponding to the first clock signal and a second frequency corresponding to the second clock signal by a digital logic operation based on the first clock signal and the second clock signal, and a signal path for outputting the digital signal generated by the test circuit.

Abstract: An integrated circuit may have a circuit under test. The integrated circuit may have a clock generation circuit that receives a reference clock from a tester and that generates a corresponding core clock. The integrated circuit may have a built in self test circuit and a clock synthesizer that receives the core clock. The built in self test circuit may provide clock synthesizer control signals that direct the clock synthesizer to produce test clock signals at various test clock frequencies. The test clock at the test clock frequencies may be applied to the circuit under test during circuit testing. The circuit under test may assert a pass signal when the circuit tests are completed successfully. The built in self test circuit may inform the tester of the maximum clock frequency at which the circuit under test successfully passes testing.

Abstract: A data transfer device transfers data between two clock domains of a data processing device when the data processing device is in a test mode. The data transfer device receives clock signals associated with each clock domain. To transfer data from a first clock domain to a second clock domain the data transfer device identifies transitions of clock signals associated with each clock domain that are sufficiently remote from each other so that data can deterministically be provided by one clock domain and sampled by the other. This ensures that data can be transferred between the clock domains deterministically even when the phase relationship between the clock signals is indeterminate.

Abstract: Provided is a test apparatus that tests a device under test, comprising (i) a master domain that includes a master period signal generating section, which generates a master period signal, and that operates based on the master period signal and (ii) a slave domain that includes a slave period signal generating section, which generates a slave period signal, and that operates based on the slave period signal. The master period signal generating section receives a control signal and resumes generation of the master period signal, which is being held, and the slave period signal generating section receives the control signal, initializes phase data of the slave period signal, and resumes generation of the slave period signal, which is being held.

Abstract: An apparatus that reduces sampling errors for data communicated between devices uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling signal for sampling a data signal that was sent along with the timing reference signal. The data-sampling signal may be provided by adjustably delaying a clock signal according to the phase information acquired from the strobe signal. The data-sampling signal may also have an improved waveform compared to the timing reference signal, including a fifty percent duty cycle and sharp transitions. The phase information acquired from the timing reference signal may also be used for other purposes, such as aligning received data with a local clock domain, or transmitting data so that it arrives at a remote device in synchronism with a reference clock signal at the remote device.

Abstract: A test device for a system-on-chip includes a sequential logic circuit and a test circuit. The sequential logic circuit generates a test input signal by converting a serial input signal into a parallel format in response to a serial clock signal and a serial enable signal and generates a serial output signal by converting a test output signal into a serial format in response to the serial clock signal and the serial enable signal. The test circuit includes at least one delay unit that is separated from a logic circuit performing original functions of the system-on-chip, performs a delay test on the at least one delay unit using the test input signal in response to a system clock signal and a test enable signal, and provides the test output signal to the sequential logic circuit, where the test output signal representing a result of the delay test.

Abstract: A method and apparatus to compact test responses containing unknown values or multiple fault effects in a deterministic test environment. The proposed selective compactor employs a linear compactor with selection circuitry for selectively passing test responses to the compactor. In one embodiment, gating logic is controlled by a control register, a decoder, and flag registers. This circuitry, in conjunction with any conventional parallel test-response compaction scheme, allows control circuitry to selectively enable serial outputs of desired scan chains to be fed into a parallel compactor at a particular clock rate. A first flag register determines whether all, or only some, scan chain outputs are enabled and fed through the compactor. A second flag register determines if the scan chain selected by the selector register is enabled and all other scan chains are disabled, or the selected scan chain is disabled and all other scan chains are enabled.

Abstract: Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated from the captured first group. A second group of applied data signals is then captured and determined to have been properly captured when the second group corresponds to the group of expect data signals. In this way, when a captured series of data signals is shifted in time from an expected capture point, subsequent captured data signals are compared to their correct expected data signals in order to determine whether that group, although shifted in time, was nonetheless correctly captured. A pattern generator generates expect data signals in this manner, and may be utilized in a variety of integrated circuits, such as an SLDRAM.

Abstract: A system comprises storage that includes first and second data. The system also comprises circuit logic coupled to the storage. The circuit logic receives a plurality of clock signals. As a result of receiving a signal, the circuit logic uses the plurality of clock signals to obtain the first and second data and to provide the first and second data to target logic coupled to the circuit logic. The system resets the circuit logic between providing the first data and providing the second data.

Abstract: A method and apparatus for testing of integrated circuits using a Direct Memory Load Execute Dump (DMLED) test module. The method includes loading a test case into a memory using the DMLED test module, loading initialization signatures of fixed pattern into the memory using the DMLED test module, and executing the test case at an operating clock rate of a processor. The method further includes writing result signatures into the memory, and dumping the results signatures from the memory to a tester using the DMLED test module.

Abstract: A clock generator is disclosed that includes an array of MEMS resonators and a test circuit. The test circuit is operable at start-up to operate one or more of the MEMS resonators to generate test output and analyze the test output to determine whether the operated MEMS resonators meet test criteria. A MEMS resonator is selected that meets the test criteria and its output is used to generate an output clock signal. In addition, the test circuit is operable to analyze the output of the selected MEMS resonator and select a replacement MEMS resonator when the output of the selected MEMS resonator no longer meets the test criteria. The replacement MEMS resonator is then operated and its output is coupled to the output of the clock generator. Thereby, failing and potentially failing MEMS resonators are automatically replaced during operation of the clock generator in its end-use application.

Abstract: A circuit verifying method is provided for a logic circuit of a first sequential circuit which outputs a first data based on an input data in synchronization with a first clock signal, and a second sequential circuit which outputs a second data based on the first data in synchronization with a second clock signal with a period longer than that of a first clock signal. The circuit verifying method includes detecting a change of the input data in synchronization with the first clock signal; outputting a data indicating a meta stable state during a period longer than one period of the first clock signal based on the change of the input data as the first data; storing the changed input data in a storage unit based on the change of the input data; and outputting the changed input data which has been stored in the storage unit as the first data after stop the output of the data indicating the meta stable state.

Abstract: A test architecture and method of testing are disclosed to allow multiple scan controllers, which control different scan chain designs in multiple logic blocks, to share a test access mechanism. During test mode, the test architecture is configured to decouple clock sources of the test access mechanism, the scan controllers and the scan chains.

Abstract: A semiconductor integrated circuit, including a data input unit for receiving an input data signal to be supplied to an external data input terminal, a storage unit for storing the input data signal received by the data input unit, a timing generating unit for generating a timing signal in response to an output request signal, a data output unit for outputting, in synchronization with the timing signal, the input data signal stored in the storage unit as an output data signal, a test output control unit for outputting, in synchronization with the timing signal, and a data selector for outputting the output data signal supplied from the data output unit to the external data output terminal in a normal operation mode and outputting the input data signal supplied from the test output control unit to the external data output terminal in a test mode.

Abstract: Disclosed is a semiconductor integrated circuit including a first storage circuit and a second storage circuit that respectively store logic levels of an input to the delay circuit and an output of the delay circuit when a logic level of a clock line is changed, and a determination circuit that determines whether or not the results of the first storage circuit and the second storage circuit coincide or not. Even if a transistor or a wiring that constitutes the semiconductor integrated circuit has been degraded due to secular change or the like, a possibility of an anomaly or a failure in one of the operation circuits caused by the degradation can be predicted before the anomaly or the failure occurs.

Abstract: Provided is a jitter injection circuit that generates a jittery signal including jitter, including a plurality of delay circuits that are connected in a cascading manner and that each sequentially delay a supplied reference signal by a preset delay amount and a signal generating section that generates each edge of the jittery signal according to a timing of the signal output by each delay circuit. In the jitter injection circuit the delay amount of at least one delay circuit is set to be a value different from an integer multiple of an average period of the jittery signal.

Abstract: An electronic circuit contains groups of flip-flops (12a-c), coupled to data terminals (11a-c) of the circuit and to a functional circuit (10). Each group (12a-c) has a clock input for clocking the flip-flops of the group. Each group (12a-c) can be switched between a shift configuration and a functional configuration, for serially shifting in test data from the data terminals and to function in parallel to supply signals to the functional circuit (10) and/or receive signals from the functional circuit (10) respectively. A test control circuit (16) can be switched between a functional mode, a test shift mode and a test normal mode. The test control circuit (16) is coupled to the groups of flip-flops (12a-c) to switch the groups to the functional configuration in the functional mode and to the shift configuration in the test shift mode. A clock multiplexing circuit (15a-c, 18) has inputs coupled to the data terminals (11a-c) and outputs coupled to clock inputs of the groups (12a-c).

Abstract: A multi-clock system-on-chip (D) comprises i) a core (CE) comprising asynchronous clock domains provided for exchanging test data therebetween, ii) a clock generator unit (CGU) arranged for delivering primary clock signals (clk1-clko) for at least some of the clock domains, and iii) clock control modules (CCl-CCo), arranged respectively for defining the functional clock signals from the primary clock signals and from control signals (intended for setting the clock control modules (CCl) in a normal mode allowing test data transmission from the corresponding emitter clock domain to at least one receiver clock domain or a shift mode forbidding such a test data transmission).

Abstract: An electronic device includes an integrated circuit operating on the basis of an operating clock signal, an error detection circuit and a control circuit coupled to the error detection circuit. The control circuit is configured to increase the frequency of the operating clock signal starting from a nominal operating frequency of the integrated circuit, to evaluate a frequency increment at which an error is detected by the error detection circuit, and to reset the frequency of the operating clock signal to said nominal frequency.

Abstract: A debug circuit for a multi-mode circuit driven by a clock signal, with an input for a clock signal, and a debug signal generator arranged to generate for each of a subset of the modes of the multi-mode circuit a corresponding debug signal based on a clock signal provided at the input. The frequency of debug signals is dependent on the frequency of a clock signal provided at the input, and each debug signal selects its respective mode for a length of time longer than that of each other mode of the multi-mode circuit, or each debug signal selects its respective mode for a length of time shorter than that of each other mode of the multi-mode circuit.

Abstract: A semiconductor device including a logic circuit and a test circuit is provided which comprises: a logic signal terminal that supplies a signal to the logic circuit; a latch circuit that latches a signal based on a synchronization signal from the test circuit; a first selection circuit that supplies an external signal from the logic signal terminal to one of the logic circuit and the latch circuit selectively based on a test mode signal; and a second selection circuit that supplies one of the external signal and a signal from the test circuit selectively to a memory.

Abstract: Systems, controllers and methods are disclosed, such as an initialization system including a controller that receives patterns of read data coupled from a memory device through a plurality of read data lanes. The controller is operable to detect any lane-to-lane skew in the patterns of read data received through the read data lanes. The controller then adjusts the manner in which the read data received through the read data lanes during normal operation are divided into frames. The controller can also couple patterns of command/address bits to the memory device through a plurality of command/address lanes. The memory device can send the received command/address bits back to the controller through the read data lanes. The controller is operable to detect any lane-to-lane skew in the patterns of command/address bits received through the read data lanes to adjust the manner in which the command/address bits coupled through the command/address lanes during normal operation are divided into frames.

Abstract: In one embodiment, the invention is a method, apparatus, and design structure for built-in self-test for embedded memory in integrated circuit chips. One embodiment of a method for built-in self-test of an embedded memory includes setting up a plurality of test patterns at a speed of a test clock, where the speed of the test clock is slow enough for a tester to directly communicate with a chip in which the memory is embedded, and where the setting up includes loading a plurality of signal states used to communicate the test patterns to one or more components of a built-in self-test system, applying the test patterns to the embedded memory as a microburst at-speed, capturing output data from the embedded memory at-speed, the output data corresponding to only one of test patterns, and comparing the output data to expected data at the speed of the test clock.

Abstract: An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP of another IC. The Off Chip TAP interface can be selected by a TAP Linking Module on the IC.

Abstract: In a method of performing a test on a logic circuit in accordance with an exemplary aspect of the present invention, the test is performed by supplying a clock signal from a clock supply circuit to a plurality of clock domains operating by a clock signal of a same frequency. The method includes calculating a number of test patterns of each of the plurality of internal clock domains; classifying the plurality of clock domains into a plurality of groups based on the calculated number of test patterns; and assigning a clock supply circuit independently to each of the groups into which the clock domains are classified.

Abstract: According to an embodiment of the invention, a system for identifying when a running speed of an integrated circuit is within an applied clock speed is provided. A monotonic circuit is configured to receive input data and transmit output data. A completion detection circuit is configured to generate a completion detection signal for the monotonic circuit. A comparator is configured to compare at least the completion detection signal and a clock signal, and configured to emit an error signal if the clock signal arrives before the completion detection signal. A synchronous circuit element is configured to receive at least a portion of the output data and configured to be clock driven by the clock signal. The error signal represents that the clock speed is faster than an operating speed of the monotonic circuit.

Abstract: A test system timing method simulates the timing of a synchronous clock on the device under test. Strobe pulses can be generated by routing an edge generator to delay elements with incrementally increasing delay values. A data signal or synchronous clock signal can be applied to the input of each of a set of latches which are clocked by the strobe pulses. An encoder can convert the series of samples which are thereby latched to a word representing edge time and polarity of the sampled signal. If the sampled signal is a data signal, the word can be stored in memory. If the sampled signal is a clock signal, the word is routed to a clock bus and used to address the memory. The difference between clock edge time and data edge time is provided and can be compared against expected values.

Abstract: A semiconductor integrated circuit includes a clock generator which generates a first clock, a test data generator which modulates a phase of the first clock, and generates test data to which jitter is added by using the modulated clock, a data extractor which samples the test data and extracts recovery data, and a detector which detects an error of the recovery data.

Abstract: Provided is a test apparatus for testing a device under test, including: a plurality of signal supply sections that output test signals at different timing from each other; and a connection section that connects lines of wiring transmitting the test signals respectively outputted from the signal supply sections with each other, connects the lines of wiring to an input terminal of the device under test, and inputs the test signals to the input terminal after superposing the test signals. The connection section may include a performance board to which the device under test is mounted, where the lines of wiring are connected with each other on the performance board.

Abstract: Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns for testing integrated circuits. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) environment). Certain embodiments of the disclosed technology can reduce the switching rates, and thus the power dissipation, in scan chains with no hardware modification. Other embodiments use specialized decompression hardware and compression techniques to achieve low power testing.

Abstract: A clock signal within an application-specific integrated circuit (ASIC) is characterized while operating a subsystem. Subsequently, also on the ASIC, a testing clock signal is generated, based on the characterization of the operative clock signal, for purposes of testing the subsystem operating according to the testing clock signal instead of the clock signal. The ASIC includes a clock signal characterization circuit configured to characterize a clock signal within the ASIC; a programmable testing clock signal generator configured for being programmed based on said characterization of the clock signal, and for generating a test clock signal based on its said programming; and the subsystem tested when operating according to the testing clock signal instead of the clock signal.

Abstract: A detection apparatus is provided. The detection apparatus includes; a multi-strobe generating section that generates a plurality of strobe signals with phases different from one another; a plurality of acquiring sections each of which acquires a signal value of a signal under measurement at a timing of each of the plurality of strobe signals; a plurality of changing point detecting sections that detect a fact that there is a changing point of the signal under measurement between two adjacent strobe signals when two signal values which are acquired in accordance with the two adjacent strobe signals are different from one another; a mask setting section that sets the changing point detecting section to be enabled among the plurality of changing point detecting sections; and a changing timing output section that outputs a changing timing of the signal under measurement based on an output of the enabled changing point detecting section.

Abstract: Provided are a method and system for testing a semiconductor memory device using an internal clock signal of the semiconductor memory device as a data strobe signal. The internally-generated data strobe signal may be delayed to synchronize with test data. Because a test device need not supply the data strobe signal, the number of semiconductor memory modules that can be simultaneously tested can be increased, and an average test time for a unit memory module can be decreased.

Abstract: A system and method for reducing timing errors in automated test equipment (ATE) offering increased data rates for the testing of higher-speed integrated circuits. Embodiments provide an effective mechanism for increasing the data rate of an ATE system by delegating processing tasks to multiple test components, where the resulting data rate of the system may approach the sum of the data rates of the individual components. Each component is able to perform data-dependent timing error correction on data processed by the component, where the timing error may result from data processed by another component in the system. Embodiments enable timing error correction by making the component performing the correction aware of the data (e.g., processed by another component) causing the error. The data may be shared between components using existing timing interfaces, thereby saving the cost associated with the design, verification and manufacturing of new and/or additional hardware.

Abstract: There is provided a method that includes, (a) determining a first clock frequency for shifting a first section of a scan pattern set through a path in a digital circuit such that a first power dissipated by the digital circuit while shifting the first section does not exceed a power limit, (b) determining a second clock frequency for shifting a second section of the scan pattern set through the path such that a second power dissipated by the digital circuit while shifting the second section does not exceed the power limit, (c) shifting the first section through the path at the first clock frequency, and (d) shifting the second section through the path at the second clock frequency, where first and second clock frequencies are different from one another. There is also provided a system that performs the method.

Abstract: A test apparatus that tests a device under test is provided, including a driver section that supplies a test signal to a corresponding pin of the device under test, a judgment section that makes a judgment concerning pass/fail of the device under test based on the response signal output by the device under test in response to the test signal, a voltage measuring section that detects a DC voltage of the signal output by the driver section, and an output side adjusting section that adjusts a duty ratio of the signal output by the driver section according to the DC voltage detected by the voltage measuring section.

Abstract: A method and system for testing a semiconductor memory device using low-speed test equipment. The method includes providing a high-frequency test pattern by grouping a command signal and an address signal into command signal groups and address signal groups each corresponding to L cycles of a clock signal output from automatic test equipment (ATE) where L is a natural number. A valid command signal and a valid address signal, which are not in an idle state, are extracted from each of a plurality of command signal groups and each of a plurality of address signal groups. The valid command signal and the valid address signal are compressed into signals having a length corresponding to 1/M (M is a natural number larger than 1) of the cycle of the clock signal where M is a natural number larger than 1. A position designating signal indicating the positions of the valid command signal and the valid address signal in each command signal group and each address signal group is generated.

Abstract: A test board includes a plurality of test modules. Each test module stores a first control signal, a data signal, and a second control signal in response to a clock signal, and tests a corresponding device under test (DUT) using the first control signal and the stored data signal in response to the second control signal to generate an error signal indicating whether the DUT is defective. Each test module outputs the first control signal, the data signal, and the second control signal to a test module in a next stage, and each test module of a subsequent stage receives the error signal stored generated by a test module in a previous stage in response to the clock signal.

Abstract: During a trace the timing stream has the active and stall information, PC stream has all the discontinuity information, and the data stream has all the data log information. The various streams are synchronized using markers called sync points. The sync points provide a unique identifier field and a context to the data that will follow it. After data corruption a sync point is inserted into the data stream. The ID of this sync point may repeat a previous sync point ID.

Abstract: An electronic device includes an integrated circuit operating on the basis of an operating clock signal, an error detection circuit and a control circuit coupled to the error detection circuit. The control circuit is configured to increase the frequency of the operating clock signal starting from a nominal operating frequency of the integrated circuit, to evaluate a frequency increment at which an error is detected by the error detection circuit, and to reset the frequency of the operating clock signal to said nominal frequency.

Abstract: A digital test instrument and a test method provide adjustable results latency. A digital test instrument includes a pattern controller configured to generate a sequence of test patterns, responsive, at least in part, to a pass/fail result, a pattern memory configured to supply the generated sequence of test patterns to a unit under test, a pattern results collection unit configured to receive at least one result value from the unit under test and to determine a pass/fail result for at least one supplied test pattern, and a synchronization unit configured to provide a no-result indication to the pattern controller during a preset number of pattern cycles following the start of a test, the preset number of pattern cycles based on a results latency of the test instrument, and to provide pass/fail results to the pattern controller after the preset number of pattern cycles.

Abstract: A signal generator device for generating at least one periodic signal for use in a data eye scan system. The signal generator comprises a clock input, at least one output and at least one signal generator coupled with the clock input and with the output. The signal generator is at least one token ring with a predetermined number of positions and is operable to propagate at least one token in the ring by moving the token from its current position to a following position dependent on a clock signal from the clock input. The signal generator further comprises a predetermined number of signal value units that each represent a respective predetermined signal value of a predetermined signal waveform and are operable to provide the signal value at an output of the signal generator dependent on a current position of the at least one token in the token ring.

Abstract: A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus allows generating and loading N pseudorandom or predetermined stimuli to all the scan cells within the N clock domains in the integrated circuit or circuit assembly during the shift operation, applying an ordered sequence of capture clocks to all the scan cells within the N clock domains during the capture operation, compacting or comparing N output responses of all the scan cells for analysis during the compact/compare operation, and repeating the above process until a predetermined limiting criteria is reached. A computer-aided design (CAD) system is further developed to realize the method and synthesize the apparatus.

Abstract: A system LSI including a semiconductor chip which receives power from a power supply, and an electronic timer which measures a time from an interruption of power supplying to the semiconductor chip to a resumption of power supplying to the semiconductor chip.

Abstract: A system and method for testing multiple smart card devices in parallel and asynchronously are provided. The system includes a smart card module that may be easily inserted in a digital test system. The smart card module includes multiple smart card instrument channels, each one of which testing a separate smart card device independently and asynchronously from the others. The smart card instrument channels employ a novel modulation technique based on palette waveforms that are formed of transitions between two data bits.

Abstract: The test method, integrated circuit and test system embodiments disclosed herein relate to testing at least one integrated circuit which uses an internal operating clock and has a first number of address pins, a second number of command pins and an address generation circuit which receives at least one encoded address information item using a third number of the address pins, which is smaller than the first number, and provides the other address pins as a fourth number of free address pins, where at least one first command is transferred using the command pins and at least one second command is transferred using at least one portion of the fourth number of the address pins from a test apparatus to the integrated circuit using a test clock which has a lower rate than the internal operating clock.

Abstract: A system and method for testing an integrated circuit module including multiple integrated circuit devices that provide a data strobe signal associated with at least one data signal provided by the same integrated circuit device. A determination of a test outcome for the integrated circuit module may be made after identifying data valid windows for each integrated circuit device, without having to both identify a common sampling window defined by an intersection of the identified data valid windows and verify that such common sampling window meets specification requirements.

Abstract: A circuit for generating tracking error signal using differential phase detection, comprising a quadrant photodetector for receiving optical signal and inducting splitting signal A, splitting signal B, splitting signal C and splitting signal D, two adders for generating group signal (A+C) and group signal (B+D). A plurality of equalizers for receiving, equalizing and amplifying splitting signal A, splitting signal B, splitting signal C, splitting signal D, group signal (A+C) and group signal (B+D). A plurality of phase detectors for receiving the output of equalizers and comparing phase difference of splitting signal A and group signal (A+C), group signal (A+C) and splitting signal B, splitting signal C and group signal (B+D), and group signal (B+D) and splitting signal D, and outputting a plurality of adjustment signals respectively. A circuit for eliminating the phase difference by adding and subtracting some adjustment signals with same phase difference.