Abstract: Certain aspects of the present disclosure relate to methods and apparatus for Coordinated Multipoint (CoMP) communications. Certain aspects relate to methods and apparatus for determining resource mapping and/or rate matching for CoMP operations.

Abstract: Methods and apparatus are provided for transmitting and receiving data in a wireless communication system. Resource allocation information is received and hopping-related information is identified. A resource for transmitting data is determined based on the resource allocation information and hopping-related information, and data is transmitted on the determined resource. A sub-band is determined from a plurality of sub-bands based on the first hopping parameter and a resource in the determined sub-band is determined based on the second hopping parameter.

Abstract: Embodiments of a master station and method for high-efficiency Wi-Fi (HEW) communication using a multi-device HEW preamble are generally described herein. In some embodiments, the master station may select a number of long-training fields (LTFs) to be included in the multi-device HEW preamble of an HEW frame. The HEW frame may comprise a plurality of links for transmission of a plurality of streams. The master station may transmit the selected number of LTFs sequentially as part of the HEW preamble and transmit a plurality of data fields to scheduled stations during an HEW control period. Each data field may correspond to one of the links and may comprise one or more streams. The selection of the number of LTFs to be included in the HEW preamble may be based on a maximum number of streams to be transmitted on a single link.

Abstract: A circuit arrangement for determining m check bits c1, . . . , cm for k data bits u1, . . . , uk is provided, wherein the circuit arrangement includes a first subcircuit and a second subcircuit. The first subcircuit has k binary inputs for inputting the k data bits u=u1, . . . , uk and M binary outputs for outputting M binary intermediate values z1, . . . , zM determined from the data bits. The second subcircuit is configured to transform the intermediate values z1, . . . , zM into the check bits c1, . . . , cm.

Abstract: A circuit arrangement for detecting memory errors is provided. The circuit arrangement comprises a memory (11) and an error detection circuit (12). The circuit arrangement is designed to store a code word of an error detection code (C) or a code word that is inverted in a subset (M) of bits in the memory (11) at a memory location and to read out a data word from the memory (11) from the memory location. The error detection circuit (12) is designed, for the case where a control signal present assumes a first value, to indicate a memory error if the data word is not a code word of the error detection code (C).

Abstract: A trellis coded modulator and method for generating an encoded word from an input word. The TCM has a first logic branch configured to generate a data portion of the encoded word; and a second logic branch, coupled in parallel with the first logic branch, and configured to generate a corresponding parity portion of the encoded word sequentially after the generation of the data portion of the encoded word.

Abstract: A method for encoding multi-modes of BCH codes and an associated encoder is disclosed. The method has the steps of: building a number of encoding matrices; combining the encoding matrices with one side aligned to form a combined matrix; seeking common sub-expressions (CSEs) in the combined matrix, and encoding a message using the combined matrix.

Abstract: An operation method of a flash memory system includes reading data stored in a memory device, wherein the data is encoded by units of message blocks each including a row constituent code and a column constituent code by using a block-wise concatenated Bose-Chadhuri-Hocquenghem (BC-BCH) method; performing a hard decision decoding on the read data; determining, when the hard decision decoding fails, a reference voltage for a message block having an error among the message blocks of the read data; and performing a soft decision decoding by using the determined reference voltage.

Abstract: In one embodiment, a system for cycle-slip resilient iterative read channel operation includes a processor and logic integrated with and/or executable by the processor. The logic is configured to, in an iterative process until a maximum number of iterations has been reached or a valid codeword is produced, execute cycle-slip detection on signal samples to detect one or more cycle-slip events. Also, the logic is configured to selectively alter a timing estimate driving a phase-locked loop (PLL) during any time interval determined to experience a cycle slip in a first pass as indicated by one or more cycle-slip pointers. Additionally, the logic is configured to generate a set of decisions provided by a detector and generate a set of decisions provided by a decoder. Moreover, the logic is configured to output decoding information relating to the signal samples in response to a decoding algorithm producing a valid codeword.

Abstract: A method for increasing coding reliability includes generating a generator matrix for an extended polar code including a standard polar code part and an additional frozen part. The standard polar code part has N bit-channels, including K information bit-channels and N?K frozen bit-channels. The additional frozen part has q additional frozen bit-channels. Among the K information bit-channels, q information bit-channels are re-polarized using the q additional frozen bit-channels. The method further includes receiving an input vector including K information bits and N+q?K frozen bits, and transforming, using the generator matrix, the input vector to an output vector including N+q encoded bits. The K information bits are allocated to the K information bit-channels, and the N+q?K frozen bits are allocated to the N?K frozen bit-channels and the q additional frozen bit-channels.

Abstract: An operation method of a flash memory system includes: obtaining first syndrome values to a codeword; obtaining locations of errors and the number of the locations of errors based on the first syndrome values; error-correcting the codeword by flipping bit values of error bits of the codeword based on the locations of errors to generate an error-corrected codeword; obtaining second syndrome values to the error-corrected codeword; determining whether an error is found in the error-corrected codeword based on the second syndrome values; changing the first syndrome values when it is determined that no error is found in the error-corrected codeword; and restoring the error-corrected codeword to the codeword by re-flipping the flipped bit values when it is determined that an error is found in the error-corrected codeword.

Abstract: Embodiments of decoders having early decoding termination detection are disclosed. The decoders can provide for flexible and scalable decoding and early termination detection, particularly when quasi-cyclic low-density parity-check code (QC-LDPC) decoding is used. In one embodiment, a decoder iteratively decodes a data unit using a decoding matrix comprising a plurality of layers. After at least one iteration of decoding the data unit, the decoder determines whether the decoded data unit from a completed iteration and one or more layers of the plurality of layers satisfy a parity check equation. In response to determining that the decoded data unit from the completed iteration and each layer of the plurality of layers satisfy the parity check equation, the decoder terminates decoding the data unit. Advantageously, the termination of decoding of the data unit can reduce a number of iterations performed to decode the data unit.

Abstract: A distributed object storage system has a monitoring agent and/or a maintenance agent configured to determine for each of a plurality of repair tasks the actual concurrent failure tolerance of a corresponding repair data object. The actual concurrent failure tolerance corresponds to the number of storage elements that store sub blocks of the repair data object and are allowed to fail concurrently.

Abstract: Implementations disclosed herein provide a method comprising applying voltage to a read head during an unload state, detecting characteristic read head data, and storing the detected characteristic read head data in a buffer. In another implementation, the method further comprises performing a read retry operation in response to a read failure, reading the detected characteristic read head data from the buffer, determining if the detected characteristic read head data meets a threshold for a first predetermined criterion, performing a correction operation if the threshold for the first the first predetermined criterion is met, determining whether a media sector is read successfully, and ending the read retry operation if the media sector is read successfully.

Abstract: According to one embodiment, a memory controller includes a decoder configured to perform approximate maximum likelihood decoding, the decoder including: an initial value generation unit configured to calculate first data on the basis of a received word read from a non-volatile memory; a storage unit configured to store the first data and a predetermined number of second data; an update unit configured to calculate new second data by using the predetermined number of second data stored and update the storage unit; an arithmetic unit configured to output an addition result of the first data and the latest second data as decoded word information; and a selection unit configured to select a decoded word with the maximum likelihood on the basis of a plurality of the decoded word information.

Abstract: Methods and apparatus for communicating short messages from a first device, e.g., a femto cell device or peer to peer device, over communications resources which are being used by an OFDM macro network, e.g., cellular network, are described. The signal goes on top of, e.g., is transmitted on the same communications resource(s), on which a macro signal, e.g. a downlink signal from a cellular base station, is transmitted. Since the signals are transmitted on the same resources as the signals from the macro base station, they interfere with the macro signal. However, the signals transmitted by the femto cell devices and/or peer to peer devices are designed so that they cause little interference to the macro base station in terms of overall throughput and/or with the macro base station's ability to communicate control and/or pilot information.

Abstract: A method and an apparatus for encoding and decoding in an electronic device are provided. In a decoding method, at least one parity symbol is received. A Cauchy matrix is generated using the at least one parity symbol. A Cauchy submatrix is configured from the Cauchy matrix based on the number of at least one lost data symbol and an inverse matrix of the Cauchy submatrix is calculated. At least one parity symbol corresponding to the at least one lost data symbol is updated. The at least one lost data symbol is recovered using the updated at least one parity symbol.

Abstract: A method and apparatus to perform a soft demapping in a rotated quadrature amplitude modulation (QAM) based communication system is described. The method and the apparatus include pre-processing a symbol based on a priori information and performing a one-dimensional (1D) soft demapping on the pre-processed symbol, continuously.

Abstract: Methods and apparatus are provided for read retry operations with read reference voltages ranked for different page populations of a memory. One method comprises obtaining a plurality of rankings of a plurality of read reference voltages for a plurality of page populations, wherein the rankings are based on a predefined performance metric; and reading a codeword from the memory a plurality of times, wherein each of the read operations uses a different one of the plurality of read reference voltages selected based on the rankings of the plurality of read reference voltages. The performance metric comprises, for example, a bit error rate, a bit polarity disparity, a substantially minimal syndrome weight and/or measures of an average system latency or a tail latency. The ranking is optionally based on a size of the page populations that had each of the ranked read reference voltages. Channel estimation is performed separately for each of the plurality of page populations.

Abstract: The present disclosure presents a method and an apparatus for reducing cyclic redundancy check (CRC) false detections at a user equipment (UE). For example, the method may include receiving a data packet at the UE, determining whether a state metric value for each of a plurality of vector elements of a last path metric vector of the data packet is less than or equal to a first threshold, incrementing a counter when the state metric value of a vector element of the plurality of vector elements is less than or equal to the first threshold, determining whether the counter is lower than a second threshold, and providing the data packet to an upper layer protocol entity of the UE when a CRC pass for the data packet is determined and the counter is lower than the second threshold. As such, reduced CRC false detections at a UE may be achieved.

Abstract: Erasure encoded fragments are originally generated by applying an erasure encoding scheme to a data file. An erasure encoded fragment is subsequently generated directly from previously generated erasure encoded fragments or by reconstructing the original data file and then erasure encoding the reconstructed data file. The integrity or fidelity of such a subsequently generated erasure encoded fragment is verified by newly generating an error detection code, such as but not limited to a checksum, for the subsequently generated erasure encoded fragment, and comparing that subsequently error detection code against an error detection code previously generated for a previous or original version of the erasure encoded fragment. Each error detection code is preferably stored in association with its corresponding erasure encoded fragment and with one or more other erasure encoded fragments. Thus, each error detection code is saved in at least two locations.

Abstract: Disclosed herein is a method and apparatus for hardware-accelerating various data quality checking operations. Incoming data streams can be processed with respect to a plurality of data quality check operations using offload engines (e.g., reconfigurable logic such as field programmable gate arrays (FPGAs)). Accelerated data quality checking can be highly advantageous for use in connection with Extract, Transfer, and Load (ETL) systems.

Abstract: Methods and apparatus are provided for transmitting data in a broadcasting system. Input data is encoded by an encoder. A first demultiplexer generates first transmission symbols using the encoded data. The first transmission symbols are modulated, and the modulated first transmission symbols are transmitted. A second demultiplexer generates second transmission symbols using at least a portion of the encoded data. The second transmission symbols are modulated and the modulated second transmission symbols are transmitted.

Abstract: A method and electronic device for encoding data are provided. The method includes acquiring sets xj (j=1 . . . k) and yi (i=1 . . . p) in generating a Generator Cauchy Matrix, wherein k denotes a number of information symbols, and p denotes a number of parity symbols, generating a matrix A1 using the sets xj and yi, wherein elements of the matrix A1 are obtained by 1 x j + y i and have weight of Galois field, and the matrix A1 has a size of P×K, generating a set K, wherein all elements of the set K are not included in the sets xj and yi, updating the set xj by changing at least one element of the set xj for an element of the set K, updating the set yi by changing at least one element of the set yi for the set K element, generating the Generator Cauchy Matrix using the updated sets xj and yi, and encoding data including the information symbols and parity symbols using the Generator Cauchy Matrix.

Abstract: A method for decoding a headerized sub data set (SDS) according to one embodiment includes decoding a header from a headerized SDS to obtain a SDS. C1 and C2 decoding are performed on the SDS in a number of iterations based on a number of interleaves in each row of the SDS. A number of columns of the SDS are overwritten with successfully decoded C2 codewords. A number of rows of the SDS are overwritten with successfully decoded C1 codewords. A number of C1 and/or C2 codewords of the SDS are erased. Remaining rows and/or columns of the SDS are maintained as uncorrected. The SDS is output when all rows of the SDS include only C1 codewords and all columns of the SDS include only C2 codewords.

Abstract: A method of operating a memory storing data sets, and ECCs for the data sets is provided. The method includes when writing new data in a data set, computing and storing an ECC, if a number of addressable segments storing the new data and data previously programmed in the data set includes at least a predetermined number of addressable segments. The method includes storing indications for whether to enable or disable use of the ECCs, using the ECC and a first additional ECC bit derived from the ECC. The method includes reading from a data set an extended ECC including an ECC and a first additional ECC bit derived from the ECC, and enabling or disabling use of the ECC according to the indications stored for the data set. The method includes enabling use of ECCs for blank data sets, using the indications and a second additional ECC bit.

Abstract: A decoding method, a memory storage device and a memory controlling circuit are provided. The decoding method includes: sending a read command sequence configured to read the memory cells, so as to obtain a plurality of first verification bits; executing a first decoding procedure according to the first verification bits, and determining whether a first valid codeword is generated; if the first valid codeword is not generated, sending another read command sequence configured to obtain a plurality of second verification bits; calculating a total number of the memory cells conforming to a specific condition according to the second verification bits; obtaining a channel reliability message according to the total number; and executing a second decoding procedure according to the channel reliability message. Accordingly, a correcting ability of decoding may be improved.

Abstract: A method of operating a memory controller includes; receiving hard decision data and first soft decision data from a non-volatile memory device, performing a first ECC decoding operation using the hard decision data and the first soft decision data: and then determining a second soft decision read voltage or reclaim operation of the non-volatile memory device based on the number of iteration operation of the first ECC (error correction code).

Abstract: A digital broadcast transmitter includes: a first encoder configured to Forward Error Correction (FEC) encode broadcast service data to add parity data, thereby generating an FEC frame, and divide the FEC frame into a plurality of groups, each of the plurality of groups having a same size; a second encoder configured to encode transmission parameter data; an interleaver configured to interleave data of the plurality of groups; and a transmitting unit configured to transmit the interleaved data and the encoded transmission parameter data, wherein the transmission parameter data include information for identifying a number of the parity data.

Abstract: Systems and methods for encoding and decoding check-irregular non-systematic IRA codes of messages in any communication or electronic system where capacity achieving coding is desired. According to these systems and methods, IRA coding strategies, including ones that employ capacity-approaching non-systematic IRA codes that are irregular and that exhibit a low error floor, are employed. These non-systematic IRA codes are particularly advantageous in scenarios in which up to half of coded bits could be lost due to channel impairments and/or where complementary coded bits are desired to transmit over two or more communications sub-channels. An encoder includes information bit repeaters and encoders, one or more interleavers, check node combiners, a check node by-pass and an accumulator. A decoder includes a demapper, one or more check node processors, an accumulator decoder, a bit decoder, and one or more interleavers/deinterleavers.

Abstract: Systems and methods are provided for using a product code having a first dimension and a second dimension to encode data, decode data, or both. An encoding method includes receiving a portion of user data to be written in the first dimension, and computing first parity symbols with respect to the first dimension for the portion of user data. Partial parity symbols with respect to the second dimension are computed for the portion of user data and are used to obtain second parity symbols for the portion of user data. A decoding method includes decoding a first codeword in the first dimension. When the decoding the first codeword in the first dimension is successful, a target syndrome of a second codeword in the second dimension is computed based on a result of the decoding of the first codeword, wherein the first codeword partially overlaps with the second codeword.

Abstract: Systems and methods for communication using an optical transmission system having optical transmitters and receivers includes performing a low-density parity-check (LDPC) encoding; performing nonbinary pm-ary signaling, where p is a prime larger than 2; taking m p-ary symbols at a time and selecting a point from pm-ary signal constellation; after up-sampling and driving amplification, using coordinates of the pm-ary constellation as input of I/Q modulator x (y); combining two independent pm-ary streams corresponding to x and y-polarization states by a polarization beam combiner (PBS) and transmitting data over the optical transmission system.

Abstract: In one embodiment, a tape drive includes a magnetic head having a plurality of read sensors, each read sensor being configured to read data simultaneously. The tape drive also includes a controller and logic integrated with and/or executable by the controller. The logic is configured to receive encoded data read from a plurality of tracks of a magnetic tape medium simultaneously. The logic is also configured to perform priority-based decoding on the encoded data based on erasure coefficients associated with at least one codeword of the encoded data. In another embodiment, a controller-implemented method includes receiving encoded data read from a plurality of tracks of a magnetic tape medium simultaneously and performing priority-based decoding on the encoded data based on erasure coefficients associated with at least one codeword of the encoded data.

Abstract: A method begins with a computing device of a dispersed storage network (DSN) determining that an encoded data slice of a set of encoded data slices requires rebuilding and sending partial rebuild requests to storage units of the DSN. The method continues with one of the storage units generating a partial rebuilt slice based one or more encoded data slices of the set of encoded data slices stored by the one of the storage units and securing the partial rebuilt slice using a shared secret scheme that is shared among the storage units to produce a secured partial rebuilt slice. The method continues with the computing device receiving a set of secured partial rebuilt slices from the storage units, recovering a set of partial rebuilt slices from the set of secured partial rebuilt slices, and rebuilding the encoded data slice from the set of partial rebuilt slices.

Abstract: A multiple access scheme is described. A first bit stream is scrambled from a first terminal according to a first scrambling signature. A second bit stream is scrambled from a second terminal according to a second scrambling signature, wherein the first bit stream and the second bit stream are encoded using a low rate code. The first scrambling signature and the second scrambling signature are assigned, respectively, to the first terminal and the second terminal to provide a multiple access scheme.

Abstract: A method of operation in a memory controller is disclosed. The method includes generating first error information for a selectively dynamic-bus-inversion (DBI)-encoded data word. The selectively DBI-encoded data word is for transfer to a memory device. Second error information associated with the selectively DBI-encoded data word is received from the memory device. Errors in the data word are detected by comparing the first error information to the second error information. The detecting includes evaluating the DBI-encoding of the selectively DBI-encoded data word.

Abstract: A method and apparatus are provided for adaptive channel code selection according to a non-Gaussianity of a channel in a wireless communication system. A method includes receiving channel feedback information from a receiving node; selecting, based on the channel feedback information, a channel code among a plurality of channels code having different degree distributions of repetition codes; and encoding transmission data based on the selected channel code.

Abstract: Various embodiments of the present invention provide a method and apparatus for parallel data processing. In one embodiment of the present invention, there is provided a method for parallel data processing, comprising: receiving baseband data corresponding to multiple antennas from uplink data; converting the baseband data from time-domain signals to frequency-domain signals; processing the frequency-domain signals at least partially in parallel by multiple processing units in a general-purpose processor so as to restore transmitted code blocks; and constructing transmission block (TB) based on the transmitted code blocks. In one embodiment of the present invention, there is provided an apparatus for parallel data processing. By means of the method and apparatus of the present invention, the parallel data processing capacity of a general-purpose data processor may be used to process, in parallel as much as possible, data in uplink data transmission and further improve the receiver operation efficiency.

Abstract: The present invention relates to a method for transceiving downlink control information in a wireless access system that supports an enhanced physical downlink control channel (e-PDCCH), and to an apparatus for the method. More particularly, the method comprises the steps of: precoding downlink control information using a precoding matrix set in a terminal; and transmitting the precoded downlink control information to the terminal via the e-PDCCH using multiple antennas, wherein the e-PDCCH is multiplexed with a PDSCH in a first slot of a subframe in which the downlink control information is transmitted.

Abstract: A computer implemented method for dynamic data rate adjustment within a cascaded forward error correction FEC for optical communications includes subjecting data communicated over an optical network to a forward error correction in an encoding or decoding of the data, the encoding or decoding employing a codeword, re-encoding part of the codeword for generating a subsequent codeword where an actual code rate is tuned by adjusting a size of data encoded to provide re-encoded data, and dynamically changing the re-encoded data size to achieve cascaded rate adaptive FEC for communication of the data over the optical network.

Abstract: A method of processing broadcast data in a broadcast transmitter. The method can include randomizing broadcast service data, first encoding the randomized broadcast service data to add parity data to the randomized broadcast service data, second encoding the first-encoded broadcast service data at a code rate of D/E (D<E and D and E are integers equal to or greater than 1, respectively), first interleaving the second-encoded broadcast service data, second interleaving the first-interleaved broadcast service data, encoding signaling data for signaling the broadcast service data, third interleaving the encoded signaling data, fourth interleaving the third-interleaved signaling data, and transmitting the second-interleaved broadcast service data and the fourth-interleaved signaling data through a frame. The frame includes known data, and the signaling data includes information for identifying the code rate and information related to the known data.

Abstract: A transmission apparatus includes a mapping unit configured to map a first information associated with detecting an error of a frame into a payload area of the frame; and a transmission unit configured to transmit the frame including the first information and a second information associated with detecting an error of the frame.

Abstract: A system is disclosed for assuring the integrity of file segments. A first server has an associated file repository storing a plurality of files and transfers a file segment on an output upon request. A second server also has an associated file repository and receives and stores the file segment in the associated file repository. The second server identifies if there are additional segments of the same file in the associated file repository and processes the received file segment together with the additional identified file segments to identify the presence of malware. Finally, the second server transfers the received file segment on an output as a scanned file segment only if no malware is identified. A third server has an associated file repository and is configured to receive and store the scanned file segments in the associated file repository and to transfer a received scanned file segment to a client.

Abstract: The failure storage device includes a failure storage control unit configured to, when a failure determination unit detects a failure of a target to be controlled, carry out failure storage processing to select data to be stored depending on failure details of the detected failure and store the selected data in a failure analysis data storage unit and a failure name storage unit as storage means, wherein, in the failure storage processing, when several failures are detected within a prescribed period of time, the failure storage control unit stores failure details of an initial failure in the failure name storage unit, stores data selected in accordance with the failure in the failure analysis data storage unit, and stores only failure details of other failures detected after the initial failure in the failure name storage unit.

Abstract: A method and decoder are provided to decode a Low Density Parity Check codeword. An additional check processor performs hard-decision processing functions on the LDPC codeword in order to avoid running unnecessary decoder iterations. The method comprises: receiving the ECC codeword at a memory, the received ECC codeword comprising ECC data bits, ECC parity bits, and error detection code bits; soft-decision decoding the received ECC codeword at a soft-decision decoder, to update the ECC codeword according to ECC parity check equations; hard-decision processing the received ECC codeword at a check processor, while the soft-decision decoder performs the soft-decision decoding, to verify the ECC data bits using the error detection code bits; terminating the soft-decision decoding when the ECC data bits are verified, regardless of whether the updated ECC codeword satisfies all of the ECC parity check equations; and, outputting the decoded ECC codeword from the memory after termination of the decoding.

Abstract: Disclosed herein is a method of generating a generator matrix for defining how to systematically code source data, the method comprising: determining source nodes for comprising a plurality of sub-stripes of source data, wherein the number of source nodes is K and the number of sub-stripes of source data comprised by each source node is S; determining redundant nodes for comprising a plurality of sub-stripes of coded data, wherein the number of redundant nodes is R and the number of sub-stripes of coded data comprised by each redundant node is S; determining values of a first generator matrix according to a systematic coding technique such that K of the rows of the generator matrix to define how to generate all of the K source nodes as comprising source data and R of the rows of the first generator matrix define how to generate all of the R redundant nodes as comprising combinations of two or more of the source nodes; generating a second generator matrix, with a first dimension (K×S) and a second dimension ((

Abstract: A method for iteratively decoding a word of a correcting code by an iterative decoding algorithm in the course of which, for each bit of said code word, at least one extrinsic information item is generated at each iteration, includes the following steps: an initial step of decoding by means of said iterative decoding algorithm; simultaneously, for each bit of said code word, a step of developing a criterion representing the number of oscillations of at least one extrinsic information item or of one extrinsic information item with regard to another extrinsic information item; if the decoding does not converge; a step of modifying the value of the bit of said code word for which said number of oscillations is highest; and, an additional step of decoding said at least one modified code word by means of said iterative decoding algorithm.

Abstract: In one embodiment, a system includes a controller and logic integrated with and/or executable by the controller. The logic is configured to perform iterative decoding on encoded data to obtain decoded data. At least three decoding operations are performed in the iterative decoding, with the decoding operations being selected from a group consisting of: C1 decoding and C2 decoding. The logic is also configured to perform post-decoding error diagnostics on a first portion of the decoded data in response to not obtaining a valid product codeword in the first portion after the iterative decoding of the encoded data. Other systems, methods, and computer program products for producing post-decoding error signatures are presented in accordance with more embodiments.

Abstract: A non-volatile memory controller for a solid state drive includes a soft-decision LDPC decoder. The soft-decision LDPC decoder includes a probability generation module. A processor reads collected statistics collated from decoded frames and tunes the performance of the soft-decision LDPC decoder performance. Additional parameters may also be taken into account, such as the scramble seed and the type of non-volatile memory. An asymmetry in errors may also be detected and provided to a hard-decision LDPC decoder to adjust its performance.

Abstract: A DTV transmitter includes a pre-processor pre-processing enhanced data, a data formatter generating enhanced data packets including known data, a multiplexer multiplexing the enhanced data packets with main data packets, a data randomizer randomizing the multiplexed data packets, an RS encoder RS-encoding the randomized data packets, and a data interleaver interleaving the RS-coded data packets, where a plurality of known data sequences are included in the interleaved enhanced data packets. Finally, the DTV transmitter further includes an enhanced encoder which codes each block of enhanced data placed between any two of the known data sequences and bypasses the interleaved main data packets.