Look-up Table Encoding Or Decoding Patents (Class 714/759)
  • Patent number: 11924295
    Abstract: A method and system for serving assets is disclosed, comprising receiving an asset request to serve an asset, wherein the asset request originates at an application, and wherein the asset request comprises an advertisement of an asset to be served and a request for the network address of an asset server configured to serve the requested asset. The method further comprises causing a service discovery server to identify an asset server configured to serve the requested asset, and causing the requested asset to be served to the application.
    Type: Grant
    Filed: December 20, 2022
    Date of Patent: March 5, 2024
    Assignee: Palantir Technologies Inc.
    Inventors: Robert Fink, Ashwin Ramaswamy, Benjamin Duffield, Bradley Moylan, Greg DeArment, Jared Newman, Mark Elliot
  • Patent number: 11853325
    Abstract: The systems and methods described here can reduce the storage space required (memory and/or disk) to store certain types of data, provide efficient (fast) creation, modification and retrieval of such data, and support such data within the framework of a multi-version database. In some embodiments, the systems and methods can store each field of a set of records as a vector of values, e.g., a data vector. A set of records can be represented using a vector id vector, or “vid” vector, wherein each element of the vid vector contains a reference to the memory location of a data vector. A header table can store associations between labels and “vid” vectors that pertain to those labels. Identical data vectors can be re-used between different record sets or vid vectors needing that vector, thus saving space.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: December 26, 2023
    Assignee: Kinaxis Inc.
    Inventors: Robert N. Walker, James R. Crozman, Jansen Donald Kray, Mosa To Fung Yeung, James Gordon Dagg
  • Patent number: 11853279
    Abstract: The systems and methods described here can reduce the storage space required (memory and/or disk) to store certain types of data, provide efficient (fast) creation, modification and retrieval of such data, and support such data within the framework of a multi-version database. In some embodiments, the systems and methods can store each field of a set of records as a vector of values, e.g., a data vector. A set of records can be represented using a vector hash vector, or “vhash” vector, wherein each element of the vhash vector contains a unique identifier of a data vector, based on a cryptographic hash of the data vector. A header table can store associations between labels and “vhash” vectors that pertain to those labels. Identical data vectors can be re-used between different record sets or vhash vectors needing that vector, thus saving space.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: December 26, 2023
    Assignee: Kinaxis Inc.
    Inventors: Robert Nigel Walker, Marin Creanga, Dylan Ellicott
  • Patent number: 11823320
    Abstract: In examples, a list of elements may be divided into spans and each span may be allocated a respective memory range for output based on a worst-case compression ratio of a compression algorithm that will be used to compress the span. Worker threads may output compressed versions of the spans to the memory ranges. To ensure placement constraints of a data structure will be satisfied, boundaries of the spans may be adjusted prior to compression. The size allocated to a span (e.g., each span) may be increased (or decreasing) to avoid padding blocks while allowing for the span's compressed data to use a block allocated to an adjacent span. Further aspects of the disclosure provide for compaction of the portions of compressed data in memory in order to free up space which may have been allocated to account for the memory gaps which may result from variable compression ratios.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: November 21, 2023
    Assignee: NVIDIA Corporation
    Inventors: Timo Tapani Viitanen, Tero Tapani Karras, Samuli Laine
  • Patent number: 11797508
    Abstract: Disclosed are methods, systems and non-transitory computer readable memory for geospatial correlation. For instance, a method may include: obtaining a plurality of records, wherein each record has a key value that points to the record in a database, and each of the plurality of records includes at least data for an observation of an entity; and generating an index based on the plurality of records. The generating the index may include: determining a plurality of observations based on the plurality of records, an observation including a device identifier and time-and-geolocation data for a record of the plurality of records; encoding the plurality of observations into a plurality of spacetime hashes; and forming a search data structure of the index for a plurality of key values based on the plurality of spacetime hashes, wherein the search data structure groups subsets of the plurality of spacetime hashes.
    Type: Grant
    Filed: June 2, 2023
    Date of Patent: October 24, 2023
    Assignee: Black Cape Inc.
    Inventors: Abe Usher, Samuel Stowers, Scott Barnes, Stephen Corbo, Scott Fairgrieve
  • Patent number: 11777527
    Abstract: With rapid increase in wired/wireless communication traffic and data storage requirements, the performance of error correction codes and data security solutions is become crucial. Random-like codes can be used in symmetric data encryption, cryptographic hash functions, random number/sequence generators, error correction and detection codes, and other data security applications. The present disclosure provides systems and methods that implement a dynamic permutation based coding approach of input based permutation/remapping/repositioning sequence generation. As the encoding process is defined using input bits, the output of the proposed codes depends on the statistic of input bits rather than any fixed predefined encoding structure. This dynamic encoding method can facilitate to implement strong confusion-diffusion logic and randomness in symmetric cryptography, hash functions, error correction codes, and other data security and authentication areas.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: October 3, 2023
    Inventor: Mahesh Rameshbhai Patel
  • Patent number: 11763840
    Abstract: An information processing device performs control to record deletion information indicating that an object with a designated object ID has been deleted, on a recording medium, in a case where a specific object ID is designated and an instruction to delete the object is input, for a magnetic tape on which an object that includes data and metadata related to the data and that is assigned an object ID as identification information is recorded, the object being assigned an object ID in a case where the object is updated different from an object ID of the object before the update.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: September 19, 2023
    Assignee: FUJIFILM CORPORATION
    Inventors: Michitaka Kondo, Yutaka Oishi, Takashi Miyamoto, Terue Watanabe, Koji Matsumura, Yuko Uno
  • Patent number: 11748190
    Abstract: A cyclic redundancy check, CRC, computation circuit comprising an input for receiving an input stream having an input bit sequence comprising two or more bits at a time aligned to rows of a CRC generator matrix stored in a Look Up Table, LUT; a set of two or more parallel processors configured to perform a CRC computation of the input bit sequence; wherein the LUT comprises a plurality of addresses wherein at least one of the addresses is configured to store two or more rows of the CRC generator matrix; and the set of parallel processors is configured to: combine LUT data with the input stream by using two or more bits of the aligned input stream to mask the two or more rows of the CRC generator matrix stored in the LUT; and combine generated two or more intermediate parity bit sequences into a single parity bit sequence.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: September 5, 2023
    Assignee: Accelercomm Ltd
    Inventors: Robert Maunder, Matthew Brejza
  • Patent number: 11728964
    Abstract: A method begins by a processing module of a storage unit of a storage network identifying a first storage format used to store a plurality of encoded data slices in a first memory of the storage unit and continues with the processing module determining to utilize another storage format for storage of the plurality of encoded data slices. The method then continues, with the storage unit selecting a second storage format for storage of the plurality of encoded data slices and initiating migration of the plurality of encoded data slices from the first storage format to storage using the second storage format. Finally, the method continues with updating a performance metric for at least a portion of the storage network while initiating migrating the plurality of encoded data slices.
    Type: Grant
    Filed: May 16, 2022
    Date of Patent: August 15, 2023
    Assignee: Pure Storage, Inc.
    Inventors: Jason K. Resch, Greg R. Dhuse, Bart R. Cilfone
  • Patent number: 11693983
    Abstract: Commutative coding in a geographically diverse data storage system is disclosed. Commutative coding can achieve a same result as more conventional hierarchical erasure coding of data, but can be more efficient. Commutative coding can employ Galois Field (GF) based bit-matrix operations. The bit-matrix operations can employ a reduced GF order in associated with expanding elements of input matrixes. A reduced GF order can perform matrix operations at a lower complexity, e.g., employing AND operations for a GF(2) in contrast to XOR operations for a GF(2w), where w=4, 8, 16, etc. In an aspect, commutative coding can comprise generating a second-tier coding fragment based on applying a second erasure coding scheme, via bit-matrix operations, to a first-tier encoded fragment, wherein the first-tier encoded fragment is based on an input data fragment and a first erasure coding scheme.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: July 4, 2023
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Mikhail Danilov, Igor Medvedev
  • Patent number: 11677419
    Abstract: A cyclic redundancy check, CRC, decoder circuit having a K-bit input bit sequence, s, comprising information bits and CRC bits; and at least one processor (P) configured to perform a CRC decode computation and configured to: use an inverse of a predefined CRC generator polynomial that encoded the K-bit input bit sequence, s, to produce a data set; compute a CRC syndrome from the data set; and determine whether the CRC syndrome contains any one-valued bits indicative of a CRC error. An LUT stores one or more rows of a CRC generator matrix (G) generated from the inverse of the predefined CRC generator polynomial. A set of mod(?K,P) zero-valued filler bits are appended to an end of the K-bit input bit sequence, wherein an order of the rows in the CRC generator matrix (G) is reversed and aligned with the input bits of the input stream.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: June 13, 2023
    Assignee: Accelercomm Limited
    Inventors: Robert Maunder, Matthew Brejza
  • Patent number: 11663221
    Abstract: A computer-implemented method is for dynamic data minimization of a data set for transfer of the minimized data set from a central instance to outside of the central instance, the data set including a second set of individual attributes. The method includes provisioning a whitelist including a first set of attributes being a subset of a second set of attributes. The minimized data set includes the first set of attributes. The method further includes determining an attribute list including a third set of attributes, the third set of attributes including at least the complement of the first set of attributes in relation to the second set of attributes. The method also includes provisioning the attribute list by the central instance for use outside of the central instance.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: May 30, 2023
    Assignee: SIEMENS HEALTHCARE GMBH
    Inventors: Steffen Fries, Ute Rosenbaum
  • Patent number: 11561997
    Abstract: According to one method, the method comprises: receiving, from a client via a REST API, input in a first format; converting, using predetermined metadata, the input in the first format into input in a second format; sending the input in the second format to a legacy system for performing an operation using the input in the second format; receiving, from the legacy system, output in the second format, wherein the output is based at least in part on the operation performed using the input in the second format; converting, using the predetermined metadata, the output in the second format into output in the first format; and sending, to the client via the REST API, the output in the first format.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: January 24, 2023
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Alain Pigeon, Brian James Dueck, Prakash John Thomas, Deepankar Dey
  • Patent number: 11381260
    Abstract: There is provided a method comprising, at a data receiver, receiving a channel codeword from a data sender over a noisy data channel, generating a plurality of candidate error patterns, the plurality of candidate error patterns comprising a plurality of one-bit error patterns and a plurality of multiple-bit error patterns generated from the plurality of one-bit error patterns, evaluating the plurality of candidate error patterns for codebook membership, based on the channel codeword, and outputting an estimated codeword when a codebook membership constraint is satisfied for a given candidate error pattern.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: July 5, 2022
    Assignee: THE ROYAL INSTITUTION FOR THE ADVANCEMENT OF LEARNING / MCGILL UNIVERSITY
    Inventors: Warren J. Gross, Syed Mohsin Abbas, Thibaud Tonnellier
  • Patent number: 11374594
    Abstract: Apparatus and method for neural network learning to detect and correct quantum errors. For example, one embodiment of an apparatus comprises. For example, one embodiment of an apparatus comprises: a quantum processor comprising one or more data quantum bits (qbits) and one or more ancilla qbits; an error decoder to decode a state of at least one of the ancilla qbits to generate an error syndrome related to one or more qbit errors; a neural network to evaluate the error syndrome and to either identify a known corrective response for correcting the error or to perform unsupervised learning to identify a corrective response to the error syndrome.
    Type: Grant
    Filed: May 5, 2018
    Date of Patent: June 28, 2022
    Assignee: INTEL CORPORATION
    Inventors: Justin Hogaboam, Narayan Srinivasa
  • Patent number: 11341047
    Abstract: A data processing apparatus including a frequency interleaves that includes memory configured to write and read data, and an address generator configured to produce a write address and a read address, and that writes the data to the memory in accordance with the write address and reads out the data from the memory in accordance with the read address, thereby carrying out frequency interleaving. The address generator is configured to produce a first pseudo random bit stream, produce a second pseudo random bit stream, alternately produce a bit as 0 and a bit as 1 as an additional bit added as a most significant bit of the first pseudo random bit stream, and produce the write address or the read address by obtaining an exclusive-OR between the first pseudo random bit stream having the additional bit added as the most significant bit and the second pseudo random bit stream.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: May 24, 2022
    Assignee: SATURN LICENSING LLC
    Inventor: Makiko Yamamoto
  • Patent number: 11269883
    Abstract: Asset data is collected from one or more asset managers and stored in a known asset database. The known asset database enables tracking and maintenance of assets associated with each asset manager. One or more field technicians may also be associated with assets in the known asset database. A field technician is provided with access to a field asset management application on a mobile device, which allows the field technician to provide data associated with asset samples. Asset sample data is then correlated with asset data. Once an asset sample has been correlated with an asset, a field technician or other party is presented with an interface through an asset management application, allowing the party to place one or more requests for tests to be performed on one or more asset samples. Once the one or more tests are performed, test results data is provided.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: March 8, 2022
    Assignee: Scott D. Reed
    Inventor: Scott D. Reed
  • Patent number: 11138152
    Abstract: A computer-implemented method for content-agnostic referencing of a binary data file, the method comprising: pregenerating a table of all permutations of data of a particular length, determining a length of the binary data file, the length comprising the number of bits of the binary data file; chunking the binary data into chunks of data of a smaller length; for each chunk, determining if the chunk is in the pregenerated table, and if so using that chunks index in the pregenerated table, and otherwise chunking the data again until the sub-chunks are located in the pregenerated table, and using the number of chunks and associated indices to indicate the binary data file.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: October 5, 2021
    Assignee: Lognovations Holdings, LLC
    Inventor: Christopher McElveen
  • Patent number: 11106531
    Abstract: A flash memory controller used to access a flash memory includes a read-only memory, a processor, and an error correction code unit. The read-only memory is used to store a code. The processor executes the code to control access to the flash memory. The error correction code unit includes a control module and a decoder. The control module respectively calculates a first correlation between innate bad-column information which records the location of innate bad columns that become damaged after the read-only memory being manufactured and a plurality of trapping sets of a plurality of preset LDPC (low-density parity check) codes and uses the preset LDPC code which has the lowest first correlation as a selected LDPC code. The decoder decodes read information obtained from the flash memory according to the selected LDPC code.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: August 31, 2021
    Assignee: SILICON MOTION, INC.
    Inventor: Shiuan-Hao Kuo
  • Patent number: 11004507
    Abstract: A memory controller may detect degradation in accordance with a bit error rate (BER) of the resistive memory device including memory cells. The memory controller may control the memory cells to be programmed to a first resistance state, read the programmed memory cells, and receive the BER of the memory cells generated during a read operation from the resistive memory device. The memory controller may determine a quantity of program cycles of the memory cells based on the BER. The quantity may be determined based on reference to a lookup table indicating a correlation between the BER and the quantity of program cycles.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: May 11, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Han-sung Joo, Seung-You Baek, Ki-sung Kim
  • Patent number: 10998922
    Abstract: An encoder for encoding source information into an encoded codeword used in a communication channel includes a data input to receive source data, a processor, and a memory to store an encoder program. The encoder program makes the processor to encode the source data into a turbo product coding (TPC) structure, and the TPC structure comprises a data block corresponding to the source data, a first parity block including a first column part, a first corner part and a first bottom part, the first parity block being arranged so as to cover a right end column of the data block, a right bottom corner of the data block and a bottom row of the data block by the first column part, the first corner part and the first bottom part, and a second parity block having a row parity block, a joint parity block and a column parity block.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: May 4, 2021
    Assignee: Mitsubishi Electric Research Laboratories, Inc.
    Inventor: Toshiaki Koike-Akino
  • Patent number: 10956259
    Abstract: The codeword accessing method including: receiving a write data with M message bits; generating parity information with N-M bits based on an error correction algorithm and the M message bits, where N and M are positive integers; transforming the M message bits and the parity information to a scrambled codeword with N bits by a scrambling operation, where the scrambled codeword contains only a part of the M message bits; and writing the scrambled codeword into a memory device.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: March 23, 2021
    Assignee: Winbond Electronics Corp.
    Inventors: Chuen-Der Lien, Ming-Huei Shieh, Chi-Shun Lin
  • Patent number: 10944424
    Abstract: Systems and methods are disclosed for error correction with multiple log likelihood ratio (LLR) lookup tables (LUTs) for a single read, which allows for adaptation to asymmetry in the number of 0 or 1 bit errors without re-read operations. In certain embodiments, an apparatus may comprise a circuit configured to receive a sequence of bit value estimates for data read from a solid state memory during a single read operation, generate a first sequence of LLR values by applying the sequence of bit value estimates to a first LUT, and perform a decoding operation on the first sequence of LLR values. When the first sequence of LLR values fails to decode, the circuit may be configured to generate a second sequence of LLR values by applying the bit value estimates to a second LUT, and perform the decoding operation on the second sequence of LLR values to generate decoded data.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: March 9, 2021
    Assignee: Seagate Technology LLC
    Inventors: Zheng Wang, Ara Patapoutian, Deepak Sridhara
  • Patent number: 10892777
    Abstract: Method and apparatus for decoding error correction code (ECC) code words. Reference voltages are used to extract a selected code word from a communication channel. The selected code word is processed by an ECC decoder, and an initial syndrome weight is determined indicative of unresolved parity errors. A coarse search operates to concurrently adjust, over a first succession of iterations, each of the reference voltages. A subsequent fine search operates, over a second succession of iterations, to individually adjust the reference voltages. Decoding and syndrome weight determination continues over each iteration until a minimum syndrome weight is obtained, after which a user data content of the code word is decoded. The coarse search may transition the decoder from a saturated operational region to a linear operational region. The decoder may be a low density parity check (LDPC) decoder.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: January 12, 2021
    Assignee: Seagate Technology LLC
    Inventors: Zheng Wang, Ara Patapoutian, Ryan James Goss, Antoine Khoueir
  • Patent number: 10879930
    Abstract: A decoding method for a low density parity check (LDPC) code includes: updating a first check node, among a plurality of check nodes, by receiving, by the first check node, a bit decision and an associated first reliability value from each of a subset of variable nodes including a first variable node among a plurality of variable nodes, calculating a syndrome value and a second reliability value of the first check node based on the received bit decisions and first reliability values, and outputting the calculated syndrome value and second reliability value of the first check node to a variable node of the plurality of variable nodes but not of the subset of variable nodes; and updating the first variable node by receiving, by the first variable node, a syndrome value and a second reliability value of a second check node among the plurality of check nodes, and updating the first reliability value of the first variable node based on the syndrome value and the second reliability value of the second check node.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: December 29, 2020
    Assignees: SK hynix Inc., Korea Advanced Institute of Science and Technology
    Inventors: Jeong Seok Ha, Ji Eun Oh, Dae-Sung Kim
  • Patent number: 10879933
    Abstract: A Reed Solomon decoder may include a syndrome calculation (SC) circuit, a key equation solver (KES) circuit, and a Chien search and error evaluation (CSEE) circuit. The SC circuit calculates a syndrome from a codeword. The KES circuit includes a plurality of sub-KES circuit and calculates an error location polynomial and an error evaluation polynomial from the syndrome. The CSEE circuit calculates an error location and an error value from the error location polynomial and the error evaluation polynomial. Each of the plurality of sub-KES circuits, the SC circuit and the CSEE circuit respectively constitute pipeline stages. The Read Solomon decoder may also include a FIFO queue that queues the codeword among a plurality of codewords sequentially received, and an error correction circuit that produces error corrected data using an output from the FIFO queue, the error location, and the error value.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: December 29, 2020
    Assignees: SK hynix Inc., Korea Advanced Institute of Science and Technology
    Inventors: Hyunho Kim, Incheol Park, Wooyoung Kim, Youngook Song, Sanggu Jo
  • Patent number: 10817474
    Abstract: An input file is processed according to hash algorithm that references sets of literals to preceding sets of literals to facilitate copy-offset command generation. Preceding instances are identified by generating a hash of the literal set and looking up a corresponding entry in a hash table. The hash table may be accessed by placing look-up requests in a FIFO buffer. When the FIFO buffer is full, generation of the hash chain is suspended until it is no longer full. When repeated literals are found, generation of the hash chain is likewise suspended. The hash chain is used to generate a command file, such as according to the LZ algorithm. Runs of consecutive literals are replaced by a run-length command. The command file may then be encoded using Huffman encoding.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: October 27, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Alexander Hubris, Yingquan Wu
  • Patent number: 10630316
    Abstract: A method for performing low-density parity check (LDPC) decoding includes: in a first decoder which operates in a first mode, performing a plurality of decoding iterations of a codeword using a first algorithm, including: decoding the codeword to generate first information including a number of failed check nodes; linking the number of failed check nodes to a log-likelihood ratio (LLR) value to generate second information; and performing parity check equations for the codeword at check nodes. When a predetermined number of decoding iterations in the first decoder is reached without the parity check equations being solved, decoding of the codeword using the first decoder is stopped, the codeword is input to a second decoder and decoding of the codeword in the second decoder using a second algorithm and the second information is started.
    Type: Grant
    Filed: November 18, 2018
    Date of Patent: April 21, 2020
    Assignee: Silicon Motion, Inc.
    Inventors: Tsung-Chieh Yang, Jian-Dong Du
  • Patent number: 10581841
    Abstract: An authenticated network in which a physical network including physical nodes with actual physical substances and a logical network including logical nodes without actual substances are uniquely linked to expand public ledger technology, which secures Peer-to-peer (P2P) type communication on a logical network, to a physical network, is provided. The authenticated network includes a private key uniquely linked to a public key. The private key is generated by a key generator and an identification device having physical substance and included in an identification core. The private key is regarded as a physical address of the identification core and is confined in the identification core. The public key is publicized as a logical address of a logical node. The logical node and the physical node are uniquely linked by the public key and the private key. The security of the whole network is thus effectively improved.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: March 3, 2020
    Assignee: Zentel Japan Corporation
    Inventors: Hiroshi Watanabe, Takeshi Hamamoto
  • Patent number: 10547471
    Abstract: Provided is a communication control system in which a control device and one or a plurality of control target devices are connected through a network, wherein at least one of the plurality of control target devices includes a sub master and a sub slave to be synchronously controlled with each other, and the control device includes a storage unit storing each pieces of information on a synchronization period for synchronizing with the control target device, communication periods, and mutual communication control information for mutually communicate in a mutual communication period shorter than the synchronization period, a calculation unit calculating a control command for commanding an operation in synchronization with the control target device for each control target device, and a communication control unit transmitting the control command including the mutual communication control information to the sub master and the sub slave of the at least one control target device.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: January 28, 2020
    Assignee: Kobe Steel, Ltd.
    Inventors: Naoki Kida, Shuichi Inada, Takashi Wada
  • Patent number: 10511665
    Abstract: A distributed storage network (DSN) employs one or more distributed storage task execution (DST EX) units for dispersed storage of encoded data slices. A delete-slice request associated with a first encoded data slice is received at a DST EX unit, the encoded data slice is packed into a common file with other encoded data slices, and the common file is stored in a distributed storage (DS) memory included in the DST EX unit. Each encoded data slice packed into the common file is associated with a file offset within the common file. The DST EX unit identifies a file offset of the first encoded data slice within the common file. The DST EX unit releases the portion of the DS memory associated with the particular file offset within the common file to a file system maintained by the DST EX unit.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: December 17, 2019
    Assignee: PURE STORAGE, INC.
    Inventors: Greg R. Dhuse, Ilya Volvovski, Joseph M. Kaczmarek, Trevor J. Vossberg
  • Patent number: 10375252
    Abstract: A system includes a first device to select and transmit a first code by a transmitter to a remote device; the remote device implements a sequence detector based on the first code; the transmitter in the first device generates a first sequence based on the first code; the sequence detector in the remote device detects the first sequence and activates the mechanism based on the detection; the first device may be a smartphone or a smart watch.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: August 6, 2019
    Assignee: Ternarylogic LLC
    Inventor: Peter Lablans
  • Patent number: 10362111
    Abstract: A method includes receiving, by a storage unit of a set of storage units of a dispersed storage network (DSN) from a computing device of the DSN, a write request of a set of write requests regarding an encoded data slice of a set of encoded data slices. The write request includes a write set information table that includes a listing of which storage unit of the set of storage units is being sent which encoded data slice of the set of encoded data slices for storage therein. The method further includes interpreting the write set information table to determine that a particular encoded data slice assigned to a particular storage unit should be stored by a different storage unit. The method further includes facilitating storing of the particular encoded data slice in the different storage unit.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: July 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Jason K. Resch, Wesley Leggette, Greg Dhuse
  • Patent number: 10291263
    Abstract: A method for identifying log likelihood ratio (LLR) values includes programming codewords into nonvolatile memory devices in response to receiving host-requested write instructions and performing background reads of the programmed codewords in a block at a default threshold voltage, at one or more threshold voltage offset that is less than the default threshold voltage and at one or more threshold voltage offset that is greater than the default threshold voltage. One of the background reads is decoded to identify the stored codeword(s) and a set of LLR values is identified using the stored read results and the identified codeword(s). The process of performing background reads, storing, decoding and identifying is repeated to identify a set of LLR values for each block and further to identify updated sets of LLR values. Host-requested reads are performed and are decoded using LLR values from the updated set of LLR values corresponding to the block that was read.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: May 14, 2019
    Assignee: IP GEM GROUP, LLC
    Inventors: Alessia Marelli, Rino Micheloni
  • Patent number: 10248345
    Abstract: Disclosed herein are methods, systems, and processes to persist data as information. A logical container is created. The logical container is dynamically defined to correspond to a storage device. Original data or encoded data written by an application container is received. If original data is received, encoded data is generated from original data. If encoded data is received, original data is generated from encoded data. Generating encoded data from original data, and original data from encoded data involves calculating original metadata for original data, and encoded metadata for encoded data. Encoded data or original data along with original metadata and encoded metadata is transported through the logical container past a persistence boundary. In response to transporting past the persistence boundary, a confirmation is received original data has been persisted.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: April 2, 2019
    Assignee: Veritas Technologies LLC
    Inventor: Christopher M. Dickson
  • Patent number: 10230401
    Abstract: According to an embodiment, a memory controller for controlling a nonvolatile memory in which multi-dimensional error correction code having two or more component codes is stored, the memory controller configured to read out the multi-dimensional error correction code; acquire a received word of the multi-dimensional error correction code; hold an intermediate decoded word of the multi-dimensional error correction code; perform a first decoding process which is decoding a first component code included in the intermediate decoded word; when a first error symbol included in the first component code is detected by the first decoding process, perform a first rewriting process which is rewriting a value corresponding to the first error symbol in the intermediate decoded word, and record first recurrence information for reproducing a value of the first error symbol before rewriting; perform a second decoding process which is decoding a second component code included in the intermediate decoded word, of which dimens
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: March 12, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Daiki Watanabe, Daisuke Fujiwara, Kosuke Morinaga, Osamu Torii
  • Patent number: 10225046
    Abstract: An adaptive cyclic redundancy check process for uplink control information signaling is provided to allow a number of cyclic redundancy check bits to be adjusted based on the likelihood of data being corrupted during transmission. In an embodiment, a base station device can send a cyclic redundancy check length map to a mobile device that indicates to the mobile device to use a specific number of cyclic redundancy bits to use per a specified payload size of uplink control information. Optionally, the mobile device can determine a number of cyclic redundancy bits to include in the uplink control information, and use two stage uplink control information signaling to indicate to the base station how many cyclic redundancy check bits there are in the succeeding stage.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: March 5, 2019
    Assignee: AT&T INTELLECTUAL PROPERTY I, L.P.
    Inventors: Xiaoyi Wang, SaiRamesh Nammi, Arunabha Ghosh
  • Patent number: 10200065
    Abstract: An apparatus for correcting at least one bit error within a coded bit sequence includes an error syndrome generator and a bit error corrector. The error syndrome generator determines the error syndrome of a coded bit sequence derived by a multiplication of a check matrix with a coded bit sequence.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: February 5, 2019
    Assignee: Infineon Technologies AG
    Inventors: Thomas Kern, Ulrich Backhausen, Michael Goessel, Thomas Rabenalt, Stephane Lacouture
  • Patent number: 10185625
    Abstract: A system and method for data storage by shredding and deshredding of the data allows for various combinations of processing of the data to provide various resultant storage of the data. Data storage and retrieval functions include various combinations of data redundancy generation, data compression and decompression, data encryption and decryption, and data integrity by signature generation and verification. Data shredding is performed by shredders and data deshredding is performed by deshredders that have some implementations that allocate processing internally in the shredder and deshredder either in parallel to multiple processors or sequentially to a single processor. Other implementations use multiple processing through multi-level shredders and deshredders. Redundancy generation includes implementations using non-systematic encoding, systematic encoding, or a hybrid combination.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: January 22, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Douglas R. de la Torre, David W. Young
  • Patent number: 10178038
    Abstract: A system and method for improving the functioning of a data storage array by allowing for dynamically changing a speed of a communications port receiving data from a server via a fiber channel network managed by a network switch. The switch is queried to determine which server is sending data to each port, and to determine the speed and flow rate of the data through each port. The port experiencing the highest speed of data is identified, and if the cache write pending is above a threshold or if the array is otherwise unable to save the data at the speed at which it is being received, then the switch is set to limit the speed through that port, thereby avoiding a backup of data which could cause the port to be taken offline. A record of the change and an alert that the change was made are then generated.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: January 8, 2019
    Assignee: State Farm Mutual Automobile Insurance Company
    Inventor: Brent Carlock
  • Patent number: 10127402
    Abstract: A method begins by combining integrity information and a data segment to produce a data package. The data package is encrypted using a secret key to produce an encrypted data package, which is dispersed storage error encoded using a systematic erasure code, to produce a set of encoded encrypted slices. The secret key is encoded utilizing a secret sharing algorithm to produce a set of secret shares. The set of encoded encrypted slices is sent to a distributed storage network (DSN) memory for storage; and the set of secret shares is sent to the DSN memory for storage.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: November 13, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Jason K. Resch
  • Patent number: 10114580
    Abstract: A computer-executable method, computer program product, and system for managing backups in a distributed data storage system including a first zone, a second zone, and a third zone, the computer-executable method, computer program product, and system comprising processing, at the third zone, a first portion of data of the first zone and a second portion of data of the second zone to create a combined portion of data, and removing the first portion and second portion from the third zone.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: October 30, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Shashwat Srivastav, Sriram Sankaran, Vishrut Shah, Qi Zhang, Jun Luo, Chen Wang, Subba R. Gaddamadugu, Peter M. Musial, Andrew D. Robertson, Huapeng Yuan
  • Patent number: 10108490
    Abstract: A decoding method, a memory storage device and a memory control circuit unit. The method includes: reading a plurality of bits from a plurality of first memory cells; performing a first decoding operation on the bits according to first reliability information; and performing a second decoding operation on the bits according to second reliability information if the first decoding operation fails and meets a default condition, and the second reliability information is different from the first reliability information, and a correction ability of the second reliability information for a first type error of the bits is higher than a correction ability of the first reliability information for the first type error. In addition, the first type error is generated by performing a specific programming operation on the first memory cells based on error data.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: October 23, 2018
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Yu-Hsiang Lin, Shao-Wei Yen, Cheng-Che Yang, Kuo-Hsin Lai
  • Patent number: 10084478
    Abstract: An apparatus and method are provided for generating an error code for a block comprising a plurality of data bits and a plurality of address bits. The apparatus has block generation circuitry to generate a block comprising a plurality of data bits and a plurality of address bits, and error code generation circuitry for receiving that block and a mask array comprising a plurality of mask rows, and for then applying an error code generation algorithm to generate an error code for the block. The error code comprises a plurality of check bits, where each check bit is determined using the block and a corresponding mask row of the mask array. Each mask row comprises a plurality of mask bits, each mask bit being associated with a corresponding bit of the block.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: September 25, 2018
    Assignee: ARM Limited
    Inventor: Kauser Yakub Johar
  • Patent number: 9977713
    Abstract: An operation method for a low density parity check (LDPC) decoder which includes performing an initial update operation to variable nodes by updating a codeword to the variable nodes, performing a decoding operation to the codeword based on an original parity check matrix, generating a modified parity check matrix by changing data of rows of the original parity check matrix corresponding to check nodes with dummy data, performing a node update operation based on the modified parity check matrix and performing a predetermined number of single iterations of the above processes until the decoding operation is successful.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: May 22, 2018
    Assignees: SK Hynix Inc., Korea Advanced Institute of Science and Technology
    Inventors: Soon Young Kang, Jae Kyun Moon
  • Patent number: 9798613
    Abstract: According to one embodiment, a controller includes a decoder, calculation section, table creation, and control section. The decoder converts ECC frames into likelihood information based on a set table, generates decoded ECC frames by decoding using the likelihood information and switches the set table when there is an ECC frame in which the decoding is unsuccessful. The calculation section generates calculation data based on an ECC frame of calculation target among the decoded ECC frames and its ECC frame before decoded. The table creation section sets the new table to the decoder based on the calculation data. The control section controls the calculation target so that a calculation in the calculation section is not repeated for an ECC frame in which the decoding is successful.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: October 24, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masaru Ogawa, Kenji Sakurada
  • Patent number: 9774349
    Abstract: In various embodiments, a system comprising a network interface, a processor, and a non-transient memory medium operatively coupled to the processor is disclosed. The memory medium is configured to store a plurality of instructions configured to program the processor to receive a digital bit stream, transform the digital bit stream to an encoded digital bit stream. The encoded digital bit stream comprises at least one of a gateway channel, a composite channel, or a data channel, and any combination thereof, and provides the encoded digital bit stream to the network interface for transmission. A non-transitory computer-readable memory medium and a computer-implemented method also are disclosed.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: September 26, 2017
    Assignee: AgilePQ, Inc.
    Inventor: Bruce Conway
  • Patent number: 9753667
    Abstract: A high-bandwidth multiple-read memory device includes multiple memory blocks, multiple address input buses, and a number of output data buses. The memory blocks include an auxiliary memory block and each memory block include several memory sub-blocks including an auxiliary memory sub-block. The output data buses output data corresponding to addresses corresponding to the address input buses during a multiple-read operation. The addresses correspond to a single memory sub-block of the memory sub-blocks of a memory block. Also described is differential XOR circuit that includes a selection logic circuit, a precharger circuit, and a multiplexer. The selection logic circuit provides a complementary output signal corresponding to a single-ended input signal. The multiplexer provides, during an evaluate phase, a differential output signal.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: September 5, 2017
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Travis Hebig, Myron Buer, Carl Monzel, Richard John Stephani
  • Patent number: 9684558
    Abstract: A method begins by a processing module forward error correction (FEC) encoding data to produce FEC encoded data and dividing the FEC encoded data into a set of FEC encoded words. The method continues with the processing module generating integrity information based on the data and generating a word name for an FEC encoded word of the set of FEC encoded words. The method continues with the processing module affiliating an address of allocated address space of a dispersed storage memory with the word name and storing the integrity information, the word name, and the address. The method continues with the processing module creating a write command to store the FEC encoded word at the address in the dispersed storage memory.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: June 20, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gary W. Grube, Timothy W. Markison
  • Patent number: 9501349
    Abstract: A method begins with a processing module of a dispersed storage network (DSN) maintaining, over time, a continuum of time-to-repair information regarding a plurality of storage units of the DSN and maintaining, over time, a continuum of time-to-failure information regarding the plurality of storage units. When the continuum of time-to-repair information and the continuum of time-to-failure information are each below undesired levels, the method continues with the processing module changing dispersed storage error encoding parameters of a logical storage vault of the DSN by lowering a decode threshold number with respect to a current decode threshold number and increasing a pillar width number with respect to a current pillar width number. The method continues with the processing module re-encoding stored encoded data of the logical storage vault based on the increased pillar width number and the decreased decode threshold number.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: November 22, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jason K. Resch, S. Christopher Gladwin