Look-up Table Encoding Or Decoding Patents (Class 714/759)
  • Patent number: 10892777
    Abstract: Method and apparatus for decoding error correction code (ECC) code words. Reference voltages are used to extract a selected code word from a communication channel. The selected code word is processed by an ECC decoder, and an initial syndrome weight is determined indicative of unresolved parity errors. A coarse search operates to concurrently adjust, over a first succession of iterations, each of the reference voltages. A subsequent fine search operates, over a second succession of iterations, to individually adjust the reference voltages. Decoding and syndrome weight determination continues over each iteration until a minimum syndrome weight is obtained, after which a user data content of the code word is decoded. The coarse search may transition the decoder from a saturated operational region to a linear operational region. The decoder may be a low density parity check (LDPC) decoder.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: January 12, 2021
    Assignee: Seagate Technology LLC
    Inventors: Zheng Wang, Ara Patapoutian, Ryan James Goss, Antoine Khoueir
  • Patent number: 10879930
    Abstract: A decoding method for a low density parity check (LDPC) code includes: updating a first check node, among a plurality of check nodes, by receiving, by the first check node, a bit decision and an associated first reliability value from each of a subset of variable nodes including a first variable node among a plurality of variable nodes, calculating a syndrome value and a second reliability value of the first check node based on the received bit decisions and first reliability values, and outputting the calculated syndrome value and second reliability value of the first check node to a variable node of the plurality of variable nodes but not of the subset of variable nodes; and updating the first variable node by receiving, by the first variable node, a syndrome value and a second reliability value of a second check node among the plurality of check nodes, and updating the first reliability value of the first variable node based on the syndrome value and the second reliability value of the second check node.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: December 29, 2020
    Assignees: SK hynix Inc., Korea Advanced Institute of Science and Technology
    Inventors: Jeong Seok Ha, Ji Eun Oh, Dae-Sung Kim
  • Patent number: 10879933
    Abstract: A Reed Solomon decoder may include a syndrome calculation (SC) circuit, a key equation solver (KES) circuit, and a Chien search and error evaluation (CSEE) circuit. The SC circuit calculates a syndrome from a codeword. The KES circuit includes a plurality of sub-KES circuit and calculates an error location polynomial and an error evaluation polynomial from the syndrome. The CSEE circuit calculates an error location and an error value from the error location polynomial and the error evaluation polynomial. Each of the plurality of sub-KES circuits, the SC circuit and the CSEE circuit respectively constitute pipeline stages. The Read Solomon decoder may also include a FIFO queue that queues the codeword among a plurality of codewords sequentially received, and an error correction circuit that produces error corrected data using an output from the FIFO queue, the error location, and the error value.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: December 29, 2020
    Assignees: SK hynix Inc., Korea Advanced Institute of Science and Technology
    Inventors: Hyunho Kim, Incheol Park, Wooyoung Kim, Youngook Song, Sanggu Jo
  • Patent number: 10817474
    Abstract: An input file is processed according to hash algorithm that references sets of literals to preceding sets of literals to facilitate copy-offset command generation. Preceding instances are identified by generating a hash of the literal set and looking up a corresponding entry in a hash table. The hash table may be accessed by placing look-up requests in a FIFO buffer. When the FIFO buffer is full, generation of the hash chain is suspended until it is no longer full. When repeated literals are found, generation of the hash chain is likewise suspended. The hash chain is used to generate a command file, such as according to the LZ algorithm. Runs of consecutive literals are replaced by a run-length command. The command file may then be encoded using Huffman encoding.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: October 27, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Alexander Hubris, Yingquan Wu
  • Patent number: 10630316
    Abstract: A method for performing low-density parity check (LDPC) decoding includes: in a first decoder which operates in a first mode, performing a plurality of decoding iterations of a codeword using a first algorithm, including: decoding the codeword to generate first information including a number of failed check nodes; linking the number of failed check nodes to a log-likelihood ratio (LLR) value to generate second information; and performing parity check equations for the codeword at check nodes. When a predetermined number of decoding iterations in the first decoder is reached without the parity check equations being solved, decoding of the codeword using the first decoder is stopped, the codeword is input to a second decoder and decoding of the codeword in the second decoder using a second algorithm and the second information is started.
    Type: Grant
    Filed: November 18, 2018
    Date of Patent: April 21, 2020
    Assignee: Silicon Motion, Inc.
    Inventors: Tsung-Chieh Yang, Jian-Dong Du
  • Patent number: 10581841
    Abstract: An authenticated network in which a physical network including physical nodes with actual physical substances and a logical network including logical nodes without actual substances are uniquely linked to expand public ledger technology, which secures Peer-to-peer (P2P) type communication on a logical network, to a physical network, is provided. The authenticated network includes a private key uniquely linked to a public key. The private key is generated by a key generator and an identification device having physical substance and included in an identification core. The private key is regarded as a physical address of the identification core and is confined in the identification core. The public key is publicized as a logical address of a logical node. The logical node and the physical node are uniquely linked by the public key and the private key. The security of the whole network is thus effectively improved.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: March 3, 2020
    Assignee: Zentel Japan Corporation
    Inventors: Hiroshi Watanabe, Takeshi Hamamoto
  • Patent number: 10547471
    Abstract: Provided is a communication control system in which a control device and one or a plurality of control target devices are connected through a network, wherein at least one of the plurality of control target devices includes a sub master and a sub slave to be synchronously controlled with each other, and the control device includes a storage unit storing each pieces of information on a synchronization period for synchronizing with the control target device, communication periods, and mutual communication control information for mutually communicate in a mutual communication period shorter than the synchronization period, a calculation unit calculating a control command for commanding an operation in synchronization with the control target device for each control target device, and a communication control unit transmitting the control command including the mutual communication control information to the sub master and the sub slave of the at least one control target device.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: January 28, 2020
    Assignee: Kobe Steel, Ltd.
    Inventors: Naoki Kida, Shuichi Inada, Takashi Wada
  • Patent number: 10511665
    Abstract: A distributed storage network (DSN) employs one or more distributed storage task execution (DST EX) units for dispersed storage of encoded data slices. A delete-slice request associated with a first encoded data slice is received at a DST EX unit, the encoded data slice is packed into a common file with other encoded data slices, and the common file is stored in a distributed storage (DS) memory included in the DST EX unit. Each encoded data slice packed into the common file is associated with a file offset within the common file. The DST EX unit identifies a file offset of the first encoded data slice within the common file. The DST EX unit releases the portion of the DS memory associated with the particular file offset within the common file to a file system maintained by the DST EX unit.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: December 17, 2019
    Assignee: PURE STORAGE, INC.
    Inventors: Greg R. Dhuse, Ilya Volvovski, Joseph M. Kaczmarek, Trevor J. Vossberg
  • Patent number: 10375252
    Abstract: A system includes a first device to select and transmit a first code by a transmitter to a remote device; the remote device implements a sequence detector based on the first code; the transmitter in the first device generates a first sequence based on the first code; the sequence detector in the remote device detects the first sequence and activates the mechanism based on the detection; the first device may be a smartphone or a smart watch.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: August 6, 2019
    Assignee: Ternarylogic LLC
    Inventor: Peter Lablans
  • Patent number: 10362111
    Abstract: A method includes receiving, by a storage unit of a set of storage units of a dispersed storage network (DSN) from a computing device of the DSN, a write request of a set of write requests regarding an encoded data slice of a set of encoded data slices. The write request includes a write set information table that includes a listing of which storage unit of the set of storage units is being sent which encoded data slice of the set of encoded data slices for storage therein. The method further includes interpreting the write set information table to determine that a particular encoded data slice assigned to a particular storage unit should be stored by a different storage unit. The method further includes facilitating storing of the particular encoded data slice in the different storage unit.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: July 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Jason K. Resch, Wesley Leggette, Greg Dhuse
  • Patent number: 10291263
    Abstract: A method for identifying log likelihood ratio (LLR) values includes programming codewords into nonvolatile memory devices in response to receiving host-requested write instructions and performing background reads of the programmed codewords in a block at a default threshold voltage, at one or more threshold voltage offset that is less than the default threshold voltage and at one or more threshold voltage offset that is greater than the default threshold voltage. One of the background reads is decoded to identify the stored codeword(s) and a set of LLR values is identified using the stored read results and the identified codeword(s). The process of performing background reads, storing, decoding and identifying is repeated to identify a set of LLR values for each block and further to identify updated sets of LLR values. Host-requested reads are performed and are decoded using LLR values from the updated set of LLR values corresponding to the block that was read.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: May 14, 2019
    Assignee: IP GEM GROUP, LLC
    Inventors: Alessia Marelli, Rino Micheloni
  • Patent number: 10248345
    Abstract: Disclosed herein are methods, systems, and processes to persist data as information. A logical container is created. The logical container is dynamically defined to correspond to a storage device. Original data or encoded data written by an application container is received. If original data is received, encoded data is generated from original data. If encoded data is received, original data is generated from encoded data. Generating encoded data from original data, and original data from encoded data involves calculating original metadata for original data, and encoded metadata for encoded data. Encoded data or original data along with original metadata and encoded metadata is transported through the logical container past a persistence boundary. In response to transporting past the persistence boundary, a confirmation is received original data has been persisted.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: April 2, 2019
    Assignee: Veritas Technologies LLC
    Inventor: Christopher M. Dickson
  • Patent number: 10230401
    Abstract: According to an embodiment, a memory controller for controlling a nonvolatile memory in which multi-dimensional error correction code having two or more component codes is stored, the memory controller configured to read out the multi-dimensional error correction code; acquire a received word of the multi-dimensional error correction code; hold an intermediate decoded word of the multi-dimensional error correction code; perform a first decoding process which is decoding a first component code included in the intermediate decoded word; when a first error symbol included in the first component code is detected by the first decoding process, perform a first rewriting process which is rewriting a value corresponding to the first error symbol in the intermediate decoded word, and record first recurrence information for reproducing a value of the first error symbol before rewriting; perform a second decoding process which is decoding a second component code included in the intermediate decoded word, of which dimens
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: March 12, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Daiki Watanabe, Daisuke Fujiwara, Kosuke Morinaga, Osamu Torii
  • Patent number: 10225046
    Abstract: An adaptive cyclic redundancy check process for uplink control information signaling is provided to allow a number of cyclic redundancy check bits to be adjusted based on the likelihood of data being corrupted during transmission. In an embodiment, a base station device can send a cyclic redundancy check length map to a mobile device that indicates to the mobile device to use a specific number of cyclic redundancy bits to use per a specified payload size of uplink control information. Optionally, the mobile device can determine a number of cyclic redundancy bits to include in the uplink control information, and use two stage uplink control information signaling to indicate to the base station how many cyclic redundancy check bits there are in the succeeding stage.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: March 5, 2019
    Assignee: AT&T INTELLECTUAL PROPERTY I, L.P.
    Inventors: Xiaoyi Wang, SaiRamesh Nammi, Arunabha Ghosh
  • Patent number: 10200065
    Abstract: An apparatus for correcting at least one bit error within a coded bit sequence includes an error syndrome generator and a bit error corrector. The error syndrome generator determines the error syndrome of a coded bit sequence derived by a multiplication of a check matrix with a coded bit sequence.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: February 5, 2019
    Assignee: Infineon Technologies AG
    Inventors: Thomas Kern, Ulrich Backhausen, Michael Goessel, Thomas Rabenalt, Stephane Lacouture
  • Patent number: 10185625
    Abstract: A system and method for data storage by shredding and deshredding of the data allows for various combinations of processing of the data to provide various resultant storage of the data. Data storage and retrieval functions include various combinations of data redundancy generation, data compression and decompression, data encryption and decryption, and data integrity by signature generation and verification. Data shredding is performed by shredders and data deshredding is performed by deshredders that have some implementations that allocate processing internally in the shredder and deshredder either in parallel to multiple processors or sequentially to a single processor. Other implementations use multiple processing through multi-level shredders and deshredders. Redundancy generation includes implementations using non-systematic encoding, systematic encoding, or a hybrid combination.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: January 22, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Douglas R. de la Torre, David W. Young
  • Patent number: 10178038
    Abstract: A system and method for improving the functioning of a data storage array by allowing for dynamically changing a speed of a communications port receiving data from a server via a fiber channel network managed by a network switch. The switch is queried to determine which server is sending data to each port, and to determine the speed and flow rate of the data through each port. The port experiencing the highest speed of data is identified, and if the cache write pending is above a threshold or if the array is otherwise unable to save the data at the speed at which it is being received, then the switch is set to limit the speed through that port, thereby avoiding a backup of data which could cause the port to be taken offline. A record of the change and an alert that the change was made are then generated.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: January 8, 2019
    Assignee: State Farm Mutual Automobile Insurance Company
    Inventor: Brent Carlock
  • Patent number: 10127402
    Abstract: A method begins by combining integrity information and a data segment to produce a data package. The data package is encrypted using a secret key to produce an encrypted data package, which is dispersed storage error encoded using a systematic erasure code, to produce a set of encoded encrypted slices. The secret key is encoded utilizing a secret sharing algorithm to produce a set of secret shares. The set of encoded encrypted slices is sent to a distributed storage network (DSN) memory for storage; and the set of secret shares is sent to the DSN memory for storage.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: November 13, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Jason K. Resch
  • Patent number: 10114580
    Abstract: A computer-executable method, computer program product, and system for managing backups in a distributed data storage system including a first zone, a second zone, and a third zone, the computer-executable method, computer program product, and system comprising processing, at the third zone, a first portion of data of the first zone and a second portion of data of the second zone to create a combined portion of data, and removing the first portion and second portion from the third zone.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: October 30, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Shashwat Srivastav, Sriram Sankaran, Vishrut Shah, Qi Zhang, Jun Luo, Chen Wang, Subba R. Gaddamadugu, Peter M. Musial, Andrew D. Robertson, Huapeng Yuan
  • Patent number: 10108490
    Abstract: A decoding method, a memory storage device and a memory control circuit unit. The method includes: reading a plurality of bits from a plurality of first memory cells; performing a first decoding operation on the bits according to first reliability information; and performing a second decoding operation on the bits according to second reliability information if the first decoding operation fails and meets a default condition, and the second reliability information is different from the first reliability information, and a correction ability of the second reliability information for a first type error of the bits is higher than a correction ability of the first reliability information for the first type error. In addition, the first type error is generated by performing a specific programming operation on the first memory cells based on error data.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: October 23, 2018
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Yu-Hsiang Lin, Shao-Wei Yen, Cheng-Che Yang, Kuo-Hsin Lai
  • Patent number: 10084478
    Abstract: An apparatus and method are provided for generating an error code for a block comprising a plurality of data bits and a plurality of address bits. The apparatus has block generation circuitry to generate a block comprising a plurality of data bits and a plurality of address bits, and error code generation circuitry for receiving that block and a mask array comprising a plurality of mask rows, and for then applying an error code generation algorithm to generate an error code for the block. The error code comprises a plurality of check bits, where each check bit is determined using the block and a corresponding mask row of the mask array. Each mask row comprises a plurality of mask bits, each mask bit being associated with a corresponding bit of the block.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: September 25, 2018
    Assignee: ARM Limited
    Inventor: Kauser Yakub Johar
  • Patent number: 9977713
    Abstract: An operation method for a low density parity check (LDPC) decoder which includes performing an initial update operation to variable nodes by updating a codeword to the variable nodes, performing a decoding operation to the codeword based on an original parity check matrix, generating a modified parity check matrix by changing data of rows of the original parity check matrix corresponding to check nodes with dummy data, performing a node update operation based on the modified parity check matrix and performing a predetermined number of single iterations of the above processes until the decoding operation is successful.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: May 22, 2018
    Assignees: SK Hynix Inc., Korea Advanced Institute of Science and Technology
    Inventors: Soon Young Kang, Jae Kyun Moon
  • Patent number: 9798613
    Abstract: According to one embodiment, a controller includes a decoder, calculation section, table creation, and control section. The decoder converts ECC frames into likelihood information based on a set table, generates decoded ECC frames by decoding using the likelihood information and switches the set table when there is an ECC frame in which the decoding is unsuccessful. The calculation section generates calculation data based on an ECC frame of calculation target among the decoded ECC frames and its ECC frame before decoded. The table creation section sets the new table to the decoder based on the calculation data. The control section controls the calculation target so that a calculation in the calculation section is not repeated for an ECC frame in which the decoding is successful.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: October 24, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masaru Ogawa, Kenji Sakurada
  • Patent number: 9774349
    Abstract: In various embodiments, a system comprising a network interface, a processor, and a non-transient memory medium operatively coupled to the processor is disclosed. The memory medium is configured to store a plurality of instructions configured to program the processor to receive a digital bit stream, transform the digital bit stream to an encoded digital bit stream. The encoded digital bit stream comprises at least one of a gateway channel, a composite channel, or a data channel, and any combination thereof, and provides the encoded digital bit stream to the network interface for transmission. A non-transitory computer-readable memory medium and a computer-implemented method also are disclosed.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: September 26, 2017
    Assignee: AgilePQ, Inc.
    Inventor: Bruce Conway
  • Patent number: 9753667
    Abstract: A high-bandwidth multiple-read memory device includes multiple memory blocks, multiple address input buses, and a number of output data buses. The memory blocks include an auxiliary memory block and each memory block include several memory sub-blocks including an auxiliary memory sub-block. The output data buses output data corresponding to addresses corresponding to the address input buses during a multiple-read operation. The addresses correspond to a single memory sub-block of the memory sub-blocks of a memory block. Also described is differential XOR circuit that includes a selection logic circuit, a precharger circuit, and a multiplexer. The selection logic circuit provides a complementary output signal corresponding to a single-ended input signal. The multiplexer provides, during an evaluate phase, a differential output signal.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: September 5, 2017
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Travis Hebig, Myron Buer, Carl Monzel, Richard John Stephani
  • Patent number: 9684558
    Abstract: A method begins by a processing module forward error correction (FEC) encoding data to produce FEC encoded data and dividing the FEC encoded data into a set of FEC encoded words. The method continues with the processing module generating integrity information based on the data and generating a word name for an FEC encoded word of the set of FEC encoded words. The method continues with the processing module affiliating an address of allocated address space of a dispersed storage memory with the word name and storing the integrity information, the word name, and the address. The method continues with the processing module creating a write command to store the FEC encoded word at the address in the dispersed storage memory.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: June 20, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gary W. Grube, Timothy W. Markison
  • Patent number: 9501349
    Abstract: A method begins with a processing module of a dispersed storage network (DSN) maintaining, over time, a continuum of time-to-repair information regarding a plurality of storage units of the DSN and maintaining, over time, a continuum of time-to-failure information regarding the plurality of storage units. When the continuum of time-to-repair information and the continuum of time-to-failure information are each below undesired levels, the method continues with the processing module changing dispersed storage error encoding parameters of a logical storage vault of the DSN by lowering a decode threshold number with respect to a current decode threshold number and increasing a pillar width number with respect to a current pillar width number. The method continues with the processing module re-encoding stored encoded data of the logical storage vault based on the increased pillar width number and the decreased decode threshold number.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: November 22, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jason K. Resch, S. Christopher Gladwin
  • Patent number: 9386473
    Abstract: Methods and apparatus for feeding back channel quality indication in a communication system. First, a first channel quality indication index is determined in dependence upon a channel quality estimation of a first transmission channel, and a second channel quality indication index is determined in dependence upon a channel quality estimation of a second transmission channel. A differential channel quality indication index of the second channel quality indication index is determined with reference to the first channel quality indication index in dependence upon a differential compression scheme. Then, the first channel quality indication index and the differential channel quality indication index are reported.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: July 5, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: Zhouyue Pi, Jianzhong Zhang, Farooq Khan, Jiannan Tsai
  • Patent number: 9373094
    Abstract: A Dynamic Web Service server may facilitate custom Enterprise Application interface development with little or no developer input by dynamically creating a web service for performing a particular transaction according to a transaction map. An Enterprise Application client device may create a transaction map by “recording” a transaction between an Enterprise Application client and an Enterprise Application server and mapping transaction fields to a custom interface generated to collect data for re-performing the recorded transaction. The Enterprise Application client device may call the dynamic web service, and the Dynamic Web Service server may then perform the recorded transaction using input data collected in the custom interface.
    Type: Grant
    Filed: February 17, 2014
    Date of Patent: June 21, 2016
    Assignee: Winshuttle, LLC
    Inventors: Vishal Chalana, Amit Sharma, Piyush Nagar, Vishal Sharma, Vikram Chalana
  • Patent number: 9336078
    Abstract: Integrated circuits with memory elements may be provided. Integrated circuits may include memory error detection circuitry that is capable of correcting single-bit errors, correcting adjacent double-bit errors, and detecting adjacent triple-bit errors. The memory error detection circuitry may include encoding circuitry that generates parity check bits interleaved among memory data bits. The memory error detection circuitry may include decoding circuitry that is used to generate output data and error signals to indicate whether a correctable soft error or an uncorrectable soft error has been detected. The output data may be written back to the memory elements if a correctable soft error is detected. The memory error detection circuitry may be operable in a pipelined or a non-pipelined mode depending on the desired application.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: May 10, 2016
    Assignee: Altera Corporation
    Inventors: Kostas Pagiamtzis, David Lewis
  • Patent number: 9246516
    Abstract: Techniques for error correction of encoded data are described. In some examples, error correction code (ECC) information for the ECC encoded data is received that indicates the ECC encoded data includes one or more errors. A determination is then made as to whether the ECC encoded data includes a single error, two errors or more than two errors. If the ECC encoded data includes a single error, an error location of the error is identified. If the ECC encoded data includes two errors, first and second error locations are identified. If the ECC encoded data includes more than two errors, separate error locations are identified for the more than two errors. The single error, the two errors or the more than two errors is/are corrected and the ECC encoded data is then be decoded.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: January 26, 2016
    Assignee: INTEL CORPORATION
    Inventor: Zion S. Kwok
  • Patent number: 9203556
    Abstract: In various embodiments, a system comprising a network interface, a processor, and a non-transient memory medium operatively coupled to the processor is disclosed. The memory medium is configured to store a plurality of instructions configured to program the processor to receive a digital bit stream, transform the digital bit stream to an encoded digital bit stream. The encoded digital bit stream comprises at least one of a gateway channel, a composite channel, or a data channel, and any combination thereof, and provides the encoded digital bit stream to the network interface for transmission. A non-transitory computer-readable memory medium and a computer-implemented method also are disclosed.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: December 1, 2015
    Assignee: OPTCTS, INC.
    Inventor: Bruce Conway
  • Patent number: 9172499
    Abstract: In various embodiments, a system comprising a network interface, a processor, and a non-transient memory medium operatively coupled to the processor is disclosed. The memory medium is configured to store a plurality of instructions configured to program the processor to receive a digital bit stream, transform the digital bit stream to an encoded digital bit stream. The encoded digital bit stream comprises at least one of a gateway channel, a composite channel, or a data channel, and any combination thereof, and provides the encoded digital bit stream to the network interface for transmission. A non-transitory computer-readable memory medium and a computer-implemented method also are disclosed.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: October 27, 2015
    Assignee: OPTCTS, INC.
    Inventor: Bruce Conway
  • Patent number: 9166623
    Abstract: A system and method of decoding a Reed-Solomon code using a Reed-Solomon decoder comprising an erasure location selector, multiple syndrome formers and multiple Berlekamp-Massey decoders that share a single error correction unit, and means for selecting a Berlekamp-Massey decoder output as the input to the error correction unit. The method improves the bit error rate performance of the Reed-Solomon decoder compared to known hard-decision and soft-decision Reed-Solomon decoders. The Reed-Solomon decoder also provides hardware area and power savings over more complex Reed-Solomon decoders.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: October 20, 2015
    Assignee: PMC-Sierra US, Inc.
    Inventors: Stephen Bates, Peter Graumann, Phil Northcott
  • Patent number: 9164977
    Abstract: Mechanisms are provided for performing tabular data correction in a document. Tabular data is received and analyzed to identify at least one portion of the tabular data having an erroneous/missing data value. A functional dependency of the at least one portion of the tabular data on one or more other portions of the tabular data is determined. A correct data value for the erroneous or missing data value of the at least one portion of the tabular data is determined based on the functional dependency of the at least one portion. In addition, the tabular data is modified to replace the erroneous or missing data value with the correct data value and thereby generate a modified table data. A processing operation is then performed on the modified table data to generate a resulting output.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: October 20, 2015
    Assignee: International Business Machines Corporation
    Inventors: Donna K. Byron, Scott N. Gerard, Alexander Pikovsky, Timothy P. Winkler
  • Publication number: 20150149856
    Abstract: An apparatus having one or more lookup tables and a decoder is disclosed. The lookup tables are configured to store a plurality of sets of values of log likelihood ratios. The decoder is configured to (i) receive a codeword read from a memory, (ii) receive an initial one of the sets from the lookup tables and (iii) generate read data by decoding the codeword based on the values.
    Type: Application
    Filed: December 20, 2013
    Publication date: May 28, 2015
    Applicant: LSI Corporation
    Inventors: Yunxiang Wu, Zhengang Chen, Erich F. Haratsch
  • Patent number: 9043673
    Abstract: A logical operations functional block for an execution unit of a processor includes a first input data link for a first operand and a second input data link for a second operand. The execution unit includes a register connected to an error correction code detection unit. The logical operations functional block includes a look-up table configured to receive an error correction code syndrome from the error correction code detection unit. The logical operations functional block also includes a multiplexer configured to receive an output signal from the look-up table at a first input and the first operand at a second input, wherein an output of the multiplexer is coupled to the first input data link of a logical functional unit.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: May 26, 2015
    Assignee: International Business Machines Corporation
    Inventors: Markus Kaltenback, Jens Leenstra, Philipp Oehler, Philipp Panitz
  • Patent number: 9032268
    Abstract: A digital broadcast communication system includes an upload system further comprising digital transceivers that upload a plurality of voice sources from any one of announcers, players, referees, coaches, and sportscasters from a broadcast booth utilizing a synchronized multicast communication protocol. At least one access point is configured to communicate with the digital transceivers using synchronized multicast communication protocol. The system utilizes error control coding and decoding that is based upon a quasi-orthogonal maximal sequence code.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: May 12, 2015
    Inventor: Seung Moon Ryu
  • Patent number: 9021331
    Abstract: A method and apparatus for generating soft decision error correction code information. The method includes generating or creating a lookup table (LUT), such as a log likelihood ratio (LLR) lookup table, characterizing a flash memory device. The method also includes loading the lookup table into the SSD controller. The method also includes accessing the lookup table to assign LLR or other characteristic values to the cells of a flash memory device. The method also includes decoding the data in a flash memory device using the soft decision information provided by the lookup table and assigned to the appropriate cells of the flash memory device.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: April 28, 2015
    Assignee: Seagate Technology LLC
    Inventors: Yunxiang Wu, Zhengang Chen, Erich F. Haratsch
  • Patent number: 9014278
    Abstract: A method (800) of performing distributed video encoding on an input video frame (1005), is disclosed. The method (800) forms a bit-stream from original pixel values of the input video frame (1005), such that groups of bits in the bit-stream are associated with clusters of spatial pixel positions in the input video frame (1005). The bit-stream is interleaved to reduce the clustering. The interleaved bit-stream is encoded to generate parity bits from the bit-stream according to a bitwise error correction method.
    Type: Grant
    Filed: October 8, 2008
    Date of Patent: April 21, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Timothy Merrick Long, Axel Lakus-Becker, Ka-Ming Leung
  • Patent number: 9015554
    Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an output signal in response to (i) a value retrieved from a look-up table, and (ii) an index signal. The second circuit may be configured to generate the index signal in response to a plurality of page signals. The apparatus may manage decision patterns during a soft retry.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: April 21, 2015
    Assignee: Seagate Technology LLC
    Inventors: Yunxiang Wu, Ning Chen, Jamal Riani, Hakim Alhussien
  • Patent number: 9015537
    Abstract: According to exemplary embodiments, a system, is provided for bit error rate (BER)-based wear leveling in a solid state drive (SSD). A block-level BER value for a block in the SSD is determined. An adjusted PE cycle count for the block is incremented or decremented based on the block-level BER value. Wear leveling is then performed in the SSD based on the adjusted PE cycle count.
    Type: Grant
    Filed: December 10, 2013
    Date of Patent: April 21, 2015
    Assignee: International Business Machines Corporation
    Inventors: Thomas J. Griffin, Dustin J. Vanstee
  • Patent number: 9009558
    Abstract: A method for channel-coding information bits using a code generation matrix including 32 rows and A columns corresponding to length of the information bits includes, channel-coding the information bits having “A” length using basis sequences having 32-bit length corresponding to columns of the code generation matrix, and outputting the channel-coded result as an output sequence. If “A” is higher than 10, the code generation matrix is generated when (A-10) additional basis sequences were added as column-directional sequences to a first or second matrix. The first matrix is a TFCI code generation matrix composed of 32 rows and 10 columns used for TFCI coding. The second matrix is made when at least one of an inter-row location or an inter-column location of the first matrix was changed. The additional basis sequences satisfy a value 10 of a minimum Hamming distance.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: April 14, 2015
    Assignee: LG Electronics Inc.
    Inventors: Dong Wook Roh, Joon Kui Ahn, Nam Yul Yu, Jung Hyun Cho, Yu Jin Noh, Ki Jun Kim, Dae Won Lee
  • Patent number: 9003259
    Abstract: In one embodiment, a mechanism for interleaved parallel cyclic redundancy check calculation for memory devices is disclosed. In one embodiment, a method includes generating an index value as part of a cyclic redundancy check (CRC) operation, the index value being a result of a first exclusive-or operation applied to both of input data directly as-is from a data bus and to data in a 64-bit accumulator utilized to store results of the CRC operation. The method also includes indexing an interleaved parallel CRC table with the index value to retrieve a 64-bit polynomial entry from the CRC table, performing a second exclusive-or operation on the retrieved polynomial entry and data in the 64-bit accumulator, storing the results of the second exclusive-or operation in the 64-bit accumulator, and transmitting contents of the 64-bit accumulator directly as-is to the data bus.
    Type: Grant
    Filed: November 26, 2008
    Date of Patent: April 7, 2015
    Assignee: Red Hat, Inc.
    Inventor: John F. Cooper
  • Publication number: 20150095739
    Abstract: A method and apparatus that improves the performance of TCP (and other protocols) in a data network by implementing segmenting the TCP path and implementing a proprietary protocol (DPR™) over the network. The DPR™ protocol provides a multiplexed tunnel for a multiplicity of TCP sessions from a client to a cloud proxy. DPR™ implements congestion management, flow control, reliability, and link monitoring. Other network protocols (such as UDP) are supported with a reliability protocol based upon network coding that improves the transmission reliability. A network and a method for transmitting processes in a network are disclosed, using deterministic coefficients for encoding packets based on network coding principles. Disclosed is a method and implementation for using deterministic coefficients for encoding packets based on network coding principles.
    Type: Application
    Filed: November 11, 2014
    Publication date: April 2, 2015
    Inventors: Igor Zhovnirnovsky, Roy Subhash
  • Patent number: 8990668
    Abstract: Embodiments of decoding data stored in solid-state memory arrays are disclosed. In one embodiment, multiple read operations are performed while taking inter-cell interference (ICI) into account. Soft-decision information, such as log-likelihood ratios (LLRs), is determined by using known data and its corresponding multi-read output. Soft-decision information is provided to a detector. Reliability is improved and performance is increased.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: March 24, 2015
    Assignee: Western Digital Technologies, Inc.
    Inventors: Anantha Raman Krishnan, Shayan S. Garani, Kent D. Anderson
  • Publication number: 20150074488
    Abstract: A device comprising a data transfer channel is configured to transfer data between multiple memory devices and a host device. The channel includes multiple decoders and a buffer coupled between the multiple memory devices and the multiple decoders. The buffer is configured to store code words received from the memory devices. Channel control logic is configured to determine availability of one or more of the multiple decoders and to distribute the code words to the one or more decoders based on decoder availability.
    Type: Application
    Filed: September 6, 2013
    Publication date: March 12, 2015
    Applicant: Seagate Technology LLC
    Inventors: Jeffrey John Pream, Ara Patapoutian
  • Publication number: 20150067441
    Abstract: A computing device is provide, configured to compute a function of one or more inputs, the device comprising a storage device storing one or more look-up tables used in the computation of said function, the look-up tables mapping input values to output values, the look-up table being constructed with respect to the first error correcting code, a second error correcting code, a first error threshold and a second error threshold, such that any two input values (112) that each differ at most a first error threshold number of bits from a same code word of the first error correcting code, are mapped to respective output values (131-38) that each differ at most a second error threshold number of bits from a same code word of the second error correcting code, wherein the first error threshold is at least 1 and at most the error correcting capability (t1) of the first error correcting code, and the second error 10 threshold is at most the error correcting capability (t2) of the second error correcting code.
    Type: Application
    Filed: October 21, 2013
    Publication date: March 5, 2015
    Inventors: Paulus Mathias hubertus Mechtildis Antonius Gorissen, Ludovicus Marinus Gerardus Maria Tolhuizer
  • Patent number: 8965776
    Abstract: A system is to receive a word on which to perform error correction; obtain segments, from the word, each segment including a respective subset of samples; update, on a per segment basis, the word based on extrinsic information associated with a previous word; identify sets of least reliable positions (LRPs) associated with the segments; create a subset of LRPs based on a subset of samples within the sets of LRPs; generate candidate words based on the subset of LRPs; identify errors within the word or the candidate words; update, using the extrinsic information, a segment of the word that includes an error; determine distances between the candidate words and the updated word that includes the updated segment; identify best words associated with shortest distances; and perform error correction, on a next word, using other extrinsic information that is based on the best words.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: February 24, 2015
    Assignee: Infinera Corporation
    Inventors: Stanley H. Blakey, Alexander Kaganov, Yuejian Wu, Sandy Thomson
  • Patent number: 8938660
    Abstract: Methods and apparatuses are provided for decoding a codeword using an iterative decoder. The iterative decoder, in a first decoding mode, performs a number of channel iterations on the codeword, determines a first syndrome weight after a first time period, and determines a second syndrome weight after a second time period. Each channel iteration includes an iteration of the channel detector and at least one iteration of the inner iterative decoder. The iterative decoder, in a second decoding mode, determines a true syndrome of the codeword, and processes the codeword based on the true syndrome of the codeword. The codeword is processed using the second decoding mode in response to determining that the first and second determined syndrome weights are less than a syndrome weight threshold.
    Type: Grant
    Filed: October 9, 2012
    Date of Patent: January 20, 2015
    Assignee: Marvell International Ltd.
    Inventors: Nedeljko Varnica, Gregory Burd