Abstract: A cyclic redundancy check, CRC, decoder circuit having a K-bit input bit sequence, s, comprising information bits and CRC bits; and at least one processor (P) configured to perform a CRC decode computation and configured to: use an inverse of a predefined CRC generator polynomial that encoded the K-bit input bit sequence, s, to produce a data set; compute a CRC syndrome from the data set; and determine whether the CRC syndrome contains any one-valued bits indicative of a CRC error. An LUT stores one or more rows of a CRC generator matrix (G) generated from the inverse of the predefined CRC generator polynomial. A set of mod(?K,P) zero-valued filler bits are appended to an end of the K-bit input bit sequence, wherein an order of the rows in the CRC generator matrix (G) is reversed and aligned with the input bits of the input stream.

Abstract: A computer-implemented method is for dynamic data minimization of a data set for transfer of the minimized data set from a central instance to outside of the central instance, the data set including a second set of individual attributes. The method includes provisioning a whitelist including a first set of attributes being a subset of a second set of attributes. The minimized data set includes the first set of attributes. The method further includes determining an attribute list including a third set of attributes, the third set of attributes including at least the complement of the first set of attributes in relation to the second set of attributes. The method also includes provisioning the attribute list by the central instance for use outside of the central instance.

Abstract: According to one method, the method comprises: receiving, from a client via a REST API, input in a first format; converting, using predetermined metadata, the input in the first format into input in a second format; sending the input in the second format to a legacy system for performing an operation using the input in the second format; receiving, from the legacy system, output in the second format, wherein the output is based at least in part on the operation performed using the input in the second format; converting, using the predetermined metadata, the output in the second format into output in the first format; and sending, to the client via the REST API, the output in the first format.

Abstract: There is provided a method comprising, at a data receiver, receiving a channel codeword from a data sender over a noisy data channel, generating a plurality of candidate error patterns, the plurality of candidate error patterns comprising a plurality of one-bit error patterns and a plurality of multiple-bit error patterns generated from the plurality of one-bit error patterns, evaluating the plurality of candidate error patterns for codebook membership, based on the channel codeword, and outputting an estimated codeword when a codebook membership constraint is satisfied for a given candidate error pattern.

Abstract: Apparatus and method for neural network learning to detect and correct quantum errors. For example, one embodiment of an apparatus comprises. For example, one embodiment of an apparatus comprises: a quantum processor comprising one or more data quantum bits (qbits) and one or more ancilla qbits; an error decoder to decode a state of at least one of the ancilla qbits to generate an error syndrome related to one or more qbit errors; a neural network to evaluate the error syndrome and to either identify a known corrective response for correcting the error or to perform unsupervised learning to identify a corrective response to the error syndrome.

Abstract: A data processing apparatus including a frequency interleaves that includes memory configured to write and read data, and an address generator configured to produce a write address and a read address, and that writes the data to the memory in accordance with the write address and reads out the data from the memory in accordance with the read address, thereby carrying out frequency interleaving. The address generator is configured to produce a first pseudo random bit stream, produce a second pseudo random bit stream, alternately produce a bit as 0 and a bit as 1 as an additional bit added as a most significant bit of the first pseudo random bit stream, and produce the write address or the read address by obtaining an exclusive-OR between the first pseudo random bit stream having the additional bit added as the most significant bit and the second pseudo random bit stream.

Abstract: Asset data is collected from one or more asset managers and stored in a known asset database. The known asset database enables tracking and maintenance of assets associated with each asset manager. One or more field technicians may also be associated with assets in the known asset database. A field technician is provided with access to a field asset management application on a mobile device, which allows the field technician to provide data associated with asset samples. Asset sample data is then correlated with asset data. Once an asset sample has been correlated with an asset, a field technician or other party is presented with an interface through an asset management application, allowing the party to place one or more requests for tests to be performed on one or more asset samples. Once the one or more tests are performed, test results data is provided.

Abstract: A computer-implemented method for content-agnostic referencing of a binary data file, the method comprising: pregenerating a table of all permutations of data of a particular length, determining a length of the binary data file, the length comprising the number of bits of the binary data file; chunking the binary data into chunks of data of a smaller length; for each chunk, determining if the chunk is in the pregenerated table, and if so using that chunks index in the pregenerated table, and otherwise chunking the data again until the sub-chunks are located in the pregenerated table, and using the number of chunks and associated indices to indicate the binary data file.

Abstract: A flash memory controller used to access a flash memory includes a read-only memory, a processor, and an error correction code unit. The read-only memory is used to store a code. The processor executes the code to control access to the flash memory. The error correction code unit includes a control module and a decoder. The control module respectively calculates a first correlation between innate bad-column information which records the location of innate bad columns that become damaged after the read-only memory being manufactured and a plurality of trapping sets of a plurality of preset LDPC (low-density parity check) codes and uses the preset LDPC code which has the lowest first correlation as a selected LDPC code. The decoder decodes read information obtained from the flash memory according to the selected LDPC code.

Abstract: A memory controller may detect degradation in accordance with a bit error rate (BER) of the resistive memory device including memory cells. The memory controller may control the memory cells to be programmed to a first resistance state, read the programmed memory cells, and receive the BER of the memory cells generated during a read operation from the resistive memory device. The memory controller may determine a quantity of program cycles of the memory cells based on the BER. The quantity may be determined based on reference to a lookup table indicating a correlation between the BER and the quantity of program cycles.

Abstract: An encoder for encoding source information into an encoded codeword used in a communication channel includes a data input to receive source data, a processor, and a memory to store an encoder program. The encoder program makes the processor to encode the source data into a turbo product coding (TPC) structure, and the TPC structure comprises a data block corresponding to the source data, a first parity block including a first column part, a first corner part and a first bottom part, the first parity block being arranged so as to cover a right end column of the data block, a right bottom corner of the data block and a bottom row of the data block by the first column part, the first corner part and the first bottom part, and a second parity block having a row parity block, a joint parity block and a column parity block.

Abstract: The codeword accessing method including: receiving a write data with M message bits; generating parity information with N-M bits based on an error correction algorithm and the M message bits, where N and M are positive integers; transforming the M message bits and the parity information to a scrambled codeword with N bits by a scrambling operation, where the scrambled codeword contains only a part of the M message bits; and writing the scrambled codeword into a memory device.

Abstract: Systems and methods are disclosed for error correction with multiple log likelihood ratio (LLR) lookup tables (LUTs) for a single read, which allows for adaptation to asymmetry in the number of 0 or 1 bit errors without re-read operations. In certain embodiments, an apparatus may comprise a circuit configured to receive a sequence of bit value estimates for data read from a solid state memory during a single read operation, generate a first sequence of LLR values by applying the sequence of bit value estimates to a first LUT, and perform a decoding operation on the first sequence of LLR values. When the first sequence of LLR values fails to decode, the circuit may be configured to generate a second sequence of LLR values by applying the bit value estimates to a second LUT, and perform the decoding operation on the second sequence of LLR values to generate decoded data.

Abstract: Method and apparatus for decoding error correction code (ECC) code words. Reference voltages are used to extract a selected code word from a communication channel. The selected code word is processed by an ECC decoder, and an initial syndrome weight is determined indicative of unresolved parity errors. A coarse search operates to concurrently adjust, over a first succession of iterations, each of the reference voltages. A subsequent fine search operates, over a second succession of iterations, to individually adjust the reference voltages. Decoding and syndrome weight determination continues over each iteration until a minimum syndrome weight is obtained, after which a user data content of the code word is decoded. The coarse search may transition the decoder from a saturated operational region to a linear operational region. The decoder may be a low density parity check (LDPC) decoder.

Abstract: A Reed Solomon decoder may include a syndrome calculation (SC) circuit, a key equation solver (KES) circuit, and a Chien search and error evaluation (CSEE) circuit. The SC circuit calculates a syndrome from a codeword. The KES circuit includes a plurality of sub-KES circuit and calculates an error location polynomial and an error evaluation polynomial from the syndrome. The CSEE circuit calculates an error location and an error value from the error location polynomial and the error evaluation polynomial. Each of the plurality of sub-KES circuits, the SC circuit and the CSEE circuit respectively constitute pipeline stages. The Read Solomon decoder may also include a FIFO queue that queues the codeword among a plurality of codewords sequentially received, and an error correction circuit that produces error corrected data using an output from the FIFO queue, the error location, and the error value.

Abstract: A decoding method for a low density parity check (LDPC) code includes: updating a first check node, among a plurality of check nodes, by receiving, by the first check node, a bit decision and an associated first reliability value from each of a subset of variable nodes including a first variable node among a plurality of variable nodes, calculating a syndrome value and a second reliability value of the first check node based on the received bit decisions and first reliability values, and outputting the calculated syndrome value and second reliability value of the first check node to a variable node of the plurality of variable nodes but not of the subset of variable nodes; and updating the first variable node by receiving, by the first variable node, a syndrome value and a second reliability value of a second check node among the plurality of check nodes, and updating the first reliability value of the first variable node based on the syndrome value and the second reliability value of the second check node.

Abstract: An input file is processed according to hash algorithm that references sets of literals to preceding sets of literals to facilitate copy-offset command generation. Preceding instances are identified by generating a hash of the literal set and looking up a corresponding entry in a hash table. The hash table may be accessed by placing look-up requests in a FIFO buffer. When the FIFO buffer is full, generation of the hash chain is suspended until it is no longer full. When repeated literals are found, generation of the hash chain is likewise suspended. The hash chain is used to generate a command file, such as according to the LZ algorithm. Runs of consecutive literals are replaced by a run-length command. The command file may then be encoded using Huffman encoding.

Abstract: A method for performing low-density parity check (LDPC) decoding includes: in a first decoder which operates in a first mode, performing a plurality of decoding iterations of a codeword using a first algorithm, including: decoding the codeword to generate first information including a number of failed check nodes; linking the number of failed check nodes to a log-likelihood ratio (LLR) value to generate second information; and performing parity check equations for the codeword at check nodes. When a predetermined number of decoding iterations in the first decoder is reached without the parity check equations being solved, decoding of the codeword using the first decoder is stopped, the codeword is input to a second decoder and decoding of the codeword in the second decoder using a second algorithm and the second information is started.

Abstract: An authenticated network in which a physical network including physical nodes with actual physical substances and a logical network including logical nodes without actual substances are uniquely linked to expand public ledger technology, which secures Peer-to-peer (P2P) type communication on a logical network, to a physical network, is provided. The authenticated network includes a private key uniquely linked to a public key. The private key is generated by a key generator and an identification device having physical substance and included in an identification core. The private key is regarded as a physical address of the identification core and is confined in the identification core. The public key is publicized as a logical address of a logical node. The logical node and the physical node are uniquely linked by the public key and the private key. The security of the whole network is thus effectively improved.

Abstract: Provided is a communication control system in which a control device and one or a plurality of control target devices are connected through a network, wherein at least one of the plurality of control target devices includes a sub master and a sub slave to be synchronously controlled with each other, and the control device includes a storage unit storing each pieces of information on a synchronization period for synchronizing with the control target device, communication periods, and mutual communication control information for mutually communicate in a mutual communication period shorter than the synchronization period, a calculation unit calculating a control command for commanding an operation in synchronization with the control target device for each control target device, and a communication control unit transmitting the control command including the mutual communication control information to the sub master and the sub slave of the at least one control target device.

Abstract: A distributed storage network (DSN) employs one or more distributed storage task execution (DST EX) units for dispersed storage of encoded data slices. A delete-slice request associated with a first encoded data slice is received at a DST EX unit, the encoded data slice is packed into a common file with other encoded data slices, and the common file is stored in a distributed storage (DS) memory included in the DST EX unit. Each encoded data slice packed into the common file is associated with a file offset within the common file. The DST EX unit identifies a file offset of the first encoded data slice within the common file. The DST EX unit releases the portion of the DS memory associated with the particular file offset within the common file to a file system maintained by the DST EX unit.

Abstract: A system includes a first device to select and transmit a first code by a transmitter to a remote device; the remote device implements a sequence detector based on the first code; the transmitter in the first device generates a first sequence based on the first code; the sequence detector in the remote device detects the first sequence and activates the mechanism based on the detection; the first device may be a smartphone or a smart watch.

Abstract: A method includes receiving, by a storage unit of a set of storage units of a dispersed storage network (DSN) from a computing device of the DSN, a write request of a set of write requests regarding an encoded data slice of a set of encoded data slices. The write request includes a write set information table that includes a listing of which storage unit of the set of storage units is being sent which encoded data slice of the set of encoded data slices for storage therein. The method further includes interpreting the write set information table to determine that a particular encoded data slice assigned to a particular storage unit should be stored by a different storage unit. The method further includes facilitating storing of the particular encoded data slice in the different storage unit.

Abstract: A method for identifying log likelihood ratio (LLR) values includes programming codewords into nonvolatile memory devices in response to receiving host-requested write instructions and performing background reads of the programmed codewords in a block at a default threshold voltage, at one or more threshold voltage offset that is less than the default threshold voltage and at one or more threshold voltage offset that is greater than the default threshold voltage. One of the background reads is decoded to identify the stored codeword(s) and a set of LLR values is identified using the stored read results and the identified codeword(s). The process of performing background reads, storing, decoding and identifying is repeated to identify a set of LLR values for each block and further to identify updated sets of LLR values. Host-requested reads are performed and are decoded using LLR values from the updated set of LLR values corresponding to the block that was read.

Abstract: Disclosed herein are methods, systems, and processes to persist data as information. A logical container is created. The logical container is dynamically defined to correspond to a storage device. Original data or encoded data written by an application container is received. If original data is received, encoded data is generated from original data. If encoded data is received, original data is generated from encoded data. Generating encoded data from original data, and original data from encoded data involves calculating original metadata for original data, and encoded metadata for encoded data. Encoded data or original data along with original metadata and encoded metadata is transported through the logical container past a persistence boundary. In response to transporting past the persistence boundary, a confirmation is received original data has been persisted.

Abstract: According to an embodiment, a memory controller for controlling a nonvolatile memory in which multi-dimensional error correction code having two or more component codes is stored, the memory controller configured to read out the multi-dimensional error correction code; acquire a received word of the multi-dimensional error correction code; hold an intermediate decoded word of the multi-dimensional error correction code; perform a first decoding process which is decoding a first component code included in the intermediate decoded word; when a first error symbol included in the first component code is detected by the first decoding process, perform a first rewriting process which is rewriting a value corresponding to the first error symbol in the intermediate decoded word, and record first recurrence information for reproducing a value of the first error symbol before rewriting; perform a second decoding process which is decoding a second component code included in the intermediate decoded word, of which dimens

Abstract: An adaptive cyclic redundancy check process for uplink control information signaling is provided to allow a number of cyclic redundancy check bits to be adjusted based on the likelihood of data being corrupted during transmission. In an embodiment, a base station device can send a cyclic redundancy check length map to a mobile device that indicates to the mobile device to use a specific number of cyclic redundancy bits to use per a specified payload size of uplink control information. Optionally, the mobile device can determine a number of cyclic redundancy bits to include in the uplink control information, and use two stage uplink control information signaling to indicate to the base station how many cyclic redundancy check bits there are in the succeeding stage.

Abstract: An apparatus for correcting at least one bit error within a coded bit sequence includes an error syndrome generator and a bit error corrector. The error syndrome generator determines the error syndrome of a coded bit sequence derived by a multiplication of a check matrix with a coded bit sequence.

Abstract: A system and method for data storage by shredding and deshredding of the data allows for various combinations of processing of the data to provide various resultant storage of the data. Data storage and retrieval functions include various combinations of data redundancy generation, data compression and decompression, data encryption and decryption, and data integrity by signature generation and verification. Data shredding is performed by shredders and data deshredding is performed by deshredders that have some implementations that allocate processing internally in the shredder and deshredder either in parallel to multiple processors or sequentially to a single processor. Other implementations use multiple processing through multi-level shredders and deshredders. Redundancy generation includes implementations using non-systematic encoding, systematic encoding, or a hybrid combination.

Abstract: A system and method for improving the functioning of a data storage array by allowing for dynamically changing a speed of a communications port receiving data from a server via a fiber channel network managed by a network switch. The switch is queried to determine which server is sending data to each port, and to determine the speed and flow rate of the data through each port. The port experiencing the highest speed of data is identified, and if the cache write pending is above a threshold or if the array is otherwise unable to save the data at the speed at which it is being received, then the switch is set to limit the speed through that port, thereby avoiding a backup of data which could cause the port to be taken offline. A record of the change and an alert that the change was made are then generated.

Abstract: A method begins by combining integrity information and a data segment to produce a data package. The data package is encrypted using a secret key to produce an encrypted data package, which is dispersed storage error encoded using a systematic erasure code, to produce a set of encoded encrypted slices. The secret key is encoded utilizing a secret sharing algorithm to produce a set of secret shares. The set of encoded encrypted slices is sent to a distributed storage network (DSN) memory for storage; and the set of secret shares is sent to the DSN memory for storage.

Abstract: A computer-executable method, computer program product, and system for managing backups in a distributed data storage system including a first zone, a second zone, and a third zone, the computer-executable method, computer program product, and system comprising processing, at the third zone, a first portion of data of the first zone and a second portion of data of the second zone to create a combined portion of data, and removing the first portion and second portion from the third zone.

Abstract: A decoding method, a memory storage device and a memory control circuit unit. The method includes: reading a plurality of bits from a plurality of first memory cells; performing a first decoding operation on the bits according to first reliability information; and performing a second decoding operation on the bits according to second reliability information if the first decoding operation fails and meets a default condition, and the second reliability information is different from the first reliability information, and a correction ability of the second reliability information for a first type error of the bits is higher than a correction ability of the first reliability information for the first type error. In addition, the first type error is generated by performing a specific programming operation on the first memory cells based on error data.

Abstract: An apparatus and method are provided for generating an error code for a block comprising a plurality of data bits and a plurality of address bits. The apparatus has block generation circuitry to generate a block comprising a plurality of data bits and a plurality of address bits, and error code generation circuitry for receiving that block and a mask array comprising a plurality of mask rows, and for then applying an error code generation algorithm to generate an error code for the block. The error code comprises a plurality of check bits, where each check bit is determined using the block and a corresponding mask row of the mask array. Each mask row comprises a plurality of mask bits, each mask bit being associated with a corresponding bit of the block.

Abstract: An operation method for a low density parity check (LDPC) decoder which includes performing an initial update operation to variable nodes by updating a codeword to the variable nodes, performing a decoding operation to the codeword based on an original parity check matrix, generating a modified parity check matrix by changing data of rows of the original parity check matrix corresponding to check nodes with dummy data, performing a node update operation based on the modified parity check matrix and performing a predetermined number of single iterations of the above processes until the decoding operation is successful.

Abstract: According to one embodiment, a controller includes a decoder, calculation section, table creation, and control section. The decoder converts ECC frames into likelihood information based on a set table, generates decoded ECC frames by decoding using the likelihood information and switches the set table when there is an ECC frame in which the decoding is unsuccessful. The calculation section generates calculation data based on an ECC frame of calculation target among the decoded ECC frames and its ECC frame before decoded. The table creation section sets the new table to the decoder based on the calculation data. The control section controls the calculation target so that a calculation in the calculation section is not repeated for an ECC frame in which the decoding is successful.

Abstract: In various embodiments, a system comprising a network interface, a processor, and a non-transient memory medium operatively coupled to the processor is disclosed. The memory medium is configured to store a plurality of instructions configured to program the processor to receive a digital bit stream, transform the digital bit stream to an encoded digital bit stream. The encoded digital bit stream comprises at least one of a gateway channel, a composite channel, or a data channel, and any combination thereof, and provides the encoded digital bit stream to the network interface for transmission. A non-transitory computer-readable memory medium and a computer-implemented method also are disclosed.

Abstract: A high-bandwidth multiple-read memory device includes multiple memory blocks, multiple address input buses, and a number of output data buses. The memory blocks include an auxiliary memory block and each memory block include several memory sub-blocks including an auxiliary memory sub-block. The output data buses output data corresponding to addresses corresponding to the address input buses during a multiple-read operation. The addresses correspond to a single memory sub-block of the memory sub-blocks of a memory block. Also described is differential XOR circuit that includes a selection logic circuit, a precharger circuit, and a multiplexer. The selection logic circuit provides a complementary output signal corresponding to a single-ended input signal. The multiplexer provides, during an evaluate phase, a differential output signal.

Abstract: A method begins by a processing module forward error correction (FEC) encoding data to produce FEC encoded data and dividing the FEC encoded data into a set of FEC encoded words. The method continues with the processing module generating integrity information based on the data and generating a word name for an FEC encoded word of the set of FEC encoded words. The method continues with the processing module affiliating an address of allocated address space of a dispersed storage memory with the word name and storing the integrity information, the word name, and the address. The method continues with the processing module creating a write command to store the FEC encoded word at the address in the dispersed storage memory.

Abstract: A method begins with a processing module of a dispersed storage network (DSN) maintaining, over time, a continuum of time-to-repair information regarding a plurality of storage units of the DSN and maintaining, over time, a continuum of time-to-failure information regarding the plurality of storage units. When the continuum of time-to-repair information and the continuum of time-to-failure information are each below undesired levels, the method continues with the processing module changing dispersed storage error encoding parameters of a logical storage vault of the DSN by lowering a decode threshold number with respect to a current decode threshold number and increasing a pillar width number with respect to a current pillar width number. The method continues with the processing module re-encoding stored encoded data of the logical storage vault based on the increased pillar width number and the decreased decode threshold number.

Abstract: Methods and apparatus for feeding back channel quality indication in a communication system. First, a first channel quality indication index is determined in dependence upon a channel quality estimation of a first transmission channel, and a second channel quality indication index is determined in dependence upon a channel quality estimation of a second transmission channel. A differential channel quality indication index of the second channel quality indication index is determined with reference to the first channel quality indication index in dependence upon a differential compression scheme. Then, the first channel quality indication index and the differential channel quality indication index are reported.

Abstract: A Dynamic Web Service server may facilitate custom Enterprise Application interface development with little or no developer input by dynamically creating a web service for performing a particular transaction according to a transaction map. An Enterprise Application client device may create a transaction map by “recording” a transaction between an Enterprise Application client and an Enterprise Application server and mapping transaction fields to a custom interface generated to collect data for re-performing the recorded transaction. The Enterprise Application client device may call the dynamic web service, and the Dynamic Web Service server may then perform the recorded transaction using input data collected in the custom interface.

Abstract: Integrated circuits with memory elements may be provided. Integrated circuits may include memory error detection circuitry that is capable of correcting single-bit errors, correcting adjacent double-bit errors, and detecting adjacent triple-bit errors. The memory error detection circuitry may include encoding circuitry that generates parity check bits interleaved among memory data bits. The memory error detection circuitry may include decoding circuitry that is used to generate output data and error signals to indicate whether a correctable soft error or an uncorrectable soft error has been detected. The output data may be written back to the memory elements if a correctable soft error is detected. The memory error detection circuitry may be operable in a pipelined or a non-pipelined mode depending on the desired application.

Abstract: Techniques for error correction of encoded data are described. In some examples, error correction code (ECC) information for the ECC encoded data is received that indicates the ECC encoded data includes one or more errors. A determination is then made as to whether the ECC encoded data includes a single error, two errors or more than two errors. If the ECC encoded data includes a single error, an error location of the error is identified. If the ECC encoded data includes two errors, first and second error locations are identified. If the ECC encoded data includes more than two errors, separate error locations are identified for the more than two errors. The single error, the two errors or the more than two errors is/are corrected and the ECC encoded data is then be decoded.

Abstract: In various embodiments, a system comprising a network interface, a processor, and a non-transient memory medium operatively coupled to the processor is disclosed. The memory medium is configured to store a plurality of instructions configured to program the processor to receive a digital bit stream, transform the digital bit stream to an encoded digital bit stream. The encoded digital bit stream comprises at least one of a gateway channel, a composite channel, or a data channel, and any combination thereof, and provides the encoded digital bit stream to the network interface for transmission. A non-transitory computer-readable memory medium and a computer-implemented method also are disclosed.

Abstract: In various embodiments, a system comprising a network interface, a processor, and a non-transient memory medium operatively coupled to the processor is disclosed. The memory medium is configured to store a plurality of instructions configured to program the processor to receive a digital bit stream, transform the digital bit stream to an encoded digital bit stream. The encoded digital bit stream comprises at least one of a gateway channel, a composite channel, or a data channel, and any combination thereof, and provides the encoded digital bit stream to the network interface for transmission. A non-transitory computer-readable memory medium and a computer-implemented method also are disclosed.

Abstract: A system and method of decoding a Reed-Solomon code using a Reed-Solomon decoder comprising an erasure location selector, multiple syndrome formers and multiple Berlekamp-Massey decoders that share a single error correction unit, and means for selecting a Berlekamp-Massey decoder output as the input to the error correction unit. The method improves the bit error rate performance of the Reed-Solomon decoder compared to known hard-decision and soft-decision Reed-Solomon decoders. The Reed-Solomon decoder also provides hardware area and power savings over more complex Reed-Solomon decoders.

Abstract: Mechanisms are provided for performing tabular data correction in a document. Tabular data is received and analyzed to identify at least one portion of the tabular data having an erroneous/missing data value. A functional dependency of the at least one portion of the tabular data on one or more other portions of the tabular data is determined. A correct data value for the erroneous or missing data value of the at least one portion of the tabular data is determined based on the functional dependency of the at least one portion. In addition, the tabular data is modified to replace the erroneous or missing data value with the correct data value and thereby generate a modified table data. A processing operation is then performed on the modified table data to generate a resulting output.

Abstract: An apparatus having one or more lookup tables and a decoder is disclosed. The lookup tables are configured to store a plurality of sets of values of log likelihood ratios. The decoder is configured to (i) receive a codeword read from a memory, (ii) receive an initial one of the sets from the lookup tables and (iii) generate read data by decoding the codeword based on the values.

Abstract: A logical operations functional block for an execution unit of a processor includes a first input data link for a first operand and a second input data link for a second operand. The execution unit includes a register connected to an error correction code detection unit. The logical operations functional block includes a look-up table configured to receive an error correction code syndrome from the error correction code detection unit. The logical operations functional block also includes a multiplexer configured to receive an output signal from the look-up table at a first input and the first operand at a second input, wherein an output of the multiplexer is coupled to the first input data link of a logical functional unit.