Abstract: A method begins with a processing module of a dispersed storage network (DSN) maintaining, over time, a continuum of time-to-repair information regarding a plurality of storage units of the DSN and maintaining, over time, a continuum of time-to-failure information regarding the plurality of storage units. When the continuum of time-to-repair information and the continuum of time-to-failure information are each below undesired levels, the method continues with the processing module changing dispersed storage error encoding parameters of a logical storage vault of the DSN by lowering a decode threshold number with respect to a current decode threshold number and increasing a pillar width number with respect to a current pillar width number. The method continues with the processing module re-encoding stored encoded data of the logical storage vault based on the increased pillar width number and the decreased decode threshold number.

Abstract: Methods and apparatus for feeding back channel quality indication in a communication system. First, a first channel quality indication index is determined in dependence upon a channel quality estimation of a first transmission channel, and a second channel quality indication index is determined in dependence upon a channel quality estimation of a second transmission channel. A differential channel quality indication index of the second channel quality indication index is determined with reference to the first channel quality indication index in dependence upon a differential compression scheme. Then, the first channel quality indication index and the differential channel quality indication index are reported.

Abstract: A Dynamic Web Service server may facilitate custom Enterprise Application interface development with little or no developer input by dynamically creating a web service for performing a particular transaction according to a transaction map. An Enterprise Application client device may create a transaction map by “recording” a transaction between an Enterprise Application client and an Enterprise Application server and mapping transaction fields to a custom interface generated to collect data for re-performing the recorded transaction. The Enterprise Application client device may call the dynamic web service, and the Dynamic Web Service server may then perform the recorded transaction using input data collected in the custom interface.

Abstract: Integrated circuits with memory elements may be provided. Integrated circuits may include memory error detection circuitry that is capable of correcting single-bit errors, correcting adjacent double-bit errors, and detecting adjacent triple-bit errors. The memory error detection circuitry may include encoding circuitry that generates parity check bits interleaved among memory data bits. The memory error detection circuitry may include decoding circuitry that is used to generate output data and error signals to indicate whether a correctable soft error or an uncorrectable soft error has been detected. The output data may be written back to the memory elements if a correctable soft error is detected. The memory error detection circuitry may be operable in a pipelined or a non-pipelined mode depending on the desired application.

Abstract: Techniques for error correction of encoded data are described. In some examples, error correction code (ECC) information for the ECC encoded data is received that indicates the ECC encoded data includes one or more errors. A determination is then made as to whether the ECC encoded data includes a single error, two errors or more than two errors. If the ECC encoded data includes a single error, an error location of the error is identified. If the ECC encoded data includes two errors, first and second error locations are identified. If the ECC encoded data includes more than two errors, separate error locations are identified for the more than two errors. The single error, the two errors or the more than two errors is/are corrected and the ECC encoded data is then be decoded.

Abstract: In various embodiments, a system comprising a network interface, a processor, and a non-transient memory medium operatively coupled to the processor is disclosed. The memory medium is configured to store a plurality of instructions configured to program the processor to receive a digital bit stream, transform the digital bit stream to an encoded digital bit stream. The encoded digital bit stream comprises at least one of a gateway channel, a composite channel, or a data channel, and any combination thereof, and provides the encoded digital bit stream to the network interface for transmission. A non-transitory computer-readable memory medium and a computer-implemented method also are disclosed.

Abstract: In various embodiments, a system comprising a network interface, a processor, and a non-transient memory medium operatively coupled to the processor is disclosed. The memory medium is configured to store a plurality of instructions configured to program the processor to receive a digital bit stream, transform the digital bit stream to an encoded digital bit stream. The encoded digital bit stream comprises at least one of a gateway channel, a composite channel, or a data channel, and any combination thereof, and provides the encoded digital bit stream to the network interface for transmission. A non-transitory computer-readable memory medium and a computer-implemented method also are disclosed.

Abstract: A system and method of decoding a Reed-Solomon code using a Reed-Solomon decoder comprising an erasure location selector, multiple syndrome formers and multiple Berlekamp-Massey decoders that share a single error correction unit, and means for selecting a Berlekamp-Massey decoder output as the input to the error correction unit. The method improves the bit error rate performance of the Reed-Solomon decoder compared to known hard-decision and soft-decision Reed-Solomon decoders. The Reed-Solomon decoder also provides hardware area and power savings over more complex Reed-Solomon decoders.

Abstract: Mechanisms are provided for performing tabular data correction in a document. Tabular data is received and analyzed to identify at least one portion of the tabular data having an erroneous/missing data value. A functional dependency of the at least one portion of the tabular data on one or more other portions of the tabular data is determined. A correct data value for the erroneous or missing data value of the at least one portion of the tabular data is determined based on the functional dependency of the at least one portion. In addition, the tabular data is modified to replace the erroneous or missing data value with the correct data value and thereby generate a modified table data. A processing operation is then performed on the modified table data to generate a resulting output.

Abstract: An apparatus having one or more lookup tables and a decoder is disclosed. The lookup tables are configured to store a plurality of sets of values of log likelihood ratios. The decoder is configured to (i) receive a codeword read from a memory, (ii) receive an initial one of the sets from the lookup tables and (iii) generate read data by decoding the codeword based on the values.

Abstract: A logical operations functional block for an execution unit of a processor includes a first input data link for a first operand and a second input data link for a second operand. The execution unit includes a register connected to an error correction code detection unit. The logical operations functional block includes a look-up table configured to receive an error correction code syndrome from the error correction code detection unit. The logical operations functional block also includes a multiplexer configured to receive an output signal from the look-up table at a first input and the first operand at a second input, wherein an output of the multiplexer is coupled to the first input data link of a logical functional unit.

Abstract: A digital broadcast communication system includes an upload system further comprising digital transceivers that upload a plurality of voice sources from any one of announcers, players, referees, coaches, and sportscasters from a broadcast booth utilizing a synchronized multicast communication protocol. At least one access point is configured to communicate with the digital transceivers using synchronized multicast communication protocol. The system utilizes error control coding and decoding that is based upon a quasi-orthogonal maximal sequence code.

Abstract: A method and apparatus for generating soft decision error correction code information. The method includes generating or creating a lookup table (LUT), such as a log likelihood ratio (LLR) lookup table, characterizing a flash memory device. The method also includes loading the lookup table into the SSD controller. The method also includes accessing the lookup table to assign LLR or other characteristic values to the cells of a flash memory device. The method also includes decoding the data in a flash memory device using the soft decision information provided by the lookup table and assigned to the appropriate cells of the flash memory device.

Abstract: A method (800) of performing distributed video encoding on an input video frame (1005), is disclosed. The method (800) forms a bit-stream from original pixel values of the input video frame (1005), such that groups of bits in the bit-stream are associated with clusters of spatial pixel positions in the input video frame (1005). The bit-stream is interleaved to reduce the clustering. The interleaved bit-stream is encoded to generate parity bits from the bit-stream according to a bitwise error correction method.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an output signal in response to (i) a value retrieved from a look-up table, and (ii) an index signal. The second circuit may be configured to generate the index signal in response to a plurality of page signals. The apparatus may manage decision patterns during a soft retry.

Abstract: According to exemplary embodiments, a system, is provided for bit error rate (BER)-based wear leveling in a solid state drive (SSD). A block-level BER value for a block in the SSD is determined. An adjusted PE cycle count for the block is incremented or decremented based on the block-level BER value. Wear leveling is then performed in the SSD based on the adjusted PE cycle count.

Abstract: A method for channel-coding information bits using a code generation matrix including 32 rows and A columns corresponding to length of the information bits includes, channel-coding the information bits having “A” length using basis sequences having 32-bit length corresponding to columns of the code generation matrix, and outputting the channel-coded result as an output sequence. If “A” is higher than 10, the code generation matrix is generated when (A-10) additional basis sequences were added as column-directional sequences to a first or second matrix. The first matrix is a TFCI code generation matrix composed of 32 rows and 10 columns used for TFCI coding. The second matrix is made when at least one of an inter-row location or an inter-column location of the first matrix was changed. The additional basis sequences satisfy a value 10 of a minimum Hamming distance.

Abstract: In one embodiment, a mechanism for interleaved parallel cyclic redundancy check calculation for memory devices is disclosed. In one embodiment, a method includes generating an index value as part of a cyclic redundancy check (CRC) operation, the index value being a result of a first exclusive-or operation applied to both of input data directly as-is from a data bus and to data in a 64-bit accumulator utilized to store results of the CRC operation. The method also includes indexing an interleaved parallel CRC table with the index value to retrieve a 64-bit polynomial entry from the CRC table, performing a second exclusive-or operation on the retrieved polynomial entry and data in the 64-bit accumulator, storing the results of the second exclusive-or operation in the 64-bit accumulator, and transmitting contents of the 64-bit accumulator directly as-is to the data bus.

Abstract: A method and apparatus that improves the performance of TCP (and other protocols) in a data network by implementing segmenting the TCP path and implementing a proprietary protocol (DPR™) over the network. The DPR™ protocol provides a multiplexed tunnel for a multiplicity of TCP sessions from a client to a cloud proxy. DPR™ implements congestion management, flow control, reliability, and link monitoring. Other network protocols (such as UDP) are supported with a reliability protocol based upon network coding that improves the transmission reliability. A network and a method for transmitting processes in a network are disclosed, using deterministic coefficients for encoding packets based on network coding principles. Disclosed is a method and implementation for using deterministic coefficients for encoding packets based on network coding principles.

Abstract: Embodiments of decoding data stored in solid-state memory arrays are disclosed. In one embodiment, multiple read operations are performed while taking inter-cell interference (ICI) into account. Soft-decision information, such as log-likelihood ratios (LLRs), is determined by using known data and its corresponding multi-read output. Soft-decision information is provided to a detector. Reliability is improved and performance is increased.

Abstract: A device comprising a data transfer channel is configured to transfer data between multiple memory devices and a host device. The channel includes multiple decoders and a buffer coupled between the multiple memory devices and the multiple decoders. The buffer is configured to store code words received from the memory devices. Channel control logic is configured to determine availability of one or more of the multiple decoders and to distribute the code words to the one or more decoders based on decoder availability.

Abstract: A computing device is provide, configured to compute a function of one or more inputs, the device comprising a storage device storing one or more look-up tables used in the computation of said function, the look-up tables mapping input values to output values, the look-up table being constructed with respect to the first error correcting code, a second error correcting code, a first error threshold and a second error threshold, such that any two input values (112) that each differ at most a first error threshold number of bits from a same code word of the first error correcting code, are mapped to respective output values (131-38) that each differ at most a second error threshold number of bits from a same code word of the second error correcting code, wherein the first error threshold is at least 1 and at most the error correcting capability (t1) of the first error correcting code, and the second error 10 threshold is at most the error correcting capability (t2) of the second error correcting code.

Abstract: A system is to receive a word on which to perform error correction; obtain segments, from the word, each segment including a respective subset of samples; update, on a per segment basis, the word based on extrinsic information associated with a previous word; identify sets of least reliable positions (LRPs) associated with the segments; create a subset of LRPs based on a subset of samples within the sets of LRPs; generate candidate words based on the subset of LRPs; identify errors within the word or the candidate words; update, using the extrinsic information, a segment of the word that includes an error; determine distances between the candidate words and the updated word that includes the updated segment; identify best words associated with shortest distances; and perform error correction, on a next word, using other extrinsic information that is based on the best words.

Abstract: Methods and apparatuses are provided for decoding a codeword using an iterative decoder. The iterative decoder, in a first decoding mode, performs a number of channel iterations on the codeword, determines a first syndrome weight after a first time period, and determines a second syndrome weight after a second time period. Each channel iteration includes an iteration of the channel detector and at least one iteration of the inner iterative decoder. The iterative decoder, in a second decoding mode, determines a true syndrome of the codeword, and processes the codeword based on the true syndrome of the codeword. The codeword is processed using the second decoding mode in response to determining that the first and second determined syndrome weights are less than a syndrome weight threshold.

Abstract: In one embodiment a data decoding apparatus includes first and second decoding blocks configured to decode codeword bits in a first mode determined by a first probability of non-standard errors and a second mode determined by a second probability of non-standard errors. The apparatus also includes a mode modification logic configured to cause at least one of the first and second decoding blocks to operate in the second mode when the first and second decoding blocks fail to decode the codeword bits in the first mode. In another embodiment, a method includes decoding codeword bits in a first mode determined by a first probability of non-standard errors. When decoding the codeword bits in the first mode fails to decode the codeword bits, the codeword bits are decoded in a second mode determined by a second probability of non-standard errors.

Abstract: Methods and apparatus intelligently switching between line coding schemes based on context. In one exemplary embodiment, an High Definition Multimedia Interface (HDMI) system is configured to transmit control and video data according to an 8B/10B line coding protocol, and data island data according to TERC4 (TMDS (Transition Minimized Differential Signaling) Error Reduction Coding 4-bit). Various elements of the disclosed HDMI devices are configured to determine when a context switch occurs, and thereafter seamlessly transition between the appropriate line code protocol.

Abstract: A communication link analyzer is disclosed for analyzing a communication link. The communication link analyzer may analyze bitstreams that have been FEC encoded and are transmitted according to one or more 10 Gigabit Ethernet standards, 40 Gigabit Ethernet standards, and other such standards. The communication link analyzer may maintain a running count of the errors detected for the bit positions of a 2112-bit FEC-encoded datablock. These errors may include, but are not limited to, baseline wander, deterministic jitter, and predictive-interval errors. When a given error threshold is met or exceeded for one or more received bitstreams, the communication link analyzer may then attempt a diagnosis of the communication link. Using previously provided empirical data, the communication link analyzer may provide a diagnosis of the communication link based on the error type threshold that was met or exceeded and the bit position associated with the error type threshold.

Abstract: A memory system includes data lines, cache lines temporarily storing data of the data lines, an error correction circuit reading the data stored in each of the cache lines, detecting or correcting errors in the read data, calculating error rates according to each type of the detected errors, and accumulating the calculated error rates on previous error rates, an error rate table storing the accumulated error rates, and a line allocator allocating the cache lines corresponding to the data lines by using the error rate table, wherein cache lines whose accumulated error rates are greater than a predetermined value are not allocated.

Abstract: Patterns that might be generated due to a burst error are prepared beforehand. These patterns are formed by shifting all “1”s in an original channel word. A list of these patterns generated as described above is retrieved in parallel with a general conversion table during demodulation. When the demodulation is interrupted due to the burst error, the result of the retrieval of the previous pattern is referred to, and when there is a hit, the error is regarded as the burst error of the original channel word, and the demodulation is continued.

Abstract: A method obtains at least part of a file from a dispersed storage network (DSN) memory, and stores it in a data object cache. When the file is changed, a determination is made about where to store the changed file portions: in the data object cache or in the DSN. The changed file portions, for example a new copy of the part of the file obtained from the DSN, are encoded utilizing an error coding dispersal storage function, and stored in either the data object cache, or in the DSN memory.

Abstract: To produce a memory which resists ion or photon attack, a memory structure is chosen whose memory point behaves asymmetrically with regard to these attacks. It is shown that in this case, it is sufficient to have a reference cell for an identical and periodic storage structure in order to be able to correct all the memory cells assailed by an attack. An error correction efficiency of ½ is thus obtained, with a simple redundancy, whereas the conventional methods make provision, for the same result, to triple the storage, to obtain a less beneficial efficiency of ?.

Abstract: A nonvolatile memory storage controller is provided for delivering log likelihood ratios (LLRs) to a low-density parity check (LDPC) decoder for use in the decoding of an LDPC encoded codeword. The controller includes read circuitry for reading an LDPC encoded codeword stored in a nonvolatile memory storage module using a plurality of soft-decision reference voltages to provide a plurality of soft-decision bits representative of the codeword. The controller further includes a plurality of neighboring cell contribution LLR look-up tables representative of the contribution of the neighboring cells to threshold voltage distribution of the memory storage module. The controller provides the LLRs from the appropriate LLR look-up table to an LDPC decoder for the subsequent decoding of the codeword.

Abstract: According to exemplary embodiments, a system, method, and computer program product are provided for BER-based wear leveling in a SSD. A block-level BER value for a block in the SSD is determined. An adjusted PE cycle count for the block is incremented or decremented based on the block-level BER value. Wear leveling is then performed in the SSD based on the adjusted PE cycle count.

Abstract: Provided is a soft demapping apparatus that may detect a log likelihood ratio (LLR) value of a quadrature amplitude modulation (QAM) signal, using a shifted table scheme, may designate a sub-region of the QAM signal corresponding to bit information that is obtained by decoding the LLR value, and may calculate an LLR value of other bit information included in the designated sub-region.

Abstract: A memory system including a first memory for storing data and an ECC unit for accessing the first memory and for detecting errors in data retrieved from the first memory, and characterised by an error further processing arrangement operable to process errors detected by the ECC unit, the error further processing arrangement including a second memory for recording information relating to the detected errors. Also described is a method of operation in the memory system.

Abstract: Systems and methods are provided for decoding data. A decoder receives a variable node value and reliability data for a variable node, and check node values for check nodes associated with the variable node. Circuitry generates an updated variable node value, based on the received reliability data and the received check node values. The circuitry also generates, for at least one check node, an updated check node value based on the updated variable node value.

Abstract: According to some embodiments, a turbo decoder configured for High-Speed Packet Access (HSPA) and Long Term Evolution (LTE) is provided, comprising: a plurality of maximum a posteriori (MAP) engines; a plurality of extrinsic memory banks accessible by a MAP engine of the plurality of MAP engines; and wherein when the turbo decoder is operating in HSDPA mode the plurality of extrinsic memory banks is configured such that during a first half of a decoding iteration, the MAP engine is able to read a first dataset from and write second dataset to the plurality of extrinsic memory banks in natural row and column order, and during a second half of the decoding iteration, the MAP engine is able to read a third dataset from and write a fourth dataset to the plurality of extrinsic memory banks in a predetermined row and column order in accordance with an interleaver table using a read column buffer and a write column buffer.

Abstract: A QC-LDPC decoding system employing a trapping set look-up table is provided. The entries of the trapping set look-up table may be sorted according to failure frequencies of the trapping sets. The decoder may determine short-cycles associated with dominant trapping sets in order to decode the received codeword. If the iterative decoder of the QC-LDPC decoding system fails to produce a valid codeword, the decoder may compute the syndrome pattern of the processed codeword and search the look-up table for a trapping set class that is responsible for the iterative decoder's failure. If no responsible trapping set is found in the look-up table, the decoder may attempt to decode the received codeword using alternate decoding methods and subsequently determine a trapping set associated with the decoded codeword. If a trapping set is determined, then that trapping set may be added to the look-up table.

Abstract: A channel coding method of variable length information using block code is disclosed. A method for channel-coding information bits using a code generation matrix including 20 rows and A columns corresponding to length of the information bits includes, channel-coding the information bits having “A” length using basis sequences having 20-bit length corresponding to columns of the code generation matrix. If “A” is 10, individual basis sequences of the code generation matrix correspond to column-directional sequences of a specific matrix composed of 20 rows and 10 columns. The specific matrix is made from 20 rows of the (32,10) code matrix used for TFCI coding were selected.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an output signal in response to (i) a value retrieved from a look-up table, and (ii) an index signal. The second circuit may be configured to generate the index signal in response to a plurality of page signals. The apparatus may manage decision patterns during a soft retry.

Abstract: A channel coding method of variable length information using block code is disclosed. A method for channel-coding information bits using a code generation matrix including 32 rows and A columns corresponding to length of the information bits includes channel-coding the information bits having “A” length using basis sequences having 32-bit length corresponding to columns of the code generation matrix, and outputting the channel-coded result as an output sequence. If “A” is higher than 10, the code generation matrix is generated when (A?10) additional basis sequences were added as column-directional sequences to a first or second matrix. The first matrix is a TFCI code generation matrix composed of 32 rows and 10 columns used for TFCI coding. The second matrix is made when at least an inter-row location or an inter-column location of the first matrix was changed. The additional basis sequences satisfy a value 10 of minimum Hamming distance.

Abstract: A channel coding method of variable length information using block code is disclosed. A method for channel-coding information bits using a code generation matrix including 32 rows and A columns corresponding to length of the information bits includes, channel-coding the information bits having “A” length using basis sequences having 32-bit length corresponding to columns of the code generation matrix, and outputting the channel-coded result as an output sequence. If “A” is higher than 10, the code generation matrix is generated when (A?10) additional basis sequences were added as column-directional sequences to a first or second matrix. The first matrix is a TFCI code generation matrix composed of 32 rows and 10 columns used for TFCI coding. The second matrix is made when at least one of an inter-row location or an inter-column location of the first matrix was changed. The additional basis sequences satisfy a value 10 of a minimum Hamming distance.

Abstract: Various embodiments of the present inventions provide a symbol flipping LDPC decoding system. For example, a symbol flipping data processing system is disclosed that includes a low density parity check decoder operable to decode codewords and to identify unsatisfied parity checks, a symbol flipping controller operable to change values of at least one symbol in the codewords based on the unsatisfied parity checks to assist the low density parity check decoder to decode the codewords, a scheduler operable to control a decoding and symbol flipping mode in the low density parity check decoder and the symbol flipping controller, and a hard decision queue operable to store hard decisions for converged codewords from the low density parity check decoder.

Abstract: An approach to reducing interpolation error is described. This approach generally involves using an offset correction table, populated with predetermined offset correction values, to reduce the error introduced by linear interpolation. This approach includes calculating an approximate inverse quantized value. The offset correction table is accessed, and a corrected inverse quantized value is then calculated.

Abstract: In one embodiment, a turbo equalizer has an LDPC decoder, a channel detector, and one or more adjustment blocks for recovering an LDPC codeword from a set of input samples. The decoder attempts to recover the codeword from an initial set of channel soft-output values and generates a set of extrinsic soft-output values, each corresponding to a bit of the codeword. If the decoder converges on a trapping set, then the channel detector performs detection on the set of input samples to generate a set of updated channel soft-output values, using the extrinsic soft-output values to improve the detection. The one or more adjustment blocks adjust at least one of (i) the extrinsic soft-output values before the channel detection and (ii) the updated channel soft-output values. Subsequent decoding is then performed on the updated and possibly-adjusted channel soft-output values to attempt to recover the codeword.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data set quality determination.

Abstract: An error locator unit for correcting two bit error. The error locator unit includes a plurality of operational units, a normalized basis transform unit, and a conversion unit. The plurality of operations units calculates coefficients of the polynomial based on the generated syndromes in a first basis of a Galois Field. Operating on the coefficients produces a root definition value vector in the first basis. The normalized basis transform unit transforms the root definition value vector to a normal basis to produce a plurality of roots. The conversion unit converts the plurality of roots to the first basis. A scaling factor calculated based on the coefficients is applied to the output of the conversion unit to produce a plurality of scaled roots for said polynomial in the first basis. The plurality of scaled roots is added to produce error locations for the polynomial.

Abstract: A log-likelihood ratio (LLR) for a bit bi in a message is determined by generating a first term, including by summing LLRs corresponding to bits in a first codeword having a specified value. The first codeword has a corresponding first message and bit bi of the first message corresponds to a 0. A second term is generated, including by summing LLRs corresponding to bits in a second codeword having the specified value. The second codeword has a corresponding second message and bit bi of the second message corresponds to a 1. The LLR for bit bi in the message is generated based at least in part on the first term and the second term.

Abstract: A method of processing a stream of coded data before decoding comprises a step of detecting missing or erroneous data in the stream of coded data. It comprises a step of generating a series of data ready for decoding formed from the stream of coded data, and a series of additional data supplying information representing the position of the missing or erroneous data detected.

Abstract: Systems and methods for processing and decoding TCM/BCM-coded signal vectors. A multi-dimensional signal vector is received by, for example, a TCM or BCM decoder. The TCM/BCM decoder identifies the closest signal points in the signal constellation set, or “nearest neighbors,” for each dimension of the received signal vector. The TCM/BCM decoder then forms a test set that includes a plurality of multi-dimensional test vectors, where each dimension of each test vector is based on an identified nearest neighbor. In particular, each test point in the test set is based on a different combination of the nearest neighbors. The TCM/BCM decoder can compute branch metrics based on only the test points in the test set, and can make detection decisions using the computed branch metrics.