Abstract: A method includes determining a quantity of errors for a bit string based on a quantity of bits having a logical value of one within the bit string and writing an indication corresponding to the quantity of errors for the bit string to an array of memory cells. The method can further include determining that the quantity of errors for the bit string has reached a threshold quantity of errors and refraining from performing a subsequent operation to determine the quantity of errors for the bit string in response to determining that the quantity of errors for the bit string has reached the threshold quantity of errors.

Abstract: Systems and methods are disclosed for an improved utilization of parity within a data storage device, and manufacturing methods thereof. In some embodiments, a data storage device can implement an improved codeword redundancy process that can be utilized for data storage locations which were not previously scanned for defects. In some embodiments, a data storage device can implement an improved codeword redundancy process to store write data to a data storage location without having to perform a read operation prior to storing the write data to the storage location. The improved codeword redundancy process can include various methods of storing or updating an outer code codeword for the data to be stored.

Abstract: A method for detecting a reading error of a datum in memory. A binary word which is representative of the datum and an error correcting or detecting code is read by: reading a first part of the binary word stored at a first address in a first memory circuit; and reading a second part of the binary word stored at a second address in a second memory circuit. The first and second parts read from the first and second memory circuits, respectively, are concatenated to form a read binary word. The datum is then obtained by removing the error correcting or detecting code from the read binary word. A new error correcting or detecting code is calculated from the obtained datum and compared to the removed error correcting or detecting code to detect error in the obtained datum.

Abstract: Methods, systems, and devices for extended error detection for a memory device are described. For example, during a read operation, the memory device may perform an error detection operation capable of detecting single-bit errors, double-bit errors, and errors that impact more than two bits and indicate the detected error to a host device. The memory device may use parity information to perform an error detection procedure to detect and/or correct errors within data retrieved during the read operation. In some cases, the memory device may associate each bit of the data read during the read operation with two or more bits of parity information. For example, the memory device may use two or more sets of parity bits to detect errors within a matrix of the data. Each set of parity bits may correspond to a dimension of the matrix of data.

Abstract: The present technology relates to an electronic device. According to the present technology, a storage device having an improved operation speed includes a memory device including a plurality of memory areas, a buffer memory configured to store first parity information including a parity for data stored in each of one or more first memory areas among the plurality of memory areas, and a memory controller configured to store second parity information including a parity for data stored in each of one or more second memory areas except for the one or more first memory areas among the plurality of memory areas and control the memory device to store, when a sudden power off occurs, dump parity information including some of the first parity information and the second parity information.

Abstract: A method for execution by a computing device of a dispersed storage network includes obtaining resource information for a subset of storage units of a storage unit pool. W available storage units of the storage unit pool are identified in response to receiving a store data request. W choose S combinations of selecting S number of storage units of the W available storage units are identified. A plurality of rating levels is calculated based on the resource information, where each of the plurality of rating levels are assigned to a corresponding combination of the W choose S combinations. One combination of the W choose S combinations is selected based on the plurality of rating levels. Storage of data of the store data request is facilitated utilizing the S number of storage units of the selected one combination.

Abstract: A method begins by a dispersed storage (DS) processing unit of a dispersed storage network (DSN) generating a hint regarding data stored or to be stored. When the data is to be stored, the DS processing module divides the data into data segments and dispersed storage error encodes a data segment of the data segments to produce a set of encoded data slices. The method continues by the DS processing unit generating a set of hints based on the hint and affiliating the set of hints with the set of encoded data slices to produce a set of affiliated encoded data slices. The method continues by the DS processing unit sending the set of affiliated encoded data slices to a set of storage units of the DSN such that a storage unit of the set of storage units stores an encoded data slice in accordance with a corresponding hint.

Abstract: An active optical cable (AOC) signals to a source that it needs power above a standard voltage, e.g., above five volts, by sending a signal such as a voltage step from one non-zero voltage to a second non-zero voltage or other voltage pattern on a hot plug detect (HPD) pin of a display data channel (DDC). While a legacy source device may not be able to detect this and consequently will operate as usual, a source device programmed according to present principles detects the request for more power represented by the voltage pattern established by the AOC, and in response increases the power (voltage and/or current) on DDC 5V line to the requested level, e.g., 10V at 500 mA.

Abstract: An embodiment of a semiconductor apparatus may include technology to provide information related to one or more parity capabilities of a controller and a persistent storage media in response to an inquiry from a host device, and adjust one or more parameters related to the one or more parity capabilities of the controller and the persistent storage media in response to a request from the host device. Other embodiments are disclosed and claimed.

Abstract: A plurality of communication stations transmit a plurality of modulated signals so that data is efficiently transmitted from a network through negotiation by a communication terminal capable of transmitting and receiving modulated signals of a plurality of wireless communication schemes with a proxy server present on a network. The communication terminal receives a plurality of modulated signals to obtain data. Thus, the efficiency of frequency utilization is improved.

Abstract: A multi-port PUF circuit based on MOSFET current division deviations comprises a reference source, a row decoder, a column decoder, a timing controller and 32 PUF arrays. Each PUF array comprises 512 PUF cells arranged in 128 rows and 4 columns, an arbiter, a 1st inverter, a 2nd inverter, a 3rd inverter, a 4th inverter and eight transmission gates. The reference source is connected to the PUF arrays. The mth output terminal of the row decoder is connected to the mth row selective signal input terminals of the 32 PUF arrays. The jth output terminal of the column decoder is connected to the jth selective signal input terminals of the 32 PUF arrays. The 1st output terminal of the timing controller is connected to the control terminal of the row decoder. The 2nd output terminal of the timing controller is connected to the control terminal of the column decoder. The multi-port PUF circuit has the advantages of small circuit area and low power consumption while ensuring circuit performance.

Abstract: Apparatuses and methods for determining soft data for fractional digit memory cells are provided. One example apparatus can include a controller to determine states of memory cells of a group of memory cells operated as fractional digit memory cells, and determine soft data based, at least partially, on dimensions to which particular memory cells correspond with respect to the group of memory cells, determined states of the memory cells with respect to a state adjacent a state corresponding to a swapping shell, and whether a particular memory cell is a candidate for swapping.

Abstract: A system for an Error Correction Code (“ECC”) decoder includes a first decoder and a second decoder. The first decoder is configured to determine a first estimated number of errors in encoded data received at the first decoder and to compare the first estimated number of errors to a first threshold and a second threshold. The second decoder is configured to receive the encoded data when the first estimated number of errors is below the first threshold and is above a second threshold. When the first estimated number of errors is above the first threshold, the first decoder passes the encoded data out of the ECC. The first decoder has a lower power consumption than the second decoder.

Abstract: According to one embodiment, a memory system comprises a nonvolatile memory, and a memory controller configured to manage a history value about setting of a read voltage in performing reading of data from the nonvolatile memory, in accordance with a first management unit and a second management unit, a size of the second management unit being smaller than a size of the first management unit. A first region of the nonvolatile memory corresponds to the first management unit. A plurality of second regions of the nonvolatile memory each correspond to the second management unit. The first region includes the plurality of second regions.

Abstract: A method begins by a dispersed storage (DS) processing unit of a dispersed storage network (DSN) generating a hint regarding data stored or to be stored. When the data is to be stored, the DS processing module divides the data into data segments and dispersed storage error encodes a data segment of the data segments to produce a set of encoded data slices. The method continues by the DS processing unit generating a set of hints based on the hint and affiliating the set of hints with the set of encoded data slices to produce a set of affiliated encoded data slices. The method continues by the DS processing unit sending the set of affiliated encoded data slices to a set of storage units of the DSN such that a storage unit of the set of storage units stores an encoded data slice in accordance with a corresponding hint.

Abstract: A wireless receiver is disclosed that includes a peak detector coupled to receive a plurality of phases of an input signal, said plurality being substantially in quadrature, and to provide a detector output and a demodulator comprising an analog comparator coupled to receive said detector output and to provide a comparator output.

Abstract: A semiconductor device according to one embodiment includes a unique ID generation circuit configured to generate a unique ID using a memory array including a plurality of complementary cells, each of the complementary cells includes first and second memory cells MC1 and MC2. The unique ID generation circuit uses, when data in the complementary cell read out in a first state in which an initial threshold voltage of the first memory cell MC1 has been virtually offset and data in the complementary cell read out in a second state in which an initial threshold voltage of the second memory cell MC2 has been virtually offset coincide with each other, the data in the complementary cell as the unique ID.

Abstract: Systems and methods for maximizing read performance of error detection code are provided. More particularly, systems and methods for maximizing read performance of Reed Solomon Based code are provided.

Abstract: Early termination of enhanced multimedia broadcast-multicast service (eMBMS) is discussed. Forward error correction (FEC) redundancy data is added to broadcast data, such that if enough of the data symbols are successfully received, the data object may be reassembled before the entire transmission has been received. The aspects involve an application processor and modem processor, which may either be integrated into the same integrated circuit or separate components. The application processor obtains a total number of source symbols and a redundancy level for a data object to be received from the eMBMS, receives the successfully received data symbols from the modem processor, and then determines whether the number of successfully received data symbols exceeds a threshold for reassembling the transmitted data object. If so, then the application processor and/or the modem processor can shut down until the next broadcast.

Abstract: A memory management system and a method of managing a memory device are described. The system includes a memory device with a memory array to store data and associated error correction coding (ECC) bits and an extended correction table. The extended correction table stores error information additional to the ECC bits for one or more of the data in the memory array. The system also includes a controller to control the memory device to write and read the data.

Abstract: Apparatuses and methods for determining soft data for fractional digit memory cells are provided. One example apparatus can include a controller to determine states of memory cells of a group of memory cells operated as fractional digit memory cells, and determine soft data based, at least partially, on dimensions to which particular memory cells correspond with respect to the group of memory cells, determined states of the memory cells with respect to a state adjacent a state corresponding to a swapping shell, and whether a particular memory cell is a candidate for swapping.

Abstract: A method begins by a processing module of a dispersed storage network (DSN) receiving a data object for storage in DSN memory and determining dispersed storage error encoding parameters for encoding the data object to produce a plurality of sets of encoded data slices. The method continues with the processing module determining to use a dual storage path approach for storing the plurality of sets of encoded data slices in first memory type of the DSN memory and in second memory type of the DSN memory. The method continues with the processing module dispersed storage error encoding the data object to produce the plurality of sets of encoded data slices and outputting the plurality of sets of encoded data slices to the first and second memory types of the DSN memory in accordance with the dispersed storage error encoding parameters.

Abstract: The disclosure is related to systems and methods of providing superparity protection to data. A storage device or other processing system, such as a host, may be capable of providing intermediate superparity protection to data. For example, superparity may be determined in response to a command received at a storage device. A superparity can be determined for read data to provide superparity protection to the read data. It may also be determined whether the read data is already protected by a valid superparity.

Abstract: Systems and methods are provided for decoding data. A decoder includes a syndrome memory, a state memory, and decoding circuitry communicatively coupled to the syndrome memory and the state memory. The decoding circuitry retrieves data related to a symbol from the syndrome memory. The decoding circuitry also retrieves data related to the symbol from the state memory. The decoding circuitry processes the data retrieved from the syndrome memory and the data retrieved from the state memory to determine whether to toggle a value of the symbol. The determination is based at least in part on whether the symbol of the data being decoded was previously toggled from an original state.

Abstract: The present invention provides a method and an apparatus for lowering I/O power of a computer system and a computer system. According to an aspect of the present invention, there is provided a method for lowering I/O power of a computer system, comprising: buffering a plurality of ways of data to be sent to a bus; encoding each of the plurality of ways of data buffered from n bits to n+m bits based on an encoding rule, wherein n and m are both an integer larger than or equal to 1, the encoding rule is used to lower code switching frequency; and sending the plurality of ways of data encoded to the bus.

Abstract: An apparatus supporting hybrid quick response (QR) codes may include: a computer chassis; a dynamic display on the exterior of the computer chassis, the dynamic display configured to render dynamic QR code portions; and a static display that includes static QR code portions, where the static display is adapted to the chassis such that the static QR code portions and dynamic QR code portions rendered by the dynamic display comprise a single, hybrid scannable QR code.

Abstract: An apparatus supporting hybrid quick response (QR) codes may include: a computer chassis; a dynamic display on the exterior of the computer chassis, the dynamic display configured to render dynamic QR code portions; and a static display that includes static QR code portions, where the static display is adapted to the chassis such that the static QR code portions and dynamic QR code portions rendered by the dynamic display comprise a single, hybrid scannable QR code.

Abstract: The present inventions are related to systems and methods for iterative data processing scheduling. In one case a data processing system is disclosed that includes a data detector circuit and a data decoder circuit. The data detector circuit is operable to apply a data detection algorithm to a data set to yield a detected output. The data decoder circuit is operable to repeatedly apply a data decoding algorithm to the detected output to yield a decoded output over a number of passes, where the number of passes is within an allowable number of local iterations selected based at least in part on a read gate signal.

Abstract: According to exemplary embodiments, a system, is provided for bit error rate (BER)-based wear leveling in a solid state drive (SSD). A block-level BER value for a block in the SSD is determined. An adjusted PE cycle count for the block is incremented or decremented based on the block-level BER value. Wear leveling is then performed in the SSD based on the adjusted PE cycle count.

Abstract: A method is provided in one example and includes receiving a data stream that includes an error code probability; detecting an error in the data stream; and determining whether to generate an error signal for the error in the data stream based on the error code probability being compared to a threshold value. In more particular embodiments, the error code probability may be based on a total number of network elements that receive the data stream. In addition, more specific methodologies may include generating a number to be used as a basis for the threshold value; and generating the error signal if the error code probability is below the threshold value.

Abstract: This disclosure relates generally to low power data decoding, and more particularly to low power iterative decoders for data encoded with a low-density parity check (LDPC) encoder. Systems and methods are disclosed in which a low-power syndrome check may be performed in the first iteration or part of the first iteration during the process of decoding a LDPC code in an LDPC decoder. Systems and methods are also disclosed in which a control over the precision of messages sent or received and/or a change in the scaling of these messages may be implemented in the LDPC decoder. The low-power techniques described herein may reduce power consumption without a substantial decrease in performance of the applications that make use of LDPC codes or the devices that make use of low-power LDPC decoders.

Abstract: A method and system to improve the performance and/or reliability of a solid-state drive (SSD). In one embodiment of the invention, the SSD has logic to compress a block of data to be stored in the SSD. If it is not possible to compress the block of data below the threshold, the SSD stores the block of data without any compression. If it is possible to compress the block of data below the threshold, the SSD compresses the block of data and stores the compressed data in the SSD. In one embodiment of the invention, the SSD has logic to dynamically adjust or select the strength of the error correcting code of the data that is stored in the SSD. In another embodiment of the invention, the SSD has logic to provide intra-page XOR protection of the data in the page.

Abstract: An apparatus, system, and method are disclosed for providing error correction for a data storage device. A determination module determines an error-correcting code (“ECC”) characteristic of the data storage device. An ECC module validates requested data read from the data storage device using a hardware ECC decoder. In response to the requested data satisfying a correction threshold, a software ECC decoder module validates the data using a software ECC decoder. The software ECC decoder is configured according to the ECC characteristic of the data storage device.

Abstract: By utilizing Reed-Solomon erasure decoding algorithms and techniques, the system is able to perform error detection for the case where the number of bytes received in error exceeds a correcting capability of a decoder. The error detection can be used, for example, to determine whether a codeword is decodable, and whether the retransmission of data is necessary. The retransmission can be accomplished by assembling a message that is sent to another modem requesting retransmission of one or more portions of data, such as one or more codewords.

Abstract: A method may be performed at a data storage device that includes a memory and a controller. The method includes providing user data to a variable-bit error correction coding (ECC) encoder. The ECC encoder generates a first set of parity bits. A first number of parity bits in the first set of parity bits is determined based on stored counts of read errors. The method also includes storing the user data and the first set of parity bits to a memory of the data storage device.

Abstract: To produce a memory which resists ion or photon attack, a memory structure is chosen whose memory point behaves asymmetrically with regard to these attacks. It is shown that in this case, it is sufficient to have a reference cell for an identical and periodic storage structure in order to be able to correct all the memory cells assailed by an attack. An error correction efficiency of ½ is thus obtained, with a simple redundancy, whereas the conventional methods make provision, for the same result, to triple the storage, to obtain a less beneficial efficiency of ?.

Abstract: A semiconductor integrated circuit pertaining to the present invention comprises a plurality of storage elements for storing and holding an input signal, a majority circuit that outputs a result of a majority decision of outputs from the plurality of storage elements; an error detector circuit that detects a mismatch among the outputs of the plurality of storage elements and outputs error signals; and a monitor circuit that monitors the error signals from the error detector circuit, wherein the monitor circuit, based on the error signals, orders a refresh action that rewrites data for rectification to a storage element in which an output mismatch occurs out of the plurality of storage elements and, if rewrite and rectification by the refresh action are unsuccessful, sends a notification to an external unit or process.

Abstract: A plurality of error correction circuits connected in series include a calculator circuit that corrects the codeword when the determination results of a determination circuit indicate that the error correction circuit at the present stage is to correct the codeword, and a determination circuit at a subsequent error correction apparatus determines whether the error correction circuit at the subsequent stage is to correct the codeword when the determination results of the determination circuit indicate that the error correction circuit at the present stage is not to correct the codeword.

Abstract: According to exemplary embodiments, a system, method, and computer program product are provided for BER-based wear leveling in a SSD. A block-level BER value for a block in the SSD is determined. An adjusted PE cycle count for the block is incremented or decremented based on the block-level BER value. Wear leveling is then performed in the SSD based on the adjusted PE cycle count.

Abstract: A method for controlling a message-passing algorithm (MPA) based decoding operation includes: gathering statistics data of syndromes obtained from executed iterations; and selectively adjusting a decoding operation in a next iteration to be executed according to the statistics data. A control apparatus for controlling an MPA based decoder includes an adjusting circuit and a detecting circuit. The detecting circuit is coupled to the adjusting circuit, and used for gathering statistics data of syndromes obtained from executed iterations, and selectively controlling the adjusting circuit to adjust a decoding operation in a next iteration to be executed according to the statistics data.

Abstract: A decoding device includes: a determination unit that determines whether or not a decoding ending condition is satisfied at an interval shorter than an interval of one decoding process in repeated decoding and ends the process in the middle of the one decoding process in a case where the decoding ending condition is satisfied.

Abstract: An integrated circuit may have an array of memory elements. Each memory element may have multiple memory cells. Each memory element may have a voting circuit that receives signals from the memory cells in that memory element. The voting circuit can produce an output based on the signals. The signals stored by the memory cells of each memory element may be redundant so that the voting circuit can produce an accurate output even in the event that a radiation strike causes some of the memory cells to flip their states to erroneous values. The memory elements may be based on memory cells such as static random-access memory cells and thyristor-based cells.

Abstract: Data words from a parallel communication channel are interleaved to two majority vote blocks that operate out of phase, using a divided clock signal that has half the clock frequency of the clock signal associated with the parallel communication channel. As one majority vote block evaluates a data word and outputs a result, the other majority vote block is in pre-charge mode awaiting the next data for evaluation.

Abstract: A plurality of interpolated samples is generated. Using a plurality of soft-decision detectors, error correction decoding is performed on the plurality of interpolated samples in order to obtain a plurality of decisions. From the plurality of decisions, one is selected by determining which of the plurality of soft-decision detectors are able to come to a decision during error correction decoding. It is determined whether a majority of the detectors that are able to come to a decision come to a same decision. If not, a decision associated with a greatest reliability is selected from the decision detectors that are able to come to a decision.

Abstract: A method of processing a stream of coded data before decoding comprises a step of detecting missing or erroneous data in the stream of coded data. It comprises a step of generating a series of data ready for decoding formed from the stream of coded data, and a series of additional data supplying information representing the position of the missing or erroneous data detected.

Abstract: Various embodiments of the present invention provide systems and methods for stochastic stream decoding of binary LDPC codes. For example, a data decoder circuit is discussed that includes a number of variable nodes and check nodes, with serial connections between the variable nodes and the check nodes. The variable nodes are each operable to perform a real-valued computation of a variable node to check node message for each neighboring check node. The check nodes are operable to perform a real-valued computation of a check node to variable node message for each neighboring variable node. The messages are passed iteratively between the variable nodes and the check nodes.

Abstract: A system receives a first word on which to perform error correction; identifies combinations in which encoded bits, within the first word, can be inverted; generates candidate words based on the first word and the combinations; decodes the candidate words; determines distances between the decoded words and the first word; selects, as a second word, one of the decoded words associated with a shortest distance; compares the second word to the first word to identify errors within the first word; generates a value to cause a reliability level of the first word to increase when a quantity of the errors is less than a threshold; generates another value to cause a reliability level of the first word to decrease when the quantity of the errors is not less than the threshold; and outputs a third word based on the first word, and the value or the other value.

Abstract: A decoder comprises a feedback shift register having a plurality of register elements that implement a simplex code and take a register vector for determining an appropriate syndrome fed into the feedback shift register and stored in the plurality of register elements. A combination device algebraically combines a subset of the register elements and provides a combination result vector. A majority decision-making unit ascertains a most frequently occurring value within the combination result vector and provides it as a decision result. An input selector connects an input of the feedback shift register to an input interface arrangement or to an output of the majority decision-making unit, and provides an input vector by the input interface arrangement and corresponds to the ascertained form of the physical unclonable properties as a register vector and, and provides a decision vector comprising the decision result and further decision results as a register vector.

Abstract: There is provided a solution for rearranging data to a decoder of a receiver. The solution comprises receiving data, writing the data to one or more memory slots in parts, first in an ascending order of addresses and then in a descending order of addresses. The solution further comprises reading the full memory slots in a descending order of addresses and forwarding the read data to the decoder.

Abstract: Properly detects an anomaly on the basis of directional data that are obtained in sequence from a monitored object.