Threshold Decoding (e.g., Majority Logic) Patents (Class 714/760)
  • Patent number: 10936388
    Abstract: A method begins by a dispersed storage (DS) processing unit of a dispersed storage network (DSN) generating a hint regarding data stored or to be stored. When the data is to be stored, the DS processing module divides the data into data segments and dispersed storage error encodes a data segment of the data segments to produce a set of encoded data slices. The method continues by the DS processing unit generating a set of hints based on the hint and affiliating the set of hints with the set of encoded data slices to produce a set of affiliated encoded data slices. The method continues by the DS processing unit sending the set of affiliated encoded data slices to a set of storage units of the DSN such that a storage unit of the set of storage units stores an encoded data slice in accordance with a corresponding hint.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: March 2, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Wesley B. Leggette
  • Patent number: 10868624
    Abstract: An active optical cable (AOC) signals to a source that it needs power above a standard voltage, e.g., above five volts, by sending a signal such as a voltage step from one non-zero voltage to a second non-zero voltage or other voltage pattern on a hot plug detect (HPD) pin of a display data channel (DDC). While a legacy source device may not be able to detect this and consequently will operate as usual, a source device programmed according to present principles detects the request for more power represented by the voltage pattern established by the AOC, and in response increases the power (voltage and/or current) on DDC 5V line to the requested level, e.g., 10V at 500 mA.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: December 15, 2020
    Assignee: Sony Corporation
    Inventors: Peter Shintani, Robert Noel Blanchard
  • Patent number: 10776200
    Abstract: An embodiment of a semiconductor apparatus may include technology to provide information related to one or more parity capabilities of a controller and a persistent storage media in response to an inquiry from a host device, and adjust one or more parameters related to the one or more parity capabilities of the controller and the persistent storage media in response to a request from the host device. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: September 15, 2020
    Assignee: Intel Corporation
    Inventors: Jeffrey McVay, Joseph Edgington, Mark Leinwander
  • Patent number: 10667204
    Abstract: A plurality of communication stations transmit a plurality of modulated signals so that data is efficiently transmitted from a network through negotiation by a communication terminal capable of transmitting and receiving modulated signals of a plurality of wireless communication schemes with a proxy server present on a network. The communication terminal receives a plurality of modulated signals to obtain data. Thus, the efficiency of frequency utilization is improved.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: May 26, 2020
    Assignee: Panasonic Intellectual Property Corporation of America
    Inventor: Yutaka Murakami
  • Patent number: 10659238
    Abstract: A multi-port PUF circuit based on MOSFET current division deviations comprises a reference source, a row decoder, a column decoder, a timing controller and 32 PUF arrays. Each PUF array comprises 512 PUF cells arranged in 128 rows and 4 columns, an arbiter, a 1st inverter, a 2nd inverter, a 3rd inverter, a 4th inverter and eight transmission gates. The reference source is connected to the PUF arrays. The mth output terminal of the row decoder is connected to the mth row selective signal input terminals of the 32 PUF arrays. The jth output terminal of the column decoder is connected to the jth selective signal input terminals of the 32 PUF arrays. The 1st output terminal of the timing controller is connected to the control terminal of the row decoder. The 2nd output terminal of the timing controller is connected to the control terminal of the column decoder. The multi-port PUF circuit has the advantages of small circuit area and low power consumption while ensuring circuit performance.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: May 19, 2020
    Assignee: Ningbo University
    Inventors: Pengjun Wang, Gang Li, Yuejun Zhang, Huihong Zhang
  • Patent number: 10573377
    Abstract: Apparatuses and methods for determining soft data for fractional digit memory cells are provided. One example apparatus can include a controller to determine states of memory cells of a group of memory cells operated as fractional digit memory cells, and determine soft data based, at least partially, on dimensions to which particular memory cells correspond with respect to the group of memory cells, determined states of the memory cells with respect to a state adjacent a state corresponding to a swapping shell, and whether a particular memory cell is a candidate for swapping.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: February 25, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Sivagnanam Parthasarathy, Patrick R. Khayat, Mustafa N. Kaynak
  • Patent number: 10498362
    Abstract: A system for an Error Correction Code (“ECC”) decoder includes a first decoder and a second decoder. The first decoder is configured to determine a first estimated number of errors in encoded data received at the first decoder and to compare the first estimated number of errors to a first threshold and a second threshold. The second decoder is configured to receive the encoded data when the first estimated number of errors is below the first threshold and is above a second threshold. When the first estimated number of errors is above the first threshold, the first decoder passes the encoded data out of the ECC. The first decoder has a lower power consumption than the second decoder.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: December 3, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Paul Hanham, Josh Bowman, David Symons
  • Patent number: 10475518
    Abstract: According to one embodiment, a memory system comprises a nonvolatile memory, and a memory controller configured to manage a history value about setting of a read voltage in performing reading of data from the nonvolatile memory, in accordance with a first management unit and a second management unit, a size of the second management unit being smaller than a size of the first management unit. A first region of the nonvolatile memory corresponds to the first management unit. A plurality of second regions of the nonvolatile memory each correspond to the second management unit. The first region includes the plurality of second regions.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: November 12, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Takehiko Amaki, Riki Suzuki, Yoshihisa Kojima
  • Patent number: 10409661
    Abstract: A method begins by a dispersed storage (DS) processing unit of a dispersed storage network (DSN) generating a hint regarding data stored or to be stored. When the data is to be stored, the DS processing module divides the data into data segments and dispersed storage error encodes a data segment of the data segments to produce a set of encoded data slices. The method continues by the DS processing unit generating a set of hints based on the hint and affiliating the set of hints with the set of encoded data slices to produce a set of affiliated encoded data slices. The method continues by the DS processing unit sending the set of affiliated encoded data slices to a set of storage units of the DSN such that a storage unit of the set of storage units stores an encoded data slice in accordance with a corresponding hint.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: September 10, 2019
    Assignee: International Business Machines Corporation
    Inventor: Wesley B. Leggette
  • Patent number: 10389456
    Abstract: A wireless receiver is disclosed that includes a peak detector coupled to receive a plurality of phases of an input signal, said plurality being substantially in quadrature, and to provide a detector output and a demodulator comprising an analog comparator coupled to receive said detector output and to provide a comparator output.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: August 20, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Sudipto Chakraborty
  • Patent number: 10224083
    Abstract: A semiconductor device according to one embodiment includes a unique ID generation circuit configured to generate a unique ID using a memory array including a plurality of complementary cells, each of the complementary cells includes first and second memory cells MC1 and MC2. The unique ID generation circuit uses, when data in the complementary cell read out in a first state in which an initial threshold voltage of the first memory cell MC1 has been virtually offset and data in the complementary cell read out in a second state in which an initial threshold voltage of the second memory cell MC2 has been virtually offset coincide with each other, the data in the complementary cell as the unique ID.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: March 5, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Tomoya Saito
  • Patent number: 10128870
    Abstract: Systems and methods for maximizing read performance of error detection code are provided. More particularly, systems and methods for maximizing read performance of Reed Solomon Based code are provided.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: November 13, 2018
    Assignee: LOCKHEED MARTIN CORPORATION
    Inventor: Richard C. Vanhall
  • Patent number: 10084567
    Abstract: Early termination of enhanced multimedia broadcast-multicast service (eMBMS) is discussed. Forward error correction (FEC) redundancy data is added to broadcast data, such that if enough of the data symbols are successfully received, the data object may be reassembled before the entire transmission has been received. The aspects involve an application processor and modem processor, which may either be integrated into the same integrated circuit or separate components. The application processor obtains a total number of source symbols and a redundancy level for a data object to be received from the eMBMS, receives the successfully received data symbols from the modem processor, and then determines whether the number of successfully received data symbols exceeds a threshold for reassembling the transmitted data object. If so, then the application processor and/or the modem processor can shut down until the next broadcast.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: September 25, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Kuo-Chun Lee, Sivaramakrishna Veerepalli, Jack Shyh-hurng Shauh, Shailesh Maheshwari, Daniel Amerga, Ralph Akram Gholmieh
  • Patent number: 10027349
    Abstract: A memory management system and a method of managing a memory device are described. The system includes a memory device with a memory array to store data and associated error correction coding (ECC) bits and an extended correction table. The extended correction table stores error information additional to the ECC bits for one or more of the data in the memory array. The system also includes a controller to control the memory device to write and read the data.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: July 17, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael B. Healy, Hillery C. Hunter, Charles A. Kilmer, Kyu-hyoun Kim, Warren E. Maule, Adam J. McPadden
  • Patent number: 9875792
    Abstract: Apparatuses and methods for determining soft data for fractional digit memory cells are provided. One example apparatus can include a controller to determine states of memory cells of a group of memory cells operated as fractional digit memory cells, and determine soft data based, at least partially, on dimensions to which particular memory cells correspond with respect to the group of memory cells, determined states of the memory cells with respect to a state adjacent a state corresponding to a swapping shell, and whether a particular memory cell is a candidate for swapping.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: January 23, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Sivagnanam Parthasarathy, Patrick R. Khayat, Mustafa N. Kaynak
  • Patent number: 9740547
    Abstract: A method begins by a processing module of a dispersed storage network (DSN) receiving a data object for storage in DSN memory and determining dispersed storage error encoding parameters for encoding the data object to produce a plurality of sets of encoded data slices. The method continues with the processing module determining to use a dual storage path approach for storing the plurality of sets of encoded data slices in first memory type of the DSN memory and in second memory type of the DSN memory. The method continues with the processing module dispersed storage error encoding the data object to produce the plurality of sets of encoded data slices and outputting the plurality of sets of encoded data slices to the first and second memory types of the DSN memory in accordance with the dispersed storage error encoding parameters.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: August 22, 2017
    Assignee: International Business Machines Corporation
    Inventor: S. Christopher Gladwin
  • Patent number: 9632865
    Abstract: The disclosure is related to systems and methods of providing superparity protection to data. A storage device or other processing system, such as a host, may be capable of providing intermediate superparity protection to data. For example, superparity may be determined in response to a command received at a storage device. A superparity can be determined for read data to provide superparity protection to the read data. It may also be determined whether the read data is already protected by a valid superparity.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: April 25, 2017
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Richard P Michel, Narayanan Krishnamurthy, Anil Kashyap
  • Patent number: 9300328
    Abstract: Systems and methods are provided for decoding data. A decoder includes a syndrome memory, a state memory, and decoding circuitry communicatively coupled to the syndrome memory and the state memory. The decoding circuitry retrieves data related to a symbol from the syndrome memory. The decoding circuitry also retrieves data related to the symbol from the state memory. The decoding circuitry processes the data retrieved from the syndrome memory and the data retrieved from the state memory to determine whether to toggle a value of the symbol. The determination is based at least in part on whether the symbol of the data being decoded was previously toggled from an original state.
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: March 29, 2016
    Assignee: MARVELL INTERNATIONAL LTD.
    Inventor: Nedeljko Varnica
  • Patent number: 9286259
    Abstract: The present invention provides a method and an apparatus for lowering I/O power of a computer system and a computer system. According to an aspect of the present invention, there is provided a method for lowering I/O power of a computer system, comprising: buffering a plurality of ways of data to be sent to a bus; encoding each of the plurality of ways of data buffered from n bits to n+m bits based on an encoding rule, wherein n and m are both an integer larger than or equal to 1, the encoding rule is used to lower code switching frequency; and sending the plurality of ways of data encoded to the bus.
    Type: Grant
    Filed: October 10, 2008
    Date of Patent: March 15, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yu Li, Wen Bo Shen, Yan Qi Wang, Yudong Yang
  • Patent number: 9087275
    Abstract: An apparatus supporting hybrid quick response (QR) codes may include: a computer chassis; a dynamic display on the exterior of the computer chassis, the dynamic display configured to render dynamic QR code portions; and a static display that includes static QR code portions, where the static display is adapted to the chassis such that the static QR code portions and dynamic QR code portions rendered by the dynamic display comprise a single, hybrid scannable QR code.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: July 21, 2015
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventors: Adrian X. Rodriguez, Felicia N. Soto
  • Patent number: 9082052
    Abstract: An apparatus supporting hybrid quick response (QR) codes may include: a computer chassis; a dynamic display on the exterior of the computer chassis, the dynamic display configured to render dynamic QR code portions; and a static display that includes static QR code portions, where the static display is adapted to the chassis such that the static QR code portions and dynamic QR code portions rendered by the dynamic display comprise a single, hybrid scannable QR code.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: July 14, 2015
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventors: Adrian X. Rodriguez, Felicia N. Soto
  • Patent number: 9058842
    Abstract: The present inventions are related to systems and methods for iterative data processing scheduling. In one case a data processing system is disclosed that includes a data detector circuit and a data decoder circuit. The data detector circuit is operable to apply a data detection algorithm to a data set to yield a detected output. The data decoder circuit is operable to repeatedly apply a data decoding algorithm to the detected output to yield a decoded output over a number of passes, where the number of passes is within an allowable number of local iterations selected based at least in part on a read gate signal.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: June 16, 2015
    Assignee: LSI Corporation
    Inventors: Fan Zhang, Yang Han, Ming Jin, Chung-Li Wang
  • Patent number: 9015537
    Abstract: According to exemplary embodiments, a system, is provided for bit error rate (BER)-based wear leveling in a solid state drive (SSD). A block-level BER value for a block in the SSD is determined. An adjusted PE cycle count for the block is incremented or decremented based on the block-level BER value. Wear leveling is then performed in the SSD based on the adjusted PE cycle count.
    Type: Grant
    Filed: December 10, 2013
    Date of Patent: April 21, 2015
    Assignee: International Business Machines Corporation
    Inventors: Thomas J. Griffin, Dustin J. Vanstee
  • Patent number: 9015555
    Abstract: A method is provided in one example and includes receiving a data stream that includes an error code probability; detecting an error in the data stream; and determining whether to generate an error signal for the error in the data stream based on the error code probability being compared to a threshold value. In more particular embodiments, the error code probability may be based on a total number of network elements that receive the data stream. In addition, more specific methodologies may include generating a number to be used as a basis for the threshold value; and generating the error signal if the error code probability is below the threshold value.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: April 21, 2015
    Assignee: Cisco Technology, Inc.
    Inventors: Charles Moreman, William C. VerSteeg
  • Patent number: 9003267
    Abstract: This disclosure relates generally to low power data decoding, and more particularly to low power iterative decoders for data encoded with a low-density parity check (LDPC) encoder. Systems and methods are disclosed in which a low-power syndrome check may be performed in the first iteration or part of the first iteration during the process of decoding a LDPC code in an LDPC decoder. Systems and methods are also disclosed in which a control over the precision of messages sent or received and/or a change in the scaling of these messages may be implemented in the LDPC decoder. The low-power techniques described herein may reduce power consumption without a substantial decrease in performance of the applications that make use of LDPC codes or the devices that make use of low-power LDPC decoders.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: April 7, 2015
    Assignee: Marvell World Trade Ltd.
    Inventors: Nedeljko Varnica, Gregory Burd
  • Patent number: 8924816
    Abstract: A method and system to improve the performance and/or reliability of a solid-state drive (SSD). In one embodiment of the invention, the SSD has logic to compress a block of data to be stored in the SSD. If it is not possible to compress the block of data below the threshold, the SSD stores the block of data without any compression. If it is possible to compress the block of data below the threshold, the SSD compresses the block of data and stores the compressed data in the SSD. In one embodiment of the invention, the SSD has logic to dynamically adjust or select the strength of the error correcting code of the data that is stored in the SSD. In another embodiment of the invention, the SSD has logic to provide intra-page XOR protection of the data in the page.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: December 30, 2014
    Assignee: Intel Corporation
    Inventor: Jawad B. Khan
  • Patent number: 8892980
    Abstract: An apparatus, system, and method are disclosed for providing error correction for a data storage device. A determination module determines an error-correcting code (“ECC”) characteristic of the data storage device. An ECC module validates requested data read from the data storage device using a hardware ECC decoder. In response to the requested data satisfying a correction threshold, a software ECC decoder module validates the data using a software ECC decoder. The software ECC decoder is configured according to the ECC characteristic of the data storage device.
    Type: Grant
    Filed: June 15, 2011
    Date of Patent: November 18, 2014
    Assignee: Fusion-io, Inc.
    Inventor: Jeremy Fillingim
  • Publication number: 20140325306
    Abstract: By utilizing Reed-Solomon erasure decoding algorithms and techniques, the system is able to perform error detection for the case where the number of bytes received in error exceeds a correcting capability of a decoder. The error detection can be used, for example, to determine whether a codeword is decodable, and whether the retransmission of data is necessary. The retransmission can be accomplished by assembling a message that is sent to another modem requesting retransmission of one or more portions of data, such as one or more codewords.
    Type: Application
    Filed: July 10, 2014
    Publication date: October 30, 2014
    Inventors: Joshua Grossman, John A. Greszczuk, Marcos C. Tzannes
  • Patent number: 8862967
    Abstract: A method may be performed at a data storage device that includes a memory and a controller. The method includes providing user data to a variable-bit error correction coding (ECC) encoder. The ECC encoder generates a first set of parity bits. A first number of parity bits in the first set of parity bits is determined based on stored counts of read errors. The method also includes storing the user data and the first set of parity bits to a memory of the data storage device.
    Type: Grant
    Filed: April 19, 2012
    Date of Patent: October 14, 2014
    Assignee: Sandisk Technologies Inc.
    Inventors: Deepak Pancholi, Manuel Antonio D'Abreu, Radhakrishnan Nair, Stephen Skala
  • Patent number: 8856603
    Abstract: To produce a memory which resists ion or photon attack, a memory structure is chosen whose memory point behaves asymmetrically with regard to these attacks. It is shown that in this case, it is sufficient to have a reference cell for an identical and periodic storage structure in order to be able to correct all the memory cells assailed by an attack. An error correction efficiency of ½ is thus obtained, with a simple redundancy, whereas the conventional methods make provision, for the same result, to triple the storage, to obtain a less beneficial efficiency of ?.
    Type: Grant
    Filed: June 18, 2009
    Date of Patent: October 7, 2014
    Assignees: European Aeronautic Defence And Space Company EADS France, Astrium SAS
    Inventors: Florent Miller, Thierry Carriere, Antonin Bougerol
  • Patent number: 8843800
    Abstract: A semiconductor integrated circuit pertaining to the present invention comprises a plurality of storage elements for storing and holding an input signal, a majority circuit that outputs a result of a majority decision of outputs from the plurality of storage elements; an error detector circuit that detects a mismatch among the outputs of the plurality of storage elements and outputs error signals; and a monitor circuit that monitors the error signals from the error detector circuit, wherein the monitor circuit, based on the error signals, orders a refresh action that rewrites data for rectification to a storage element in which an output mismatch occurs out of the plurality of storage elements and, if rewrite and rectification by the refresh action are unsuccessful, sends a notification to an external unit or process.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: September 23, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Koichi Nakamura
  • Patent number: 8839070
    Abstract: A plurality of error correction circuits connected in series include a calculator circuit that corrects the codeword when the determination results of a determination circuit indicate that the error correction circuit at the present stage is to correct the codeword, and a determination circuit at a subsequent error correction apparatus determines whether the error correction circuit at the subsequent stage is to correct the codeword when the determination results of the determination circuit indicate that the error correction circuit at the present stage is not to correct the codeword.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: September 16, 2014
    Assignee: Fujitsu Limited
    Inventor: Yohei Koganei
  • Patent number: 8832506
    Abstract: According to exemplary embodiments, a system, method, and computer program product are provided for BER-based wear leveling in a SSD. A block-level BER value for a block in the SSD is determined. An adjusted PE cycle count for the block is incremented or decremented based on the block-level BER value. Wear leveling is then performed in the SSD based on the adjusted PE cycle count.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: September 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Thomas J. Griffin, Dustin J. Vanstee
  • Patent number: 8806309
    Abstract: A method for controlling a message-passing algorithm (MPA) based decoding operation includes: gathering statistics data of syndromes obtained from executed iterations; and selectively adjusting a decoding operation in a next iteration to be executed according to the statistics data. A control apparatus for controlling an MPA based decoder includes an adjusting circuit and a detecting circuit. The detecting circuit is coupled to the adjusting circuit, and used for gathering statistics data of syndromes obtained from executed iterations, and selectively controlling the adjusting circuit to adjust a decoding operation in a next iteration to be executed according to the statistics data.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: August 12, 2014
    Assignee: Silicon Motion Inc.
    Inventors: Zhen-U Liu, Tsung-Chieh Yang
  • Patent number: 8762812
    Abstract: A decoding device includes: a determination unit that determines whether or not a decoding ending condition is satisfied at an interval shorter than an interval of one decoding process in repeated decoding and ends the process in the middle of the one decoding process in a case where the decoding ending condition is satisfied.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: June 24, 2014
    Assignee: Sony Corporation
    Inventor: Hiroyuki Yamagishi
  • Patent number: 8739010
    Abstract: An integrated circuit may have an array of memory elements. Each memory element may have multiple memory cells. Each memory element may have a voting circuit that receives signals from the memory cells in that memory element. The voting circuit can produce an output based on the signals. The signals stored by the memory cells of each memory element may be redundant so that the voting circuit can produce an accurate output even in the event that a radiation strike causes some of the memory cells to flip their states to erroneous values. The memory elements may be based on memory cells such as static random-access memory cells and thyristor-based cells.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: May 27, 2014
    Assignee: Altera Corporation
    Inventor: Yanzhong Xu
  • Patent number: 8729923
    Abstract: Data words from a parallel communication channel are interleaved to two majority vote blocks that operate out of phase, using a divided clock signal that has half the clock frequency of the clock signal associated with the parallel communication channel. As one majority vote block evaluates a data word and outputs a result, the other majority vote block is in pre-charge mode awaiting the next data for evaluation.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: May 20, 2014
    Assignee: SanDisk Technologies Inc.
    Inventor: Venkatesh Ramachandra
  • Patent number: 8713413
    Abstract: A plurality of interpolated samples is generated. Using a plurality of soft-decision detectors, error correction decoding is performed on the plurality of interpolated samples in order to obtain a plurality of decisions. From the plurality of decisions, one is selected by determining which of the plurality of soft-decision detectors are able to come to a decision during error correction decoding. It is determined whether a majority of the detectors that are able to come to a decision come to a same decision. If not, a decision associated with a greatest reliability is selected from the decision detectors that are able to come to a decision.
    Type: Grant
    Filed: February 7, 2011
    Date of Patent: April 29, 2014
    Assignee: SK hynix memory solutions inc.
    Inventors: Jason Bellorado, Marcus Marrow
  • Patent number: 8650469
    Abstract: A method of processing a stream of coded data before decoding comprises a step of detecting missing or erroneous data in the stream of coded data. It comprises a step of generating a series of data ready for decoding formed from the stream of coded data, and a series of additional data supplying information representing the position of the missing or erroneous data detected.
    Type: Grant
    Filed: April 2, 2009
    Date of Patent: February 11, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Christophe Gisquet, Hervé Le Floch
  • Patent number: 8650451
    Abstract: Various embodiments of the present invention provide systems and methods for stochastic stream decoding of binary LDPC codes. For example, a data decoder circuit is discussed that includes a number of variable nodes and check nodes, with serial connections between the variable nodes and the check nodes. The variable nodes are each operable to perform a real-valued computation of a variable node to check node message for each neighboring check node. The check nodes are operable to perform a real-valued computation of a check node to variable node message for each neighboring variable node. The messages are passed iteratively between the variable nodes and the check nodes.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: February 11, 2014
    Assignee: LSI Corporation
    Inventors: Anantha Raman Krishnan, Nenad Miladinovic, Yang Han, Shaohua Yang
  • Patent number: 8645788
    Abstract: A system receives a first word on which to perform error correction; identifies combinations in which encoded bits, within the first word, can be inverted; generates candidate words based on the first word and the combinations; decodes the candidate words; determines distances between the decoded words and the first word; selects, as a second word, one of the decoded words associated with a shortest distance; compares the second word to the first word to identify errors within the first word; generates a value to cause a reliability level of the first word to increase when a quantity of the errors is less than a threshold; generates another value to cause a reliability level of the first word to decrease when the quantity of the errors is not less than the threshold; and outputs a third word based on the first word, and the value or the other value.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: February 4, 2014
    Assignee: Infinera Corporation
    Inventors: Jeffrey T. Rahn, Han Henry Sun, Stanley H. Blakey
  • Publication number: 20140032990
    Abstract: A decoder comprises a feedback shift register having a plurality of register elements that implement a simplex code and take a register vector for determining an appropriate syndrome fed into the feedback shift register and stored in the plurality of register elements. A combination device algebraically combines a subset of the register elements and provides a combination result vector. A majority decision-making unit ascertains a most frequently occurring value within the combination result vector and provides it as a decision result. An input selector connects an input of the feedback shift register to an input interface arrangement or to an output of the majority decision-making unit, and provides an input vector by the input interface arrangement and corresponds to the ascertained form of the physical unclonable properties as a register vector and, and provides a decision vector comprising the decision result and further decision results as a register vector.
    Type: Application
    Filed: July 25, 2013
    Publication date: January 30, 2014
    Applicant: Infineon Technologies AG
    Inventor: Rainer Goettfert
  • Patent number: 8640004
    Abstract: There is provided a solution for rearranging data to a decoder of a receiver. The solution comprises receiving data, writing the data to one or more memory slots in parts, first in an ascending order of addresses and then in a descending order of addresses. The solution further comprises reading the full memory slots in a descending order of addresses and forwarding the read data to the decoder.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: January 28, 2014
    Assignee: Nokia Corporation
    Inventor: Petros Oikonomakos
  • Patent number: 8640015
    Abstract: Properly detects an anomaly on the basis of directional data that are obtained in sequence from a monitored object.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: January 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Tsuyoshi Ide, Keisuke Inoue, Toshiyuki Yamane, Hironori Takeuchi
  • Patent number: 8631300
    Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for power governance in a data processing system.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: January 14, 2014
    Assignee: LSI Corporation
    Inventors: Yang Han, Shaohua Yang, Zhi Kai Chen, Lei Wang, Changyou Xu
  • Patent number: 8621312
    Abstract: An embodiment of the present invention provides an apparatus, including a transceiver operable for communication using LDPC codes for error correction, the transceiver adapted to use an LDPC decoder that acts as a server to serve all LDPC codewords contained in at least one block transmission, and wherein the LDPC decoder consumes a certain number of clock cycles per decoding of a single codeword and a length of the block dictates a clock cycles budget that the server can use.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: December 31, 2013
    Assignee: Intel Corporation
    Inventor: Ilan Sutskover
  • Patent number: 8612827
    Abstract: A computer includes an interface and a processing module. The processing module receives, over time and via the interface, requests to playback recorded broadcast data, wherein a single copy of the recorded broadcast data is dispersed error encoded to produce a plurality of sets of encoded data slices that is stored in a dispersed storage network (DSN). In response to the playback requests, the processing module identifies unique combinations of at least a threshold number of encoded data slices for sets of the plurality of sets of encoded data slices to produce unique copies of the recorded broadcast data. For a particular playback request, the processing module retrieves a unique copy of the unique copies of the recorded broadcast data from the DSN and outputs, via the interface, the retrieved unique copy to a device associated with the particular playback request.
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: December 17, 2013
    Assignee: Cleversafe, Inc.
    Inventors: S. Christopher Gladwin, Kumar Abhijeet, Greg Dhuse, Jason K. Resch, Gary W. Grube, Timothy W. Markison
  • Patent number: 8589756
    Abstract: A memory card according to an embodiment includes: a memory section having a binary storage area (SLC area) and a multi-value storage area (MLC area); an error correction section configured to correct an error of data stored in the MLC area; and an erasure correction section configured to store, in the SLC area, the position information on the multi-value memory cell storing the data having the error detected by the error correction section and configured to perform erasure correction on the basis of the position information.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: November 19, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukio Ishikawa, Kenji Sakaue
  • Patent number: 8583982
    Abstract: A concatenated decoder and concatenated decoding method are provided. The concatenated decoder, including: an inner decoder to receive an input bit stream, inner-decode the received input bit stream, and generate a first bit stream; and an outer decoder to generate error information about the received first bit stream, according to the generated error information, transmit an iterative decoding continuation request to the inner decoder or outer-decode the first bit stream to generate a second bit stream.
    Type: Grant
    Filed: March 11, 2008
    Date of Patent: November 12, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaehong Kim, Jun Jin Kong
  • Patent number: 8572452
    Abstract: A block code decoding method and device thereof are provided. The procedure of the bounded distance decoding is simplified and the number of correlation calculating is reduced via a set of pre-established XOR masks. The decoding method includes: picking up the source code part of the received message; executing a XOR calculating for the source code part with the XOR masks, and encoding the results thereof to produce a set of compared codes; executing a correlation calculating for the set of compared codes and the received message; and determining a compared code having the maximum correlation result as the decision.
    Type: Grant
    Filed: September 25, 2009
    Date of Patent: October 29, 2013
    Assignee: Realtek Semiconductor Corp.
    Inventors: Cheng-Kang Wang, Chun-Ming Cho, Chia Chun Hung