Abstract: An embodiment of the present invention provides an apparatus, including a transceiver operable for communication using LDPC codes for error correction, the transceiver adapted to use an LDPC decoder that acts as a server to serve all LDPC codewords contained in at least one block transmission, and wherein the LDPC decoder consumes a certain number of clock cycles per decoding of a single codeword and a length of the block dictates a clock cycles budget that the server can use.

Abstract: A computer includes an interface and a processing module. The processing module receives, over time and via the interface, requests to playback recorded broadcast data, wherein a single copy of the recorded broadcast data is dispersed error encoded to produce a plurality of sets of encoded data slices that is stored in a dispersed storage network (DSN). In response to the playback requests, the processing module identifies unique combinations of at least a threshold number of encoded data slices for sets of the plurality of sets of encoded data slices to produce unique copies of the recorded broadcast data. For a particular playback request, the processing module retrieves a unique copy of the unique copies of the recorded broadcast data from the DSN and outputs, via the interface, the retrieved unique copy to a device associated with the particular playback request.

Abstract: A memory card according to an embodiment includes: a memory section having a binary storage area (SLC area) and a multi-value storage area (MLC area); an error correction section configured to correct an error of data stored in the MLC area; and an erasure correction section configured to store, in the SLC area, the position information on the multi-value memory cell storing the data having the error detected by the error correction section and configured to perform erasure correction on the basis of the position information.

Abstract: A concatenated decoder and concatenated decoding method are provided. The concatenated decoder, including: an inner decoder to receive an input bit stream, inner-decode the received input bit stream, and generate a first bit stream; and an outer decoder to generate error information about the received first bit stream, according to the generated error information, transmit an iterative decoding continuation request to the inner decoder or outer-decode the first bit stream to generate a second bit stream.

Abstract: A block code decoding method and device thereof are provided. The procedure of the bounded distance decoding is simplified and the number of correlation calculating is reduced via a set of pre-established XOR masks. The decoding method includes: picking up the source code part of the received message; executing a XOR calculating for the source code part with the XOR masks, and encoding the results thereof to produce a set of compared codes; executing a correlation calculating for the set of compared codes and the received message; and determining a compared code having the maximum correlation result as the decision.

Abstract: A method includes, after data is stored at a data area of a memory device and error correction code (ECC) data corresponding to the data is stored at an ECC area corresponding to the data area, detecting a triggering condition. In response to detecting the triggering condition, the method also includes storing second ECC data in the ECC area, where the second ECC data includes redundant information for a first portion of the data area and storing third ECC data at the memory device. The third ECC data includes redundant information for a second portion of the data area.

Abstract: A method and system to improve the performance and/or reliability of a solid-state drive (SSD). In one embodiment of the invention, the SSD has logic compress a block of data to be stored in the SSD. If it is not possible to compress the block of data below the threshold, the SSD stores the block of data without any compression. If it is possible to compress the block of data below the threshold, the SSD compresses the block of data and stores the compressed data in the SSD. In one embodiment of the invention, the SSD has logic to dynamically adjust or select the strength of the error correcting code of the data that is stored in the SSD. In another embodiment of the invention, the SSD has logic to provide intra-page XOR protection of the data in the page.

Abstract: A data element can be encoded into multiple encoded data elements using an encoding algorithm that includes an encoding function and one or more encoder constant. The encoded data elements can be organized into multiple pillars, each having a respective pillar number. Each of the pillars is sent to a different storage unit of a distributed storage network. To recover the original data element, the encoded data elements are retrieved from storage, and the encoder constant is recovered using multiple encoded data elements. Recovering the encoder constant allows the encoding algorithm originally used to encode the data elements to be determined, and used to recover the original data element. The security of the stored data is enhanced, because an encoded data element from a single pillar is insufficient to identify the encoder constant.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for power governance in a data processing system.

Abstract: A method includes providing data including hard bit data and soft bit data to a rank modulation decoder.

Abstract: A network controller receives data substantially simultaneously from multiple client nodes. The network controller assigns to each client node one or more sub-carriers of an orthogonal frequency-division multiplexing access frequency spectrum. The client nodes transmit substantially simultaneously M LDPC codewords that are encoded in a parity check matrix so that the number of rows m? depend on the code rate and are mapped on its assigned sub-carriers. The network controller computes a bit log-likelihood ratio for each received bit of the codewords and arranges the bit LLR by codeword to align with an equivalent parity check matrix. The network controller decodes the codewords with the equivalent parity check matrix.

Abstract: The present invention relates to an apparatus and a method for detecting presence of data, wherein input data is decoded using a decoder metric to obtain decoded data, and an error check is performed for the decoded data. Furthermore, a threshold value is determined based on an obtained maximum value that the decoder metric can assume for the input data, and the threshold value is compared with an actual value of the decoder metric. Presence of the input data is then decided based on results of the error check and the comparison.

Abstract: Various embodiments relate to the production of erasure flags to indicate errors resulting from decoding of convolutional codes. A Viterbi decoder may use a register exchange method to produce a plurality of survivor codes. At a defined index, a majority vote may take place comparing values of bits in each of the survivor codes. This majority vote may involve obtaining both the quantity of high-order bits and the quantity of low-order bits and obtaining the difference of the two quantities. The absolute value of the difference of high-order bits to low-order bits may be compared to a defined threshold. When the absolute value difference is below the defined quantity, an erasure flag may be produced and associated with the bits of the defined index, indicating that they are eligible for erasure. In some embodiments, a Reed-Solomon decoder may use the erasure flag to target specific survivor bits or survivor bytes for error-correction through erasure.

Abstract: Apparatus, and an associated method, for estimating a bit error rate of data communicated to a receiving station of a digital communications system, such as a GSM/EDGE cellular communication system. Soft decision values, indicative of confidence levels that decided values have been correctly decided are compared with threshold values by a comparator. A count is accumulated by a counter whose counted value is representative of decided data values having low levels of confidence that the decided values are correct. The count value is used in the formulation of the BER estimation.

Abstract: A transmitting apparatus transmits a plurality of data packets to a receiver in a communication system, by transmitting one or more data packets from a list of data packets to be transmitted, and determining whether an acknowledgment is received for each transmitted data packet. When it is determined that an acknowledgement has not been received for at least one data packet, referred to as an unacknowledged data packet, the apparatus selects one or more additional data packets from the list of data packets to be transmitted, generates one or more parity packets by encoding a block of data containing a combination of the selected one or more additional data packets and at least one unacknowledged data packet using a forward error correction scheme, and transmits at least one of the generated parity packets.

Abstract: A method of encoding for optical transmission of information includes encoding information with a generalized low-density parity-check (GLDPC) code for providing coding gains, and constructing the GLDPC code with a Reed-Muller RM code as a component code, the component code being decodable using a maximum posterior probability (MAP) decoding. In a preferred embodiment, the GLDPC code includes a codeword length of substantially 4096, an information word length of substantially 3201, a lower-bound on minimum distance of substantially greater than or equal to 16, a code rate of substantially 0.78 and the RM component code includes an order of substantially 4 and an r parameter of substantially 6.

Abstract: Systems and methods for data loss protection are presented. In one embodiment, a data loss protection switch includes a first port, a second port, an error threshold management component and a multiplexer. Components of the data loss protection switch cooperatively operate to efficiently protect data. The first port receives information from a first data stream. The second port receives data from a second data stream. The error threshold management component analyzes errors in the first data stream and the second data stream. The multiplexer is controlled by the error threshold management component and selects among the first and second data streams based on the analysis.

Abstract: Systems and methods are provided for correcting absorb sets and near absorb sets in the (2048, 1723) LDPC code used in 10GBase-T transmission systems. Absorb sets and near absorb sets correspond to error patterns that, due to the structure and imperfections of the LDPC code, cannot easily be corrected using standard correction methods. To correct these error patterns, a set of failed syndrome checks associated with the error pattern can be identified, and the 4, 8, 12, or 16 error patterns associated with the failed syndrome checks can be determined. The codeword may then be corrected based on the error pattern that most likely occurred.

Abstract: A method begins by a processing module determining whether to error encode broadcast data. The method continues with the processing module encoding a portion of the broadcast data using an error coding storage dispersal function to produce a set of encoded broadcast data slices, determining whether to compress the set of encoded broadcast data slices for the set of encoded broadcast data slices, and when the set of encoded broadcast data slices is to be compressed, selecting a subset of encoded broadcast data slices of the set of encoded broadcast data slices, when the broadcast data is to be error encoded.

Abstract: A data processing apparatus includes a non-volatile semiconductor memory configured to store a storage data and an additional data control circuit configured to generate an additional data and add the additional data to a main storage data, and the additional data is different between a first mode and a second mode. The additional data control circuit includes a first mode circuit configured to generate the additional data in the first mode; and a second mode circuit configured to generate the additional data in the second mode. The storage data contains a target data or an inversion data of the target data, as the main storage data and the additional data.

Abstract: A method includes reading data from a data area of a word line and reading first ECC data from an ECC area of the word line. The method also includes, in response to determining that an error indicator exceeds a threshold, storing second ECC data in the ECC area. The second ECC data corresponds to a subsection of the data area.

Abstract: A tester is configured to access and test each redundant channel of a voter. The tester is disposed between the voter and a multitude of redundant circuits supplying redundant channel signals to the voter. The tester includes a number of input ports receiving the redundant channel signals as well as the test signals. In response to a number of logic combinations of the test signals, the voter generates output signals each corresponding to one of the redundant channel signals. In response to other logic combinations of the test signals, the voter generates a voted output signal. The voter is optionally a majority voter.

Abstract: A method for adaptively applying an error-correcting code to a storage device is disclosed. A determination is made that a system is in an idle state of input/output requests. First data symbols are copied into a first location within a buffer. First data symbol errors corrected using a first error-correcting code. Second data symbols including corrected bits are written in a second location on the recording media with a second error-correcting code. An error number for the second data symbols in the second location is determined. If the error number is below a first threshold error number, the first data symbols are deleted. If the error number is above the first threshold error number, the second data symbols are deleted.

Abstract: The invention provides a test circuit for n input/output arrays. Each of the n input/output arrays has M pairs of input/output. The test circuit includes M write drivers and M comparing circuits. The ith write driver provides an ith test signal to the ith inputs of all of the n input/output arrays, and 1?i?M. The jth comparing circuit determines if jth output signals of all of the n input/output arrays are the same, and outputs a jth comparing result correspondingly, and 1?j?M. The invention also provides a method of testing n input/output arrays. The invention also provides a storage device.

Abstract: Decoding data received includes decoding the received data using a first error correcting circuitry that decodes data in accordance with a first decoding process, terminating execution of the first decoding process used to correct the data before the first error correcting circuitry completes executing the first, decoding process and outputting partially decoded data, determining whether partially decoded data requires further decoding, and in response to determining whether partially decoded data requires further decoding, decoding the partially decoded data using a second error correcting circuitry that decodes data in accordance with a second decoding process. A system decodes data in accordance with the method.

Abstract: A phase-change memory (PCM) includes a matrix of storage cells, including at least a first group with at least one cell. Each cell includes a phase change material having at least a first resistance value and a second resistance value, such that the first group can have an identical message encoded therein in at least a first way and a second way. The memory also includes a controller configured to encode the identical message in the at least first group the first or second way, based on which way causes the least amount of writing cost, given current levels of the group. Another embodiment of memory includes a matrix of storage cells. Each of the storage cells has at least two levels, such that each of the storage cells can have an identical message encoded therein in at least a first way and a second way.

Abstract: A decoding device includes: a determination unit that determines whether or not a decoding ending condition is satisfied at an interval shorter than an interval of one decoding process in repeated decoding and ends the process in the middle of the one decoding process in a case where the decoding ending condition is satisfied.

Abstract: A tester is configured to access and test each redundant channel of a voter. The tester is disposed between the voter and a multitude of redundant circuits supplying redundant channel signals to the voter. The tester includes a number of input ports receiving the redundant channel signals as well as the test signals. In response to a number of logic combinations of the test signals, the voter generates output signals each corresponding to one of the redundant channel signals. In response to other logic combinations of the test signals, the voter generates a voted output signal. The voter is optionally a majority voter.

Abstract: Systems for identifying potentially erroneous and/or erased data are provided. Systems have a bit detector, an accumulator, and a data reconstruction processor. The bit detector assigns values to bits read in a data signal. The bit detector illustratively assigns multiple values to each of the bits. The accumulator accumulates a count of the multiple values assigned by the bit detector for each of the bits. The accumulator associates each bit with a particular value based at least in part on its accumulated count. The data reconstruction processor determines for each of the bits a confidence level of the particular value associated to it. The data reconstruction process sets flags for a portion of the bits. The flags identify the portion of the bits as possible erased or erroneous data. The flags are set based at least in part on the confidence levels of the portion of the bits.

Abstract: An electronic device detects occurrence of an error condition and selects a matrix code to include in an error message to transmit to a display device based on the error condition. A reader device decodes the displayed matrix code to present information regarding resolution of the error condition. The electronic device may select the matrix code by looking up the error condition in a table or by dynamically generate the matrix code. In various implementations, the electronic device may determine that the information regarding resolution of the error condition has been utilized to unsuccessfully resolve the error condition. If so, the electronic device may select and transmit and additional matrix code that may be decoded by the reader device to access and present an additional set of information regarding resolution of the error condition or to initiate an electronic device support request.

Abstract: Apparatus, and an associated method, for estimating a bit error rate of data communicated to a receiving station of a digital communications system, such as a GSM/EDGE cellular communication system. Soft decision values, indicative of confidence levels that decided values have been correctly decided are compared with threshold values by a comparator. A count is accumulated by a counter to whose counted value is representative of decided data values having associated therewith low levels of confidence that the decided values are correct. The count value is used in the formulation of the BER estimation.

Abstract: Systems and methods are provided for implementing various aspects of a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. If the decision-codeword corresponds to an inner code and an RS code is the outer code, a soft-information map can process the soft-information for the decision-codeword to produce soft-information for a RS decision-codeword. A RS decoder can employ the Berlekamp-Massey algorithm (BMA), list decoding, and a Chien search, and can include a pipelined architecture. A threshold-based control circuit can be used to predict whether list decoding will be needed and can suspend the list decoding operation if it predicts that list decoding is not needed.

Abstract: There is provided a solution for rearranging data to a decoder of a receiver. The solution comprises receiving data, writing the data to one or more memory slots in parts, first in an ascending order of addresses and then in a descending order of addresses. The solution further comprises reading the full memory slots in a descending order of addresses and forwarding the read data to the decoder.

Abstract: A decoding apparatus includes a decoder register for receiving data having a codeword including null data bits, and decoding the received data while shifting Bit Under Decoding (BUD) by one bit. A connection unit outputs a check result by applying a predetermined check equation to the data output from the decoder register. A majority logic unit for determines if an error is detected according to the check result output from the connection unit, and outputs the determination result. An error information unit determines if there is an error in the received data and if there is an uncorrectable error in the decoded data.

Abstract: The present invention is directed to methods of monitoring logic circuits for failures. In particular, the methods are directed toward establishing parallel logic cores where failures are detected by comparing the parallel paths for equivalence at key locations by a redundancy checker. Any mismatch will result in a predetermined failsafe operational mode. In addition, important techniques are applied to periodically exercise individual parallel paths to ensure that logic cores are verified in a way that does not disturb any process being monitored or controlled. This feature is important in some industries, such as the nuclear power industry, where safety critical operations require a high state of reliability on logic circuit blocks which may be infrequently utilized.

Abstract: A hard disk drive with a disk that has a plurality of data bits. The drive includes a circuit that reads each data bit n times and selects a value for the bit based on a reliability factor. The circuit may select a bit based at least in part on the most frequent occurrence of one of a plurality of values. For example, if more 0s occurred than 1s the bit would be set to 0. The reliability factor may be a ratio of the occurrence of 0s to the occurrence of 1s. A bit can be not selected or deselected if the reliability factor exceeds a threshold value.

Abstract: An apparatus and method are disclosed for correcting errors in data obtained from read operations on a storage medium. Errors that occur in a minority of read operations for the data are corrected by a voting technique. The data may then be processed with error correcting code to correct errors that occur in a majority of read operations.

Abstract: An apparatus, system, and method are disclosed for providing error correction for a data storage device. A determination module determines an error-correcting code (“ECC”) characteristic of the data storage device. An ECC module validates requested data read from the data storage device using a hardware ECC decoder. In response to the requested data satisfying a correction threshold, a software ECC decoder module validates the data using a software ECC decoder. The software ECC decoder is configured according to the ECC characteristic of the data storage device.

Abstract: A method begins by a processing module identifying sets of dispersed storage (DS) units for each of a plurality of dispersed storage networks (DSNs) in a computing system network, wherein a set of the sets of DS unit stores an error coded data file. The method continues with the processing module identifying a reference entity within the computing system network. The method continues with the processing module determining first data access performance information between the reference entity and a first one of the sets of DS units and determining second data access performance information between the reference entity and a second one of the sets of DS units for each of the plurality of DSNs. The method continues with the processing module storing the first and second data access performance information for each of the plurality of DSNs to produce system data access performance information.

Abstract: Systems and methods are provided for correcting absorb sets and near absorb sets in the (2048, 1723) LDPC code used in 10GBase-T transmission systems. Absorb sets and near absorb sets correspond to error patterns that, due to the structure and imperfections of the LDPC code, cannot easily be corrected using standard correction methods. To correct these error patterns, a set of failed syndrome checks associated with the error pattern can be identified, and the 4, 8, 12, or 16 error patterns associated with the failed syndrome checks can be determined. The codeword may then be corrected based on the error pattern that most likely occurred.

Abstract: Apparatus having corresponding methods and tangible computer-readable medium embodying instructions executable by a computer to perform the methods comprise: a receiver adapted to receive a signal representing an input code block, wherein the input code block represents information encoded with a (N, K) difference-set cyclic code, wherein the input code block includes N symbols, and wherein the N symbols represent K bits of the information; an estimator adapted to estimate a signal-to-noise ratio of the signal; a raised-threshold majority-logic decoder adapted to decode the input code block according to a raised-threshold majority-logic decoding algorithm when the signal-to-noise ratio does not exceed a first predetermined threshold; and a variable-threshold majority-logic decoder adapted to decode the input code block according to a variable-threshold majority-logic decoding algorithm when the signal-to-noise ratio exceeds the first predetermined threshold.

Abstract: Low-Density Parity-Check (LDPC) codes offer error correction at rates approaching the link channel capacity and reliable and efficient information transfer over bandwidth or return-channel constrained links with data-corrupting noise present. LDPC codes also offer error correction performance approaching channel capacity exponentially fast in terms of the code length, linear processing complexity, and parallelism that scales with the code length. They also offer challenges relating to the decoding complexity of the binary error-correction codes themselves and error floors limiting achievable bit-error rates. A new Relaxed Half-Stochastic (RHS) decoding algorithm is presented that reduces decoding complexity for high decoding throughput applications. The RHS algorithm uses an approach based on stochastic decoding algorithms but differs significantly from the conventional approaches of LDPC decoder implementation.

Abstract: This is a method for controlling the decoding of a LDPC encoded codeword composed of several digital data, said LDPC code being represented by a bipartite graph between check nodes (CN1) and variable nodes (VNi). Said method comprises updating messages exchanged iteratively between variable nodes (VN1) and check nodes (CN1). Said method comprises, at each iteration, calculating for each variable node a first sum (?n) of all the incident messages (?i) received by said variable node and the corresponding digital data (?ch) and calculating a second sum (VNRnew) of all the absolute values of the first sums (?n), and stopping the decoding process if the second sum (VNRnew) is unchanged or decreases within two successive iterations and if a predetermined threshold condition is satisfied.

Abstract: Systems and methods for data loss protection are presented. In one embodiment, a data loss protection switch includes a first port, a second port, an error threshold management component and a multiplexer. Components of the data loss protection switch cooperatively operate to efficiently protect data. The first port receives information from a first data stream. The second port receives data from a second data stream. The error threshold management component analyzes errors in the first data stream and the second data stream. The multiplexer is controlled by the error threshold management component and selects among the first and second data streams based on the analysis.

Abstract: Disclosed is a method and communication device for suppressing interference. The method comprises performing, with a turbo decoder (314), at least one turbo decoding attempt (1106) on a received signal (1104). The turbo decoding attempt generates at least one whole word code bit therefrom (1108). The whole word code bit (1108) corresponds to a group of bits comprising a transmitted symbol. The method determines if the whole word code bit (1108) has a confidence level exceeding a given threshold (1110). If the whole word code bit (1108) does have a confidence level exceeding the given threshold, the whole code word bit is selected for use in data symbol recovery (1114).

Abstract: A method begins by a processing module determining whether to error encode broadcast data. The method continues with the processing module encoding a portion of the broadcast data using an error coding storage dispersal function to produce a set of encoded broadcast data slices, determining whether to compress the set of encoded broadcast data slices for the set of encoded broadcast data slices, and when the set of encoded broadcast data slices is to be compressed, selecting a subset of encoded broadcast data slices of the set of encoded broadcast data slices, when the broadcast data is to be error encoded.

Abstract: A majority voting Viterbi decoder includes a branch metric calculator (BMC) for measuring a difference between a received symbol and a reference symbol and outputting branch metrics from the difference; an add-compare-selection (ACS) unit for determining an optimal path using the branch metrics; a survival path memory unit for outputting decoded symbols by performing decoding based on the optimal path; and a majority voting unit for determining a final decoded symbol by performing majority voting for the decoded symbols output from the survival path memory unit. Accordingly, by adding the majority voting unit, a decoding depth can be reduced without the loss of an encoding gain required in a system, and by reducing the decoding depth, miniaturization is possible, power consumption can be reduced, and a processing delay in a memory can be minimized.

Abstract: A pseudo-orthogonal code generator is provided. The pseudo-orthogonal code generator simplifies overall configuration and provides a more efficient operating speed by implementing a pseudo-orthogonal code generator using combined circuits instead of using a read only memory (ROM) circuit. The pseudo-orthogonal code generator reduces its overall size by reducing gate area.

Abstract: Disclosed is an apparatus and method for increasing the error correction capabilities of a receiver circuit that receives a data stream of encoded data symbols that are encoded with a linear block code. Analog and digital comparator circuits are used to detect laser clipping or analog to digital converter overloading. Corrupted symbols are detected by comparing in-phase and/or quadrature phase baseband signals with pre-determined threshold limits that indicate that the in-phase and quadrature phase signals have exceeded the normal signal trajectory of an unimpaired signal. Corrupted symbols may also be detected by determining that the laser has been clipped. Corrupted symbols are marked for erasure prior to decoding and error correction. Erasure of corrupted signals increases the error correction capabilities of the decoder circuit.

Abstract: Data is read from a nonvolatile memory array using one or more read voltages that are adjusted during memory life. Programming target voltages and read voltages may be adjusted together over memory life to map memory states to an increasingly wide threshold window. Individual memory states are mapped to sub-ranges that are made wider, reducing errors.