Abstract: Aspects of the disclosed technology include techniques and mechanisms for correcting uncorrectable memory errors in DIMMs using erasure code. An uncorrectable error may be detected as a result of a read transaction on a memory address within a DRAM device on a DIMM. The data stored in the memory address may be inverted to produce reference data and the reference data may be written back to the memory address. A subsequent read transaction may be executed on the memory address, and the data read from the memory address may be compared to the reference data written to the memory address. Based on determining the data read from the memory address is different from the reference data written to the memory address, the data within the memory address may be corrected using erasure code capability and the corrected data may be written back to the memory address.

Abstract: A memory device includes a plurality of first cell blocks configured to store first data; a second cell block configured to store second data; a third cell block configured to store third data; a repair information storage circuit configured to output, based on repair information stored therein, a repair use signal corresponding to an input address; and an error correction circuit configured to: receive the second data as a first error correction code from the second cell block while selectively receiving, according to the repair use signal, the third data as a second error correction code from the third cell block, and correct errors in the first data from the first cell blocks using the first and second error correction codes.

Abstract: A memory system and a data processing system including the memory system may manage a plurality of memory devices. For example, the data processing system may categorize and analyze error information from the memory devices, acquire characteristic data from the memory devices and set operation modes of the memory devices based on the characteristic data, allocate the memory devices to a host workload, detect a defective memory device among the memory devices and efficiently recover the defective memory device.

Abstract: Methods, systems, and devices for associative computing for error correction are described. A device may receive first data representative of a first codeword of a size for error correction. The device may identify a set of content-addressable memory cells that stores data representative of a set of codewords each of which is the size of the first codeword. The device may identify second data representative of the first codeword in the set of content-addressable memory cells. Based on identifying the second data, the device may transmit an indication of a valid codeword that is mapped to the second data.

Abstract: Data associated with a write request is stored at a storage device of multiple solid-state storage devices. A determination as to whether the data stored at the storage device is readable is made by determining whether a number of subsequent programming operations have been performed since the data was stored at the storage device. A notification that the stored data is readable from the storage device is generated upon determining that the data is readable.

Abstract: Apparatus and method for a die kill and recovery sequence for a non-volatile memory (NVM). Data are stored in the NVM as data sets in garbage collection units (GCUs) that span multiple semiconductor dies. A die failure management circuit is configured to detect a die failure event associated with a selected die, and to generate a recovery strategy to accommodate the detected die failure event by selecting recovery actions to be taken in a selected sequence to maintain a current level of data transfer performance with a client device. The selected recovery actions are carried out in the selected sequence to transfer at least a portion of the user data stored in the selected die to a new replacement die, after which the selected die is decommissioned from further use. The NVM may be a flash memory of a solid-state drive (SSD).

Abstract: Systems and methods for specifying storage media types in write commands executable by storage devices are disclosed. An example system comprises: a plurality of memory devices and a controller operatively coupled to the memory devices, the controller configured to: receive a write command specifying a data item and an identifier of a data stream comprising the data item; determine, by parsing the identifier of the data stream, a data stream attribute shared by data items comprised by the data stream; identify, based on the data stream attribute, a memory device managed by the controller; and transmit, to the memory device, an instruction specifying the data item.

Abstract: The present disclosure provides a method for controlling a data storage device. The method includes: storing a first data in a first area of a memory of the data storage device; storing a second data in a second area of the memory, wherein the second data is associated with the first; reading the first data and the second data via a first communication interface; and in response to the read first data and second data, generating a first output signal.

Abstract: A data processing system comprises a memory, a processing unit, a MMU operable to process memory transactions for the processing unit; and an error-detecting circuit located between the MMU and the memory. The MMU is configured to determine from respective memory address mappings corresponding memory addresses to which memory transaction applies. The determined memory addresses comprise a first part representing a memory location and a second part representing an error-detecting code generated using the first part of the memory address. The error-detecting circuit can then check using the error-detecting code for the memory address whether the memory address received by the error-detecting circuit is valid.

Abstract: In a data processing device comprising a memory controller controlling writing/reading of data to/from the memory, a processor requesting writing/reading of data, and an error detection module requesting writing/reading of data to/from the memory controller in accordance with a request from the processor, an error detection module calculates a first error detection code of the first data having a write request from the processor, reads the second data having a read request from the processor from the memory, calculates a second error detection code from the read data, compares the first error detection code and the second error detection code, and transmits the result of the comparison to the external module.

Abstract: Methods, systems, and apparatuses for memory array bit inversion are described. A memory cell (e.g., a ferroelectric memory cell) may be written with a charge associated with a logic state that may be the inverse of the intended logic state of the cell. That is, the actual logic state of one or more memory cells may be inverted, but the intended logic state of the memory cells may remain unchanged. Different sets of transistors may be configured around a sense component of a cell to enable reading and writing of intended and inverted logic states from or to the cell. For instance, a first set of transistors may be used to read the logic state currently stored at a memory cell, while a second set of transistors may be used to read a logic state inverted from the currently stored logic state.

Abstract: A memory component and a controller communicate commands and data with each other The commands to activate and then access data, and the data itself, are all communicated between a controller and the memory component at different times. The controller and memory component each calculate a respective error detecting code (EDC) values on the activate command information (e.g., bank address and row address) and store them indexed by the bank address. When the memory component is accessed, retrieved EDC values are combined with EDC values calculated from the access command information, and the data itself. The memory component transmits its combined EDC value to the controller for checking.

Abstract: The present invention provides a method for controlling a data storage device. The data storage device includes a flash memory controller and a flash memory module. The flash memory controller has a first buffer memory and a second buffer memory. The memory module has at least a first memory portion and a second memory portion. The method includes: receiving a first data from a host device; storing the first data in the first buffer memory; transmitting the first data to the first memory portion of the flash memory module from the first buffer memory; and transmitting the first data to a host memory buffer in the host device from the first buffer memory. The first data corresponds to at least a portion of a second data to be written to the second memory portion.

Abstract: Failure of a processing unit that processes a plurality of information pieces is discovered in a short time.

Abstract: One embodiment provides a computer system. The computer system comprises: a plurality of storage devices; and a first component functioning both as a network interface card and as an access switch, wherein the first component is configured to manage connections to the plurality of storage devices. A respective storage device comprises: an Ethernet port coupled to the first component; at least one microprocessor; a plurality of PCIe lanes; and a plurality of storage drives with non-volatile memory.

Abstract: A memory component and a controller communicate commands and data with each other The commands to activate and then access data, and the data itself, are all communicated between a controller and the memory component at different times. The controller and memory component each calculate a respective error detecting code (EDC) values on the activate command information (e.g., bank address and row address) and store them indexed by the bank address. When the memory component is accessed, retrieved EDC values are combined with EDC values calculated from the access command information, and the data itself. The memory component transmits its combined EDC value to the controller for checking.

Abstract: The present disclosure relates to methods for selecting or reselecting a cell from among a plurality of cells. The present disclosure is also providing mobile stations for performing these methods, and computer readable media the instructions of which cause the mobile station to perform the methods described herein. For this purpose, the mobile station is detecting cells which are candidates (i.e. candidate cells) for selection or reselection, utilizing either the normal coverage mode or the enhanced coverage mode. Further, the mobile station is selecting or reselecting a cell among the candidate cells detected, utilizing either the normal coverage mode or the enhanced coverage mode. The mobile station is performing the detection and the selection or reselection on the basis of stored information indicating whether or not at least one of the candidate cells supports that the detection and the selection or reselection utilize the enhanced coverage mode.

Abstract: Techniques for transitioning between thread-confined memory segments and shared memory segments are disclosed. The system may instantiate a confined memory segment view. The confined memory segment view confines access to a memory segment to a particular thread. The system may further receive a request to change access permissions for the confined memory segment to allow access by a first set of one or more threads. Responsive to receiving the request to change access permissions for the confined memory segment, the system may instantiate a new memory segment view, wherein the new memory segment view permits access to the memory segment by the first set of one or more threads. The system may also copy metadata from the confined memory segment view to the new memory segment view. The system may de-allocate the memory segment in response to determining that there are no memory segment views associated with the memory segment.

Abstract: Systems, methods, and computer-readable media are provided for reusing execution environments and code of serverless functions while ensuring isolation in serverless computing environments. In some examples, a method can include, in response to a first request to run a serverless function, executing, at an execution environment on a network, computer-readable code configured to perform the serverless function; after the computer-readable code has executed, modifying a pointer to an area of memory used to store a first state of the serverless function to reference a different area of memory; in response to a second request to run the serverless function, reusing, at the execution environment, the computer-readable code to perform the serverless function; and based on the pointer referencing the different area of memory, using the different area of memory to store a second state of the serverless function.

Abstract: The present embodiments provide a stacked memory apparatus and a repairing method thereof which store information about a spare resource in a pre-bond process, check a spare resource available in a post-bond process, correct an error through an error correction code, and variably use the same number of spare resources to additionally ensure a number of spare resources in the post-bond process, thereby improving a yield.

Abstract: A memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory stores a multidimensional error correction code in which each of a plurality of symbol groups is encoded by both a first component code and a second component code. The memory controller reads the error correction code from the nonvolatile memory, executes a first decoding process using the first component code and the second component code, and when the first decoding process fails, executes a second decoding process on an error symbol group. The second decoding process includes a process of selecting the positions of a plurality of symbols whose values included in the error symbol group are to be inverted according to a decision rule. The decision rule includes a rule for cyclically shifting a position selected for the second decoding process at to decide the position for the second decoding process at the next time.

Abstract: A storage device includes a nonvolatile memory including a plurality of physical blocks, a communication interface connectable to a host, and a controller. The controller is configured to generate metadata of host data, which include user data and metadata of the user data, and write, in a physical block of the nonvolatile memory, the metadata of the host data, the metadata of the user data, and the user data continuously in this order, when the host data are received through the communication interface in association with a write command.

Abstract: A memory device, a memory system, and/or a method of operating a memory system includes measuring, using processing circuitry, an erase program interval (EPI) of a memory group included in a non-volatile memory (NVM), the EPI being a time period from an erase time point to a program time point of the memory group, determining, using the processing circuitry, a plurality of program modes based on a number of data bits stored in each memory cell of the memory group, selecting, using the processing circuitry, a program mode for the memory group from the plurality of program modes, based on the measured EPI of the memory group, and performing, using the processing circuitry, a program operation on the memory group corresponding to the selected program mode.

Abstract: A memory system apparatus may be provided. The memory system may have memory controller. The memory controller may be configured to perform a scrambling operation before an error correction code (ECC) operation is performed.

Abstract: A memory device that performs internal ECC (error checking and correction) can treat an N-bit channel as two N/2-bit channels for application of ECC. The ECC for an N/2-bit channel is simpler than the ECC for N bits, and thus, each N/2-bit portion can be separately correctable when treated as two N/2-bit portions. The memory device can include an additional hardware for the application of ECC to the channel as two sub-channels. For example, the memory device can include an additional subarray to store ECC bits for the internal ECC to enable the application of ECC to two sub-channels of the N-bit channel. The memory device can include an additional driver to access the additional subarray when applied.

Abstract: Embodiments provide one write operation circuit, which includes: a serial-to-parallel conversion circuit that performs serial-to-parallel conversion on a first DBI data of a DBI port to generate a second DBI data for transfer by a DBI signal line, and that generates an input data of a data buffer module depending on the second DBI data; a data buffer module that determines whether to flip a global bus depending on the input data of the data buffer module; the DBI decoding module that decodes a global bus data according to the second DBI data, and writes the decoded data into a memory bank, where decoding includes determining whether to flip the global bus data; and a precharge module that is coupled to a precharge signal line and that sets the initial state of the global bus to high.

Abstract: A datum is written to a memory, by splitting a binary word, representative of the datum and an error correcting or detecting code, into a first part and a second part. The first part is written at a logical address in a first memory circuit. The second part is written at the logical address in a second memory circuit. The error correcting or detecting code is dependent on both the datum and the logical address.

Abstract: A memory system may include: a memory device including a plurality of storage regions; and a controller. The controller may be coupled between a host and the memory device, and perform a read retry operation when a read error occurs in any one of the storage regions based on occurrence possibilities for a plurality of different type of defects in any one storage region where a read error occurred.

Abstract: Systems, methods, and computer-readable media are provided for reusing execution environments and code of serverless functions while ensuring isolation in serverless computing environments. In some examples, a method can include, in response to a first request to run a serverless function, executing, at an execution environment on a network, computer-readable code configured to perform the serverless function; after the computer-readable code has executed, modifying a pointer to an area of memory used to store a first state of the serverless function to reference a different area of memory; in response to a second request to run the serverless function, reusing, at the execution environment, the computer-readable code to perform the serverless function; and based on the pointer referencing the different area of memory, using the different area of memory to store a second state of the serverless function.

Abstract: A failure prediction apparatus includes a memory and a processor coupled to the memory. The processor acquires a score based on an output of each of a plurality of sensors associated with each of a plurality of circuit arrangement regions, in each of the plurality of circuit arrangement regions a logic circuit constructed by programming is arrangeable, and performs a process of making a determination on a possibility of an occurrence of a failure with respect to each of the plurality of circuit arrangement regions based on the score for each of the circuit arrangement regions.

Abstract: Techniques for managing power usage in a memory subsystem are described. An operation type of each of a plurality of operations queued against one or more of a plurality of memory components is obtained. It is determined that at least two of the plurality of operations can be performed in parallel and that a first configuration of the plurality of memory components does not allow the at least two operations to be performed in parallel, the first configuration including a first set of power management cohorts. An interconnection of the plurality of memory components is reconfigured to change from the first configuration to a second configuration of the of the plurality of memory components, the second configuration including a second set of power management cohorts that allow the at least two operations to be performed in parallel.

Abstract: A system including a user interface, a memory, and a processor configured to perform operations including receiving memory scrambling information including address scrambling information and data scrambling information, and associating one or more address bus bits of a plurality of address bus bits with an address grouping of a plurality of address groupings based on the address scrambling information is disclosed. In an embodiment, the address grouping corresponds to at least one address segment of a plurality of address segments. The operations include determining an error correction code for the at least one address segment that includes one or more address check bits. The operations include generating a physical layout of memory components based on the memory scrambling information. The memory components include at least one of the plurality of address bus bits, and the one or more address check bits.

Abstract: A non-volatile dual in-line memory module (NVDIMM) instantiates first and second partitions of non-volatile memory. The first partition is reserved and is not accessible to an operating system instantiated. The second partition is accessible to the operating system. A processor detects a first bad memory location in the second partition, stores a first system physical address of the first bad memory location to a system bad memory locations list, and stores a first DIMM physical address of the first bad memory location to a first NVDIMM bad memory locations list in the first partition.

Abstract: An example method of determining storage operation parameters based on data stream attributes may include: receiving, by a controller, a write command specifying a data item and an identifier of a data stream comprising the data item, wherein a part of the identifier of the data stream encodes a data attribute shared by data items comprised by the data stream; determining, using the data attribute, a storage operation parameter; and transmitting, to a memory device, an instruction specifying the data item and the storage operation parameter.

Abstract: An error check and scrub (ECS) mode enables a memory device to perform error checking and correction (ECC) and count errors. An associated memory controller triggers the ECS mode with a trigger sent to the memory device. The memory device includes multiple addressable memory locations, which can be organized in segments such as wordlines. The memory locations store data and have associated ECC information. In the ECS mode, the memory device reads one or more memory locations and performs ECC for the one or more memory locations based on the ECC information. The memory device counts error information including a segment count indicating a number of segments having at least a threshold number of errors, and a maximum count indicating a maximum number of errors in any segment.

Abstract: A controller performs background reads of multiple physical pages of a selected physical block of a non-volatile memory. The controller detects asymmetric transient errors in a physical page among the multiple physical pages based on a bit error rate (BER) observed in the background read of the physical page. In response to detecting the asymmetric transient errors, the controller mitigates the detected asymmetric transient errors by relocating valid logical pages of data from the physical page to another physical block of the non-volatile memory and by retaining valid logical pages of data programmed into other physical pages of the selected physical block.

Abstract: A processor includes a memory-controller that controls an access to a memory which includes through electrode groups and a memory chip including a storage areas connected to each of the through-electrode groups including through-electrodes, and that includes an address-filter circuit that outputs an access address included in a read access request of reading data from the memory, as an error address, a counter that includes counters corresponding to the through-electrode groups and updates a counter value of the counter corresponding to the through-electrode group connected to the storage area indicated by the received error address, a first circuit that outputs area information indicating the storage area connected to the through-electrode group corresponding to the counter having a counter value which is greater than a predetermined value, and a second circuit that outputs an access request to the storage area indicated by the area information output from the first circuit.

Abstract: A memory system includes a nonvolatile memory device, a dynamic random access memory (DRAM) configured to store an address mapping table for an access to the nonvolatile memory device, and a controller configured to store, in the DRAM, the address mapping table that is divided in units of address mapping data, each of the units having a size of an interface of the DRAM, read, from the stored address mapping table, target address mapping data corresponding to a logical address that is received from a host, the target address mapping data including a target parity and physical addresses of the nonvolatile memory device, and perform an error correction on the read target address mapping data, using the target parity.

Abstract: In technique for dividing ECC large in size, plural ECCs of different sizes are required to be managed and control over storage areas of NVM is intricate. In addition, a relatively reliable page (a minimum record unit) and a relatively unreliable page are determined beforehand depending upon which recording method is adopted. However, as dispersion exists in quality among NVMs, it may occur among NVMs that dispersion in an error bit count is great among pages of the same reliability. An NVM controller in a nonvolatile memory (NVM) module divides the ECCCW into N pieces (N: two or a larger integer) of ECCCW portions and records the N pieces of ECCCW portions in N pieces of storage areas out of plural storage areas in one or more NVMs configuring an NVM section.

Abstract: Provided is a storage system in which a plurality of storage controllers communicate with each other and an identifier of each storage controller is determined. The storage system includes a plurality of controllers that receive and process an input and output request specifying any of a plurality of volumes from an external device, and a plurality of switches each having a plurality of ports. The plurality of controllers are connected in parallel to the plurality of switches and communicate with each other via the plurality of switches. Each of the plurality of controllers acquires a plurality of port identifiers identifying a plurality of connected ports from the connected switches, and determines a controller identifier in the storage system based on the acquired plurality of port identifiers.

Abstract: A memory device is provided and includes a status register, a memory array, a memory controller, an interface control circuit, and a write control logic circuit. The status register stores a plurality of status bits and a first threshold. The interface control circuit is controlled by the memory controller to perform a data program/erase operation on the memory array and re-program/re-erase the memory array in a retry mode when the data program/erase operation is not complete. The write control logic circuit counts the number of times the memory array is re-programmed/re-erased in the retry mode to generate a retry counting value, compares the retry counting value with the first threshold to generate a result signal. The status register updates a result bit included in the status bits according to the result signal. The memory controller determines whether the data program/erase operation is successful according to the result bit.

Abstract: A memory system includes a nonvolatile memory device, a dynamic random access memory (DRAM) configured to store an address mapping table for an access to the nonvolatile memory device, and a controller configured to store, in the DRAM, the address mapping table that is divided in units of address mapping data, each of the units having a size of an interface of the DRAM, read, from the stored address mapping table, target address mapping data corresponding to a logical address that is received from a host, the target address mapping data including a target parity and physical addresses of the nonvolatile memory device, and perform an error correction on the read target address mapping data, using the target parity.

Abstract: The present disclosure generally relates to solid state storage device and techniques for conserving storage capacity associated therewith. Several embodiments are presented, including a data storage device, data storage controller, and methods for using the same are provided in the subject disclosure. A data storage device includes: a plurality of memory devices, a controller coupled to the plurality of memory devices and configured to program data to and read data from the plurality of memory devices, a memory including a logical-to-physical address translation map configured to enable the controller to determine a physical location of stored data in the plurality of memory devices, where the logical-to-physical address translation map contains at least one entry that merges at least two addresses that map, respectively, to at least two physical locations in the plurality of memory devices, where the controller is configured to encode each merged entry with an error-correcting code.

Abstract: A method for execution by a computing device of a dispersed storage network includes obtaining resource information for a subset of storage units of a storage unit pool. W available storage units of the storage unit pool are identified in response to receiving a store data request. W choose S combinations of selecting S number of storage units of the W available storage units are identified. A plurality of rating levels is calculated based on the resource information, where each of the plurality of rating levels are assigned to a corresponding combination of the W choose S combinations. One combination of the W choose S combinations is selected based on the plurality of rating levels. Storage of data of the store data request is facilitated utilizing the S number of storage units of the selected one combination.

Abstract: A method jointly estimates a state of a vehicle including a velocity and a heading rate of the vehicle and a state of stiffness of tires of the vehicle including at least one parameter defining an interaction of at least one tire of the vehicle with a road on which the vehicle is traveling. The method uses the motion and measurement models that include a combination of deterministic component independent from the state of stiffness and probabilistic components dependent on the state of stiffness. The method represents the state of stiffness with a set of particles. Each particle includes a mean and a variance of the state of stiffness defining a feasible space of the parameters of the state of stiffness.

Abstract: Disclosed herein are system, method, and computer program product embodiments for accessing data of a memory. A method embodiment operates by receiving one or more requests for data stored across at least a first memory area and a second memory area of a memory. The method continues with performing, by at least one processor, a wrapped read of data within a first memory area of the memory. The method then performs, by the at least one processor, a continuous read of data within a second memory area of the memory, the second memory area being adjacent to the first memory area. The continuous read starts at a first boundary of the second memory area, and is performed automatically after the wrapped read of data within the first memory area.

Abstract: In a memory system in an embodiment, in a case of normal operation, a control unit returns a write completion response upon completion of reception of write data from a host, and writes the write data into nonvolatile memory in a multiple values. In a case of unordinary power-off, changeover to operation using a backup battery is conducted and the control unit writes dirty data that is not completed in writing into the nonvolatile memory, into the nonvolatile memory with two values. When next boot, the control unit reads the dirty data from the nonvolatile memory into the volatile memory, and thereafter writes the dirty data into the nonvolatile memory in a multiple values.

Abstract: A method for execution by a processing system in dispersed storage and task network (DSTN) that includes a processor, includes: identifying a slice name of a slice in error of a set of slices stored in a set of dispersed storage (DS) units; identifying a number of slice errors of the set of slices; generating a queue entry that includes the slice name of the slice in error, a rebuilding task indicator, an identity of the set of slices, and the number of slice errors; identifying a rebuilding queue based on the number of slice errors, wherein the rebuilding queue is associated with one of: the set of DS units or another set of DS units; and facilitating storing the queue entry in the identified rebuilding queue.

Abstract: Disclosed herein are systems and methods for electronically tagging a video component (VC) in a video package. One example method includes the steps of: (i) receiving a video package; (ii) identifying a position of each of multiple video sections (VS) in the received video package; (iii) identifying a type of at least a portion of the VSs having identified positions, wherein at least one VS is identified as having a show-segment VC type; (iv) determining a total duration of the VSs identified as having a show-segment VC type; (v) determining a total count of the VSs identified as having a show-segment VC type; (vi) responsive to determining that the determined total duration is within a threshold range of a predetermined duration, associating tagging data with the received video package, wherein the tagging data indicates the position and type of each VS identified as having a show-segment VC type.

Abstract: A method of rebuilding data stored as encoded data slices in a dispersed storage network (DSN) includes using a scanning module to identify a slice name of a slice in error of a set of slices stored in a set of dispersed storage (DS) units. The number of erroneous slices in the set of slices is also identified. A queue entry that includes the following items is generated: the slice name of the slice in error; a rebuilding task indicator; an identifier of the set of slices; and the number of slice errors. Additionally, a vault source name is generated based on the number of slice errors. The queue entry is stored in a rebuilding queue at the same or another set of DS units, using the vault source name. A rebuilding module facilitates rebuilding the slice in error.