Memory Access Patents (Class 714/763)
  • Patent number: 11216443
    Abstract: An apparatus in one embodiment comprises at least one processing device comprising a processor coupled to a memory. The processing device is configured, in a first phase of a given write operation of a data integrity test process, to associate with each of a plurality of pages of the given write operation at least one additional field having a designated signature, and in a second phase of the given write operation, to modify the signature of the additional field for each of the pages. The processing device is further configured, in a given read operation of the data integrity test process, to determine integrity of each of at least a subset of the pages based at least in part on the signature of its associated additional field. The data integrity test process may be configured to confirm consistency of the pages written by the given write operation relative to a corresponding point-in-time replica.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: January 4, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: David Meiri, Anton Kucherov
  • Patent number: 11200114
    Abstract: A system is provided for performing error correction in memory. During operation, the system can receive a memory access request from a host processor. The system can then compare a memory address specified in the memory access request with a set of entries in an error correction code (ECC) mapping table. In response to the system determining that the memory address corresponds to at least one entry in the ECC mapping table, the system may determine, based on value in the counter field, whether the memory address belongs to a first portion or a second portion of the address range specified in the ECC mapping table entry. The system can then select a current ECC mode when the memory address belongs to the first portion; and select a previous ECC mode when the memory address belongs to the second portion. The system may then process the memory access request based on the selected ECC mode.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: December 14, 2021
    Assignee: Alibaba Group Holding Limited
    Inventor: Jian Chen
  • Patent number: 11194658
    Abstract: A semiconductor device of an embodiment includes an ECC decoding processing circuit configured to perform ECC decoding on ECC frame data in a lateral direction of a product code frame, an RS decoding processing circuit configured to perform Reed-Solomon (RS) decoding on second frame data in a longitudinal direction of the product code frame, a memory M0 in which a syndrome generated for the ECC frame data decoded is stored, a memory M1 in which an RS syndrome generated for ECC frame data for which the ECC decoding has been successful is stored, and a memory D in which ECC frame data for which the ECC decoding has been failed is stored as frame data which cannot be corrected through decoding, and frame collection processing, and iterative correction processing of performing RS decoding on the uncorrected frame data collected in the frame collection processing are executed.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: December 7, 2021
    Assignee: Kioxia Corporation
    Inventors: Ryo Nogami, Takahiro Fujiki, Kosuke Morinaga, Naoki Wada, Atsushi Takayama
  • Patent number: 11194643
    Abstract: Techniques for access operation status signaling for memory systems are described. In some examples, a memory system may respond to access commands from a host system by performing access operations such as read or write operations. In accordance with examples as disclosed herein, a system may be configured to support access operation status signaling between a host system and a memory system, which may improve the ability of the system to adapt to various access scenarios, including when access operation completion is delayed. For example, when a memory system is performing an error recovery or media management operation, the memory system may indicate that the error recovery or media management operation is being performed or is otherwise ongoing. Such status signaling may indicate that the memory system is actively performing operations, which may be used to inhibit a reset or reinitialization by a host system.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: December 7, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Qing Liang, Jonathan S. Parry, Giuseppe Cariello, Deping He
  • Patent number: 11188564
    Abstract: Multiple shippable storage devices may be used for a bulk data transfer, local storage, and remote synchronization to a remote storage service. A storage service provider ships multiple shippable storage devices to a client, which are then attached to the client network. The client data on the client network is transferred to the shippable storage devices according to a redundancy encoding scheme. A subset of the shippable storage devices are then shipped back to the remote storage provider to store a copy of the client data at the remote storage service. The remainder of the shippable storage devices are sufficient in number to store the client data. When the client data is updated on the shippable storage devices, the shippable storage devices send an update via network transmission to the remote storage service. The remote storage service then updates the copy of the client data.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: November 30, 2021
    Assignee: Amazon Technologies, Inc.
    Inventor: Frank Charles Paterra
  • Patent number: 11189360
    Abstract: A system includes a memory device that includes a first memory region to store first data at first addresses, and a second memory region to store, on command, either second data at second addresses or error correction code check bits associated with the first data at third addresses.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: November 30, 2021
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Jean-Michel Gril-Maffre, Christophe Eva
  • Patent number: 11182240
    Abstract: Examples include techniques to improve error correction using an exclusive OR (XOR) rebuild scheme that includes two uncorrectable codewords. Examples include generation of soft XOR codewords using bits of correctable codewords to rebuild a codeword read from a memory that has uncorrectable errors and adjust bit reliability information to generate a new codeword having correctable errors. Examples also include techniques to prevent mis-correction due to read reference voltage shifts using non-linear transformations.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: November 23, 2021
    Assignee: Intel Corporation
    Inventors: Santhosh K. Vanaparthy, Zion S. Kwok, Ravi H. Motwani
  • Patent number: 11176988
    Abstract: A control method for a memory is provided. In a test mode, a tendency check operation is performed for a cell array to define the tendency of the cell array. In a write mode: receiving external data; determining the tendency of the external data; comparing the tendency of the external data and the tendency of the cell array; inverting the external data and writing the inverted external data into the cell array in response to the tendency of the external data being different from the tendency of the cell array; and writing the external data into the cell array in response to the tendency of the external data being the same as the tendency of the cell array.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: November 16, 2021
    Assignee: WINBOND ELECTRONICS CORP.
    Inventor: Wen-Chiao Ho
  • Patent number: 11169874
    Abstract: A memory system includes; a memory device, a memory controller including a first interface, a second interface, and a first data processor having a first error correction code (ECC) engine, and a field programmable gate array (FPGA) including a third interface connected to the first interface, a fourth interface connected to the second interface, a fifth interface connected to an external host, and a second data processor having a second ECC engine. The memory controller may configure a normal write operation path or highly reliable write operation path.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: November 9, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Min Shin, Hong-Rak Son
  • Patent number: 11171670
    Abstract: A parity generation logic circuit includes a first parity generation part and a second parity generation part. The first parity generation part is configured to generate a first parity in a first error correction mode having a first error correction capability for original data. The second parity generation part is configured to generate a second parity using the first parity in a second error correction mode having a second error correction capability.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: November 9, 2021
    Assignee: SK hynix Inc.
    Inventors: Sung Eun Lee, Young Ook Song
  • Patent number: 11165440
    Abstract: Systems and methods are provided for an erasure coding object storage system. One method may comprise receiving an object for storing in an erasure coding object storage system, partitioning the object into a plurality of chunks including a first chunk and a second chunk. The first chunk may have a first chunk size and fall into a first bucket, the second chunk may have a second chunk size equal to the first chunk size multiplied by a ratio q that is larger than one and fall into a second bucket. The method may further comprise encoding the first bucket using a regenerating code with the first chunk size, encoding the second bucket using the regenerating code with the second chunk size and storing the encoded first and second buckets in a plurality of nodes of the erasure coding object storage system.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: November 2, 2021
    Assignee: TSINGHUA UNIVERSITY
    Inventors: Yongwei Wu, Yingdi Shan, Kang Chen, Tuoyu Gong
  • Patent number: 11164652
    Abstract: A memory sub-system configured to encode data using an error correcting code and an erasure code for storing data into memory cells and to decode data retrieved from the memory cells. For example, the data units of a predetermined size are separately encoded using the error correcting code (e.g., a low-density parity-check (LDPC) code) to generate parity data of a first layer. Symbols within the data units are cross encoded using the erasure code. Parity symbols of a second layer are calculated according to the erasure code. A collection of parity symbols having a total size equal to the predetermined size can be further encoded using the error correcting code to generate parity data for the parity symbols.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: November 2, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Sanjay Subbarao, James Fitzpatrick
  • Patent number: 11157037
    Abstract: A multi-layer time-interleaving (TI) device and method of operation therefor. This device includes a plurality of TI layers configured to receive a plurality of input clock signals and to output a plurality of output clock signals, each of which can be configured to drive subsequent devices. The layers include at least a first and second layer including a fine-grain propagation device and a barrel-shifting propagation device configured to retime the plurality of input clock signals to produce divided output clock signals. The device can include additional barrel-shifting propagation devices to time interleave an initial two layers to produce one or more additional layers. Using negative phase stepping, the plurality of output clock signals is produced with optimal timing margin and synchronized on a single clock edge.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: October 26, 2021
    Assignee: MARVELL ASIA PTE, LTD.
    Inventors: Ray Luan Nguyen, Geoffrey O. Hatcher
  • Patent number: 11158386
    Abstract: A memory system includes a memory device including a plurality of memory cells, and a controller configured to access the plurality of memory cells. The controller includes a data read block configured to read first data from one or more pages included in first memory cells, determine a target memory cell subject to a compensation based on the first data, and read second data from one or more pages of second memory cells adjacent to the target memory cell, and an equalizer configured to convert the second data into symbol interfering data, check a probability of the first data from a lookup table according to the symbol interfering data, and determine the compensation on the first data based on the probability.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: October 26, 2021
    Assignees: SK hynix Inc., Korea Advanced Institute of Science and Technology
    Inventors: Suk Kwang Park, Jaekyun Moon, Minsu Choi
  • Patent number: 11150814
    Abstract: There is a method and a corresponding system for performing partial write operations to memory. This method and corresponding system utilizes an XOR operation to generate error checking bits. Once the error checking bits are generated, they are then used for error checking a set of data bits so that these data bits can be written to memory.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: October 19, 2021
    Assignee: International Business Machines Corporation
    Inventor: Michael John Palmer
  • Patent number: 11144449
    Abstract: An operation method of a memory system includes a memory device including plural level memory cells. The operation method includes allocating a physical address according to a physical address allocation scheme which is determined based on an attribute of a write command; and performing a write operation on the allocated physical address.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: October 12, 2021
    Assignee: SK hynix Inc.
    Inventor: Eu-Joon Byun
  • Patent number: 11144246
    Abstract: A memory system includes a nonvolatile memory device including a plurality of memory blocks and a controller configured to control the nonvolatile memory device. The controller determines, as an available bad block, a memory block having data storage reliability equal to or greater than a first reference value, included in the plurality of memory blocks, determines write data to be stored in the nonvolatile memory device as first data which is required for the memory system to normally operate or second data which does not correspond to the first data, and allocate the write data determined as the second data to the available bad block. The nonvolatile memory device performs a write operation of storing the second data in the available bad block.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: October 12, 2021
    Assignee: SK hynix Inc.
    Inventor: Eu Joon Byun
  • Patent number: 11145357
    Abstract: A memory system, a memory controller and a method for operating a memory system are disclosed. Specifically, by performing soft-decision decoding for data read from some of the plurality of memory cells based on a first optimum read voltage of one or more optimum read voltages, based on reliability values of one or more first threshold voltage sections, and one or more second threshold voltage sections and also based on the first and second threshold voltage sections, it is possible to provide a memory system, a memory controller and a method for operating a memory system, capable of increasing an error correction effect by soft-decision decoding even in the case where threshold voltage distributions of memory cells in which data is stored are degraded.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: October 12, 2021
    Assignee: SK hynix Inc.
    Inventor: Su-Kyung Kim
  • Patent number: 11139029
    Abstract: A programming method for a memory device includes simultaneously starting to program a first plane and a second plane; and bypassing the first plane and keeping programming the second plane when the first plane has been programmed successfully and the second plane has not been programmed successfully yet.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: October 5, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Haibo Li, Chao Zhang
  • Patent number: 11139832
    Abstract: An operating method of a low density parity check (LDPC) decoder, the operating method includes: initially updating codewords to variable nodes; determining an update order in which a plurality of variable node groups are updated, which is determined based on reliability of each of the variable node groups; executing local iterations including update of check nodes associated with a select variable node group among the variable node groups and update of the select variable node group based on the updated check nodes until all the variable node groups are updated based on the update order; performing syndrome check to determine whether LDPC decoding is successful, based on an operation of the updated variable nodes and a parity check matrix.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: October 5, 2021
    Assignee: SK hynix Inc.
    Inventor: Soon Young Kang
  • Patent number: 11133831
    Abstract: A method includes programming data in a block of a storage device, and reading back the programmed data and determining a maximum error count for the block. A code rate index that satisfies correction of the maximum error count for the block is determined. A current code rate index is adjusted to the code rate index that satisfies correction of the maximum error count for the block.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: September 28, 2021
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Shuhei Tanakamaru, Scott McClure, Erich Franz Haratsch
  • Patent number: 11133826
    Abstract: A quasi-cyclic LDPC coding and decoding method and apparatus, and an LDPC coder and decoder. The method includes: determining from a mother basis matrix set a basis matrix used for low density parity check (LDPC) coding (S202), wherein the basis matrix used for LDPC coding includes a first-type element and a second-type element, the first-type element corresponds to an all-zero square matrix, the second-type element corresponds to a matrix obtained by means of a cyclic shift of a unit matrix according to a value of the second-type element, and dimensions of the all-zero square matrix and the unit matrix are equal; and performing LDPC coding on an information sequence to be coded according to the basis matrix used for LDPC coding, and/or performing LDPC decoding on a data sequence to be decoded according to the basis matrix used for LDPC coding (S204).
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: September 28, 2021
    Assignee: ZTE Corporation
    Inventors: Liguang Li, Jun Xu, Jin Xu
  • Patent number: 11126500
    Abstract: Systems and methods for error detection and correction with integrity checking are provided. A method includes first processing both data vector bit values and integrity vector bit values using a single error correction and double error detection (SECDED) code to generate check bit values, where the SECDED code is configured to allow both: (1) a detection and correction of a single error in the data vector values, or (2) an indication of an uncorrectable error, where the uncorrectable error corresponds to more than a single error in the data vector bit values or a single error or a multi-bit error in the integrity vector bit values. The method further includes second processing the check bit values and indicating an uncorrectable error for more than a single error in the data vector bit values or for a single error or a multi-bit error in the integrity vector bit values.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: September 21, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Jay S. Fuller
  • Patent number: 11126626
    Abstract: A system and method for processing a group and aggregate query on a relation are disclosed. A database system determines whether assistance of a heterogeneous system (HS) of compute nodes is beneficial in performing the query. Assuming that the relation has been partitioned and loaded into the HS, the database system determines, in a compile phase, whether the HS has the functional capabilities to assist, and whether the cost and benefit favor performing the operation with the assistance of the HS. If the cost and benefit favor using the assistance of the HS, then the system enters the execution phase. The database system starts, in the execution phase, an optimal number of parallel processes to produce and consume the results from the compute nodes of the HS. After any needed transaction consistency checks, the results of the query are returned by the database system.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: September 21, 2021
    Assignee: Oracle International Corporation
    Inventors: Sabina Petride, Sam Idicula, Nipun Agarwal
  • Patent number: 11099749
    Abstract: A method for erasure detection in a storage cluster is provided. The method includes establishing a connection, via a network, of a storage unit to one of a plurality of storage nodes of a storage cluster and determining, for at least one page of a storage memory of the storage unit, that the at least one page is erased. The storage unit is one of a plurality of storage units configured to store user data in memory of the storage units in accordance with direction from the plurality of storage nodes. The method includes communicating from the storage unit to the one of the plurality of storage nodes that the at least one page is erased.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: August 24, 2021
    Assignee: Pure Storage, Inc.
    Inventors: John Martin Hayes, Hari Kannan, Nenad Miladinovic
  • Patent number: 11093322
    Abstract: A determination is made that bit errors of a selected data chunk stored in a computer memory are unable to be completely corrected using an initial error correction scheme. A plurality of other data chunks sharing a physical layout structure element of the computer memory with the selected data chunk is analyzed to identify one or more likely bit error locations of the selected data chunk aligned with one or more corresponding bit error locations of a threshold number of the analyzed other data chunks. An attempt is made to correct the bit errors of the selected data chunk based on the identified one or more likely bit error locations of the selected data chunk.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: August 17, 2021
    Assignee: Facebook, Inc.
    Inventors: Yu Cai, Daniel Henry Morris
  • Patent number: 11095315
    Abstract: Dynamically adjusting an error correction effort level of a storage device, including: receiving, from a storage array controller, an error correction effort level to perform when attempting to read data from the storage device; identifying that an attempt to read the data resulted in an error; and determining whether an amount of error correction effort level required to attempt to correct the error exceeds the error correction effort level to perform when attempting to read data from the storage device.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: August 17, 2021
    Assignee: Pure Storage, Inc.
    Inventors: John Colgrove, Ethan Miller
  • Patent number: 11088710
    Abstract: A memory controller configured to control a memory module, the memory controller including processing circuitry configured to perform ECC decoding on a read codeword from the memory module using a first portion of a parity check matrix to generate a first syndrome and a second syndrome, determine a type of error in the read codeword based on the second syndrome and a decision syndrome, the decision syndrome corresponding to a sum of the first syndrome and the second syndrome, and output a decoding status flag indicating the type of error.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: August 10, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kijun Lee, Chanki Kim, Sunghye Cho, Myungkyu Lee
  • Patent number: 11080780
    Abstract: The disclosed technologies identify opportunities to display relevant three-dimensional (“3D”) model data within a real-world environment as a user wears a wearable device. The 3D model data can be associated with objects, or items, and the 3D model data rendered for display is relevant in the sense that the items are determined to be of interest to the user and the items fits within the real-world environment in which the user is currently located. For instance, the techniques described herein can recognize items typically found in a kitchen or a dining room of a user's house, an office space at the user's place of work, etc. The characteristics of the recognized items can be identified and subsequently analyzed together to determine preferred characteristics of a user. In this way, the disclosed technologies can retrieve and display an item that correlates to (e.g., matches) the preferred characteristics of the user.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: August 3, 2021
    Assignee: eBay Inc.
    Inventor: Steve Yankovich
  • Patent number: 11074560
    Abstract: Provided are systems and methods for managing storage of machine data. In one embodiment, a method can be provided. The method can include receiving, from one or more data sources, raw machine data; processing the raw machine data to generate processed machine data; storing the processed machine data in a data store; and determining an allocated data size associated with the processed machine data stored in the data store, wherein the allocated data size is the size of the raw machine data corresponding to the processed machine data stored in the data store.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: July 27, 2021
    Assignee: SPLUNK Inc.
    Inventor: Alexander D. Munk
  • Patent number: 11075654
    Abstract: A method for correcting an error of a received signal is provided. The method includes: determining a target degree based upon a length of the received signal; obtaining plural primitive polynomials each having a degree equal to the target degree; selecting one of the primitive polynomials as a target polynomial; defining plural syndromes according to the received signal; generating a group of product values based on the syndromes; obtaining plural coefficient polynomials based on the product values; obtaining monomial trace coefficients based on the coefficient polynomials; generating an error correction value based on the monomial trace coefficients; and correcting the error based on the error correction value.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: July 27, 2021
    Assignee: I SHOU UNIVERSITY
    Inventors: Yao-Tsu Chang, Chong-Dao Lee
  • Patent number: 11068347
    Abstract: A memory controller configured to control a memory module including a plurality of memory devices which constitute a first channel and a second channel includes an error correction code (ECC) engine, and a control circuit configured to control the ECC engine. The ECC engine is configured to generate a codeword including a plurality of symbols by adaptively constructing, based on device information including mapping information, each of the plurality of symbols from a predetermined number of data bits received via a plurality of input/output pads of each of the plurality of memory devices, and transmit the codeword to the memory module. The mapping information indicates whether each of the plurality of input/output pads is mapped to the same symbol among the plurality of symbols or different symbols among the plurality of symbols. Each of the plurality of symbols corresponds to a unit of error correction of the ECC engine.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: July 20, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyunjoong Kim, Taekwoon Kim, Younghoe Kim, Wonhyung Song, Jangseok Choi, Joonseok Choi
  • Patent number: 11061764
    Abstract: A data storage device includes a flash memory and a controller. The flash memory includes a plurality of dies, and each of the dies includes a first memory plane and a second memory plane, wherein each of the first memory plane and the second memory plane includes a plurality of physical pages. The controller retrieves data of a first physical page of the first memory plane and data of a second physical page of the second memory plane in response to a read command which is arranged to read a target page.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: July 13, 2021
    Assignee: Silicon Motion, Inc.
    Inventors: Chin-Chi Lin, Kun-Lin Ho
  • Patent number: 11062785
    Abstract: Apparatus including an array of memory cells, a plurality of access lines each corresponding to a respective plurality of memory cells of the array of memory cells and each connected to a control gate of each memory cell of its respective plurality of memory cells; and a controller for access of the array of memory cells that is configured to cause the apparatus to apply a particular voltage level to a particular access line of the plurality of access lines, and determine a value indicative of a number of memory cells of the respective plurality of memory cells for the particular access line that are activated in response to applying the particular voltage level. The controller might further be configured to determine an expected data age of the respective plurality of memory cells, and/or determine a plurality of read voltages for reading the respective plurality of memory cells.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: July 13, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Luca De Santis
  • Patent number: 11042438
    Abstract: Devices and techniques for performing copy-back operations in a memory device are disclosed herein. A trigger to perform a copy-back operation in relation to a section of data stored on the memory device can be detected. Circuitry of the memory device can then read the section of data at two voltage levels within a read window to obtain a first set of bits and a second set of bits respectively. The first and second sets of bits—which should be the same under normal circumstances—are compared to determine whether a difference between the sets of bits is beyond a threshold. If the difference is beyond a threshold, error correction is invoked prior to completion of the copy-back operation.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: June 22, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Giuseppe Cariello, Fulvio Rori
  • Patent number: 11037639
    Abstract: Provided herein may be a memory controller and a method of operating the same. The memory controller may include a read operation controller configured to provide a read command to a memory device and receive read data corresponding to the read command, a read fail determiner configured to determine, based on the read data, whether a read operation has passed or failed, and to generate read information including a result of the read operation and information about performance of the read operation and a read fail processor configured to select, based on the read information, one of a read retry operation, among a plurality of read retry operations, to be performed on the selected page and an operation of setting a control time for a bit line coupled to the selected page, and to control the memory device to perform the selected operation.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: June 15, 2021
    Assignee: SK hynix Inc.
    Inventors: Min Ho Her, Dong Hyun Kim, Seung Il Kim, Youn Ho Jung
  • Patent number: 11030042
    Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: June 8, 2021
    Assignee: Silicon Motion, Inc.
    Inventors: Tsung-Chieh Yang, Hong-Jung Hsu, Jian-Dong Du
  • Patent number: 11023316
    Abstract: A DRAM-based storage device includes a DRAM and a control circuit. The DRAM includes a buffering area and a host accessing area. A data is stored in the host accessing area. The control circuit is electrically connected with the DRAM. The control circuit copies a portion of the data from the host accessing area to the buffering area at a predetermined time interval counted by the control circuit. Before the portion of the data is written to the buffering area, a first ECC decoding operation is performed on the portion of the data to correct error bits contained therein. If the portion of the data is corrected, the control circuit rewrites the corrected portion of the data into the host accessing area.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: June 1, 2021
    Assignee: SOLID STATE STORAGE TECHNOLOGY CORPORATION
    Inventors: Yi-Chung Lee, Jyun-Gong Yu
  • Patent number: 11024391
    Abstract: A flash memory system may include a flash memory and a circuit for performing operations of the flash memory. The circuit may be configured to estimate slope information of a plurality of threshold voltage samples based on a first read operation on the flash memory with a first reference voltage. The circuit may be configured to generate soft information based on the estimated slope information. The circuit may be configured to decode a result of a second read operation on the flash memory based on the soft information.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: June 1, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Avi Steiner, Hanan Weingarten
  • Patent number: 11022649
    Abstract: An apparatus is provided to measure vulnerability of a circuit to transient errors. The circuit includes processing circuitry and a plurality of flops. The apparatus includes categorisation obtaining circuitry that obtains a vulnerability categorisation of the flops. The vulnerability categorisation indicates whether each flop is vulnerable, conditionally vulnerable, or isolated. Analysis circuitry determines, for at least one cycle of the processing circuitry, a set of the flops that are currently vulnerable, based on the vulnerability categorisation of the flops.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: June 1, 2021
    Assignee: Arm Limited
    Inventors: Balaji Venu, Reiley Jeyapaul
  • Patent number: 11012072
    Abstract: Method and apparatus for monitoring and reconfiguring a programmable device are disclosed. In some implementations, the programmable device may include a processor and a plurality of satellite monitors to determine operating temperatures at various locations throughout the programmable device. When temperatures of at least some of the satellite monitors exceed a threshold, the processor may reconfigure the programmable device using an alternative configuration. The alternative configuration may provide equivalent functionality with respect to an initial configuration through a different arrangement of functional blocks within the programmable device. The new arrangement of functional blocks may reduce operating temperatures by relocating blocks to different regions of the programmable device.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: May 18, 2021
    Assignee: Xilinx, Inc.
    Inventors: John K. Jennings, Brendan Farley
  • Patent number: 11004504
    Abstract: A controller comprises an error correction circuit configured to check an error bit number of error bits in the read data and correct the error bits; a read retry range setting circuit configured to reset a preset read retry range with respect to the read data, and set a new read retry range based on the error bit number and an error correction capability of the error correction circuit; a read voltage setting circuit configured to reset the set read voltage and set, as a new read voltage, a voltage among a plurality of voltages of the reset read retry range, corresponding to the new read retry range; and a flash control circuit configured to control the memory device to perform a read retry operation on the stored data, using the new read voltage.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: May 11, 2021
    Assignee: SK hynix Inc.
    Inventors: Dong Uk Lee, Hun Wook Lee
  • Patent number: 11005501
    Abstract: Some instances of a memory device include a memory die having an array of memory cells including a plurality of banks. In some cases, the memory die further includes a first error correcting code (ECC) circuit coupled with a first bank of memory cells, where the first ECC circuit is configured to perform operations associated with a first access operation (e.g., write operation) of the first bank of memory cells. In some examples, the memory die further includes a second ECC circuit coupled with the first bank of memory cells, where the second ECC circuit is configured to perform ECC operations associated with a second access operation (e.g., read operation) of the first bank. In some cases, the first ECC circuit is located under the footprint of the array and the second ECC circuit is located outside the footprint of the array.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: May 11, 2021
    Assignee: Micron Technology, Inc.
    Inventor: John David Porter
  • Patent number: 10997025
    Abstract: The data storage system is a RAID-based data storage system in which resources are globally shared. This storage system includes the first number of disks, and the RAID mechanism is used to store data on each disk. The blocks on different disks form stripes, and at least one of the blocks on the stripe stores the parity information, wherein the width of the stripe is less than the first number. The data layout of the data storage system satisfies the following characteristics: any two physical blocks in the stripe are distributed on different disks; the data blocks distributed on each disk are the same, and the distributed parity blocks are also the same; other data in the stripe associated with any piece of disk data is evenly distributed across all the remaining disks. Normal data layout and degraded data layout can be implemented by orthogonal Latin squares.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: May 4, 2021
    Assignee: TSINGHUA UNIVERSITY
    Inventors: Guangyan Zhang, Weimin Zheng
  • Patent number: 10998023
    Abstract: A method for error correction and a system. The method may include opening a selected row of a memory bank out of multiple memory banks of a dynamic memory module; and while the selected row is open: (i) receiving selected data sub-blocks that are targeted to be written to the selected row, (ii) calculating selected error correction code sub-blocks that are related to the selected data sub-blocks, (iii) caching the selected error correction code sub-blocks in a cache memory that differs from the dynamic memory module and (iv) writing, to the selected row, the selected error correction code sub-blocks.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: May 4, 2021
    Assignee: Mobileye Vision Technologies Ltd.
    Inventors: Boris Shulman, Yosef Kreinin, Leonid Smolyansky
  • Patent number: 10991444
    Abstract: Calibrating read reference voltages is disclosed. In an aspect, a control die calibrates read reference voltages for reading the non-volatile memory cells. The control die is bonded to a memory die that contains memory cells. In one aspect, a tiered approach to calibrating read reference voltages is taken. For example, first the control die may attempt to determine new values for read reference voltages. If the new read reference voltages are satisfactory, then the control die may use the new read reference voltages. The control die could use one or more different techniques to determine new read reference voltages. If the new read reference voltages determined by the control die are unsatisfactory, then a memory controller in communication with the control die may calibrate the read reference voltages. By the control die determining the new read reference voltages, the memory controller is substantially less burdened with such tasks.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: April 27, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Alexander Bazarsky, Eran Sharon, Idan Alrod
  • Patent number: 10972133
    Abstract: Fault-tolerant error correction (EC) is desirable for performing large quantum computations. In this disclosure, example fault-tolerant EC protocols are disclosed that use flag circuits, which signal when errors resulting from ? faults have weight greater than ?. Also disclosed are general constructions for these circuits (also referred to as flag qubits) for measuring arbitrary weight stabilizers. The example flag EC protocol is applicable to stabilizer codes of arbitrary distance that satisfy a set of conditions and uses fewer qubits than other schemes, such as Shor, Steane and Knill error correction. Also disclosed are examples of infinite code families that satisfy these conditions and analyze the behaviour of distance-three and -five examples numerically. Using fewer resources than Shor EC, the example flag EC protocols can be used in low-overhead fault-tolerant EC protocols using large low density parity check quantum codes.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: April 6, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Christopher Chamberland, Michael E. Beverland
  • Patent number: 10957415
    Abstract: An NAND flash memory and a reading method thereof capable of high-speed reading of SFDP data are provided. The flash memory includes a memory cell array, a page buffer/reading circuit 170 and a controller 150. The page buffer/reading circuit 170 includes a first latch circuit L1 and a second latch circuit L2. The first latch circuit L1 keeps data read from the memory cell array. The second latch circuit L2 keeps data transferred from the first latch circuit L1. Just after power is turned on or reset, the controller 150 controls data of block 0/page 0 of the memory cell array to be kept in the second latch circuit L2 and controls the SFDP data to be kept in the first latch circuit L1. The SFDP data or the data of block 0/page 0 is serially output according to an input command.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: March 23, 2021
    Assignee: Winbond Electronics Corp.
    Inventors: Kazuki Yamauchi, Katsutoshi Suito
  • Patent number: 10957416
    Abstract: Methods and apparatus for using characterized devices such as memories. In one embodiment, characterized memories are associated with a range of performances over a range of operational parameters. The characterized memories can be used in conjunction with a solution density function to optimize memory searching. In one exemplary embodiment, a cryptocurrency miner can utilize characterized memories to generate memory hard proof-of-work (POW). The results may be further validated against general compute memories; such that only valid solutions are broadcasted to the mining community. In one embodiment, the validation mechanism is implemented for a plurality of searching apparatus in parallel to provide a more distributed and efficient approach.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: March 23, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Jonathan D. Harms
  • Patent number: 10956261
    Abstract: A volatile memory device includes memory cells arranged on rows and columns; first counters each storing a count value representing a number of cells in which first data is stored among cells of a corresponding column, wherein the count value is updated or maintained whenever a write operation on each of the rows is performed; a calculator calculating a number of cells in which the first data is stored for each of the columns upon a determination that an EDC check on any one row among the rows fails, and determining a column in which a bit flip occurs by comparing the calculated number and the count value for each of the columns; and a control circuit determining that a cell of the row on which the EDC check fails among cells of the column in which the bit flip occurs is the bit-flipped cell.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: March 23, 2021
    Assignee: SK hynix Inc.
    Inventor: Dong Sop Lee