Memory Access Patents (Class 714/763)
  • Patent number: 10893099
    Abstract: Technology is generally described for automating the project management and execution of data migration from a source email system to a destination email system. In some examples, the technology can include receiving a domain name of a second computing system; obtaining domain name system (DNS) records for the received domain name; determining an email hosting provider for the second computing system; determining, by the processor, based on the obtained DNS records, an email system service type of the source email system on the second computing system; discovering mailboxes and message delivery rules of the source email system; displaying customization options for migrating discovered source email system mailboxes; migrating data items from the source email system to the destination email system; and managing migration of data from source email system client computing devices to the destination email system.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: January 12, 2021
    Assignee: SkyKick, Inc.
    Inventors: John Dennis, Evan Richman, Todd Schwartz, Trent Schwartz, Richard J. Tett, Brad Younge
  • Patent number: 10891400
    Abstract: A method includes dispersed storage error encoding, by a computing device of a dispersed storage network (DSN), a plurality of data segments to produce a plurality of sets of encoded data slices. The method further includes obfuscating a first set of encoded data slices of the plurality of sets of encoded data slices using a first obfuscating method to produce a first set of obfuscated encoded data slices. The method further includes obfuscating a second set of encoded data slices of the plurality of sets of encoded data slices using a second obfuscating method to produce a second set of obfuscated encoded data slices. The method further includes outputting the first and second sets of obfuscated encoded data slices for storage.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: January 12, 2021
    Assignee: PURE STORAGE, INC.
    Inventors: S. Christopher Gladwin, Thomas F. Shirley, Jr., Gary W. Grube
  • Patent number: 10884940
    Abstract: A method of operating a cache in a computing device includes, in response to receiving a memory access request at the cache, determining compressibility of data specified by the request, selecting in the cache a destination portion for storing the data based on the compressibility of the data and a persistent fault history of the destination portion, and storing a compressed copy of the data in a non-faulted subportion of the destination portion, wherein the persistent fault history indicates that the non-faulted subportion excludes any persistent faults.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: January 5, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: John Kalamatianos, Shrikanth Ganapathy, Shomit Das, Matthew Tomei
  • Patent number: 10880713
    Abstract: The present invention provides a method and system for enabling machine type communication in a long term evolution (LTE) network environment. In one embodiment, a Physical (PHY) layer of a LTE protocol stack maps data bits in resource elements of a logical channel to resource elements of a physical channel. The PHY layer identifies the data bits intended for legacy devices but mapped to a first set of resource elements of machine type communication (MTC) devices and the data bits intended for the MTC device but mapped to the second set of resource elements of the legacy devices. Accordingly, the PHY layer remaps the data bits intended for the legacy devices to the second set of resource elements and the data bits intended for the MTC devices to the first set of resource elements prior to transmission.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: December 29, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Satish Nanjunda Swamy Jamadagni, Sarvesha Anegundi Ganapathi, Pradeep Krishnamurthy Hirisave, Jinesh Parameshwaran Nair
  • Patent number: 10848263
    Abstract: The invention introduces a method for reducing data errors in transceiving of a flash storage interface, performed by a processing unit of a first side, comprising: continuously monitoring data frames and/or control frames from a second side; and triggering a TX (transmission) data rate adjustment when information of the data frame and/or the control frame indicates that the lowest layer of the second side detects errors from received data.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: November 24, 2020
    Assignee: SILICON MOTION, INC.
    Inventor: Fu-Jen Shih
  • Patent number: 10838768
    Abstract: The invention relates in particular to optimizing memory access in a microprocessor including several logic cores upon the resumption of executing a main application, and enabling the simultaneous execution of at least two processes in an environment including a hierarchically organized shared memory including a top portion and a bottom portion, a datum being copied from the bottom portion to the top portion for processing by the application. The computer is adapted to interrupt the execution of the main application. Upon an interruption in the execution of said application, a reference to a datum stored in a top portion of the memory is stored, wherein said datum must be used in order to enable the execution of the application. After programming a resumption of the execution of the application and before the resumption thereof, said datum is accessed in a bottom portion of the memory in accordance with the reference to be stored in a top portion of the memory.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: November 17, 2020
    Assignee: BULL SAS
    Inventors: Philippe Couvee, Yann Kalemkarian, Benoît Welterlen
  • Patent number: 10838660
    Abstract: A method includes receiving, by a computing entity of a dispersed storage network (DSN), a request from a requesting device of the DSN to perform an encoded data slice operation. The request includes an indication that the encoded data slice operation is a stage in a predefined DSN workflow. The method further includes sending, by the computing entity, a response to the requesting device that includes a DSN workflow tag, wherein the DSN workflow tag includes an identifier of the stage in the predefined DSN workflow. The method further includes enabling a performance optimization mode. The performance optimization mode includes one or more performance optimization procedures for one or more of: the stage and one or more future stages of the predefined DSN workflow. The method further includes executing the encoded data slice operation in accordance with the performance optimization mode.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: November 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David E. Reese, Ethan S. Wozniak
  • Patent number: 10831455
    Abstract: A set of quantum assembly language referencing a quantum algorithm is received from a user. A quantum device is selected to execute the set of quantum assembly language. Responsive to the selected quantum device, an implementation of the quantum algorithm from a remote repository is selected, the remote repository comprising a set of implementations of a set of quantum algorithms. An implementation in the set of implementations in the remote repository is compiled to form a compiled quantum circuit. The compiled quantum circuit is transformed into a quantum circuit model. Using the selected quantum device, the quantum circuit model is executed.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jay M. Gambetta, Ismael Faro Sertage, Marco Pistoia
  • Patent number: 10833846
    Abstract: Disclosed herein are methods, systems, and apparatus, including computer programs encoded on computer storage media, for processing blockchain data. One of the methods includes receiving a request from a blockchain node of the blockchain network to execute one or more software instructions in a trusted execution environment (TEE). One or more blocks infrequently accessed for executing the one or more software instructions are determined. Error correction coding of the one or more blocks in the TEE is performed to generate one or more encoded blocks. Each of the one or more encoded blocks are divided into a plurality of datasets based on the one or more software instructions. The plurality of datasets and a data storage arrangement are sent to blockchain network nodes, where the data storage arrangement indicates at least one of the plurality of datasets to be stored by each of the blockchain nodes.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: November 10, 2020
    Assignee: Alibaba Group Holding Limited
    Inventor: Haizhen Zhuo
  • Patent number: 10824505
    Abstract: An example multi-master system in a system-on-chip (SoC) includes a plurality of master circuits, an error-correcting code (ECC) proxy bridge comprising hardened circuitry in the SoC, a local interconnect configured to couple the plurality of master circuits to the ECC proxy bridge, a memory not having ECC support, and a system interconnect configured to couple the ECC proxy bridge to the memory. The ECC proxy bridge is configured to establish an ECC proxy region in the memory and, for each write transaction from the plurality of master circuits that targets the ECC proxy region, calculate and insert ECC bytes into the respective write transaction.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: November 3, 2020
    Assignee: XILINX, INC.
    Inventors: Ian A. Swarbrick, Nishit Patel
  • Patent number: 10817368
    Abstract: The present invention discloses a unidirectional bit error correction method for a OTP ROM, comprising: applying error correction encoding to bit information and writing the bit information to the OTP ROM; during power-up initialization, converting hard bit information read out from the OTP ROM to soft bit information; during the power-up initialization, performing error correction decoding through a soft bit decoder. The advantages of the present invention include: utilizing otherwise temporarily idle decoding modules in the chip, without requiring additional hardware resource, while providing stronger error correction capability to the OTP ROM, improving the stability of chip applications, prolonging chip service life, and significantly reducing rejection rate in chip production.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: October 27, 2020
    Assignee: Espressif Systems (Shanghai) Co., Ltd.
    Inventors: Hao Lin, Rui Zhan
  • Patent number: 10811090
    Abstract: A memory cell can have a state in a valley between adjacent data states. A determination can be made whether a state of a memory cell is in a valley between adjacent distributions of states associated with respective data states. A signal indicative of a data state of the memory cell and whether the state of the memory cell is in the valley can be transmitted.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: October 20, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Sivagnanam Parthasarathy, Patrick R. Khayat, Mustafa N. Kaynak, Robert B. Eisenhuth
  • Patent number: 10802730
    Abstract: Power consumption of a semiconductor device is reduced. A semiconductor device according to an embodiment includes a plurality of circuits, a bus circuit including a plurality of buffers that temporarily store communication data between the circuits and a plurality of arbitration circuits that arbitrate an access between the circuits and the buffers, a storage unit that stores information based on a use state of the buffers during communication between the circuits and configuration information including designation of unused circuits that are not used for the communication from among the circuits, and a control circuit that controls the bus circuit so as to stop use of unused buffers that are not used for the communication from among the buffers and at least a partial configuration in arbitration circuits corresponding to the unused circuits from among the arbitration circuits based on the configuration information.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: October 13, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yasumasa Watanabe, Mitsuhiro Ono, Toshiro Fujisaki, Kenji Kimura
  • Patent number: 10802910
    Abstract: In one embodiment, an apparatus comprises a controller comprising circuitry, the controller to generate an error correction code for a memory line, the memory line comprising a plurality of first data blocks, wherein the error correction code comprises parity bits generated based on first portions of a plurality of second data blocks, wherein the plurality of second data blocks are the first data blocks or diffused data blocks generated from the plurality of first data blocks; generate a metadata block corresponding to the memory line, wherein the metadata block comprises the error correction code for the memory line and at least one metadata bit; encode the first data blocks and the metadata block; and provide the encoded data blocks and the encoded metadata block for storage on a memory module.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: October 13, 2020
    Assignee: Intel Corporation
    Inventors: Sergej Deutsch, Wei Wu, David M. Durham, Karanvir S. Grewal
  • Patent number: 10795764
    Abstract: A data chip that may pollute data is disclosed. The data chip may include a data array, read circuitry to read raw data from the data array, and a buffer to store the raw data. Using a pollution pattern stored in a mask register, a data pollution engine may pollute the raw data. Transmission circuitry may then transmit the polluted data.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: October 6, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dimin Niu, Mu-Tien Chang, Hongzhong Zheng, Hyun-Joong Kim, Won-Hyung Song, Jangseok Choi
  • Patent number: 10795780
    Abstract: A method for analyzing a potential data breach is disclosed. In one embodiment, such a method includes identifying a time frame and data store in which a data breach potentially occurred. The method reconstructs the data store to a point in time near an end of the time frame. The method then repeatedly performs the following until the data store reaches a point in time near a beginning of the time frame: revert to a previous version of the data store by removing an incremental update to the data store; record changes to the data store caused by removing the incremental update; and record timestamps associated with the changes. Once the data store reaches the point in time near the beginning of the time frame, the method creates a report that documents the changes and the timestamps and provides the report to a user. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: October 6, 2020
    Assignee: International Business Machines Corporation
    Inventors: David C. Reed, Gregory E. McBride
  • Patent number: 10790860
    Abstract: A method of decoding data stored in non-volatile memory in which each memory cell stores data by adopting one of a plurality of storage states.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: September 29, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Memory Corporation
    Inventors: Amr Ismail, Magnus Stig Torsten Sandell
  • Patent number: 10779381
    Abstract: A load control device is able to receive radio-frequency (RF) signals from a Wi-Fi-enabled device, such as a smart phone, via a wireless local area network. The load control device comprises a controllably conductive device adapted to be coupled in series between an AC power source and an electrical load, a controller for rendering the controllably conductive device conductive and non-conductive, and a Wi-Fi module operable to receive the RF signals from the wireless network. The controller controls the controllably conductive device to adjust the power delivered to the load in response to the wireless signals received from the wireless network. The load control device may further comprise an optical module operable to receive an optical signal, such that the controller may obtain an IP address from the received optical signal and control the power delivered to the load in response to a wireless signal that includes the IP address.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: September 15, 2020
    Assignee: Lutron Technology Company LLC
    Inventors: Theodore F. Economy, John C. Browne, Jr., William Bryce Fricke, Galen Edgar Knode, Ryan S. Bedell, Christopher J. Salvestrini
  • Patent number: 10770168
    Abstract: Several embodiments of systems incorporating memory sub-systems are disclosed herein. In one embodiment, a memory sub-system can include a memory component and a processing device configured to perform a background scan on a memory region of the memory component. In some embodiments, the background scan includes generating a bit error count (BEC) of a codeword saved on the memory region and saving statistical information corresponding to the BEC of the codeword to a histogram statistics log. In some embodiments, when the BEC of the codeword is greater than a BEC threshold, a refresh operation is scheduled for the memory region and/or logged. In these and other embodiments, when one or more error recovery error correction code (ECC) operations do not correct bit errors in the codeword, a refresh and/or retirement operation is schedule for the memory region and/or is logged.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: September 8, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Gerald L. Cadloni, Bruce A. Liikanen
  • Patent number: 10755785
    Abstract: A memory system may include performing a first read operation on first data stored in first memory cells coupled to a first word line, performing an error correction operation on the first data, performing an interference program operation on second memory cells coupled to a second word line when the error correction operation fails, and performing a second read operation on the first data stored in the first memory cells after performing the interference program operation.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: August 25, 2020
    Assignee: SK hynix Inc.
    Inventor: Ji Man Hong
  • Patent number: 10747601
    Abstract: An apparatus is provided to measure vulnerability of a circuit to transient errors. The circuit includes processing circuitry and a plurality of flops. The apparatus includes categorisation obtaining circuitry that obtains a vulnerability categorisation of the flops. The vulnerability categorisation indicates whether each flop is vulnerable, conditionally vulnerable, or isolated. Analysis circuitry determines, for one cycle of the processing circuitry, a set of the flops that are currently vulnerable, based on the vulnerability categorisation of the flops.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: August 18, 2020
    Assignee: Arm Limited
    Inventors: Reiley Jeyapaul, Balaji Venu
  • Patent number: 10740179
    Abstract: An error correction method and a chip kill detection method of a memory including a plurality of chips may be provided. The method may include a first data error detection step of detecting whether an error exists in data outputted from the plurality of chips. The method may include a random error correction step of correcting an error occurred in data when it is detected in the first data error detection step that an error exists. The method may include a chip kill detection step of determining, when an error occurs even after the random error correction step, that a chip kill error has occurred, and detecting a chip where the chip kill error has occurred, by correcting the error through assuming one chip among the plurality of chips as a chip where the chip kill error has occurred.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: August 11, 2020
    Assignee: SK hynix Inc.
    Inventor: Sungeun Lee
  • Patent number: 10733046
    Abstract: Apparatuses and methods related to providing transaction metadata. Providing transaction metadata includes providing an address of data stored in the memory device using an address bus coupled to the memory device and the controller. Providing transaction metadata also includes transferring the data, associated with the address, from the memory device using a data bus coupled to the memory device and the controller. Providing transaction metadata further includes transferring a sideband signal synchronously with the data bus and in conjunction with the address bus using a transaction metadata bus coupled to the memory device and the controller.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: August 4, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Graziano Mirichigni, Marco Sforzin, Paolo Amato, Danilo Caraccio
  • Patent number: 10735515
    Abstract: A two-layer erasure-coded fault-tolerant distributed storage system offering atomic access for read and write operations is described. In some embodiments, a class of erasure codes known as regenerating codes (e.g. minimum bandwidth regenerating codes) for storage of data in a backend layer is used to reduce a cost of backend bulk storage and helps in reducing communication cost of read operations, when a value needs to be recreated from persistent storage in the backend layer. By separating the functionality of edge layer servers and backend servers, a modular implementation for atomicity using storage-efficient erasure-codes is provided. Such a two-layer modular architecture permits protocols needed for consistency implementation to be substantially limited to the interaction between clients and an edge layer, while protocols needed to implement erasure code are substantially limited to interaction between edge and backend layers.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: August 4, 2020
    Assignee: Massachusetts Institute of Technology
    Inventors: Kishori Mohan Konwar, Prakash Narayana Moorthy, Muriel Medard, Nancy Ann Lynch
  • Patent number: 10725858
    Abstract: A method for operating a memory system includes: performing a read operation in response to a first tag; performing a read operation in response to a second tag; performing a defense code operation corresponding to the first tag; performing an error correction code (ECC) operation on data output through the defense code operation corresponding to the first tag; and performing a defense code operation corresponding to the second tag, wherein the read operation in response to the second tag is started before the ECC operation corresponding to the first tag is completed, and wherein the defense code operation corresponding to the second tag is performed using a result of the defense code operation corresponding to the first tag.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: July 28, 2020
    Assignee: SK hynix Inc.
    Inventors: Seon Ju Lee, Min Hwan Moon
  • Patent number: 10725859
    Abstract: A system and method improve the performance of non-volatile memory storage by offloading parity computations to facilitate high speed data transfers, including direct memory access (DMA) transfers, between a remote host and a non-volatile memory based storage system, such as a flash memory based data storage device (e.g., SSD). In conjunction with writing to non-volatile memory storage, a stripe map is used to target a selected data storage device for parity generation. All data of a stripe is transmitted to the selected data storage device to generate the parity and the generated parity is propagated from the selected data storage device to other data storage devices in the stripe. The data for the stripe may also be propagated from the selected data storage device to the other data storage devices in the stripe.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: July 28, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Vladislav Bolkhovitin, Brian W. O'Krafka, Sanjay Subbarao
  • Patent number: 10719250
    Abstract: Resource-efficient data protection is performed by generating meta chunks in storage systems that utilize erasure coding. During erasure coding with a k+m configuration, a data chunk can be divided into k data fragments, having indices 1 to k, that can be encoded by combining them with corresponding coefficients of a coding matrix, to generate coding fragments. Source portions that have a reduced set (e.g., less than k data fragments) of data fragments and that are complementary (e.g., that do not have common indices) can be determined and combined to generate a meta chunk. The coding fragments of the source portions can be added to generate coding fragments for the meta chunk, which can then be utilized to recover data fragments of any of the source portions. Further, the coding fragments, that were previously generated by individually encoding each source portion, can be deleted.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: July 21, 2020
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Mikhail Danilov, Kirill Gusakov
  • Patent number: 10712954
    Abstract: Nonvolatile memory device includes a memory cell array and a control circuit. The memory cell array includes a plurality of memory blocks, the memory blocks including a plurality of memory cells coupled to word-lines respectively, the word-lines are stacked vertically on a substrate, and some memory cells of the plurality of memory cells are selected by sub-block unit smaller than one memory block. The control circuit divides sub-blocks of a first memory block into at least one bad sub-block and at least one normal sub-block based on error occurrence frequency of each of the sub-blocks, and applies different program/erase cycles to the at least one bad sub-block and the at least one normal sub-block based on a command and an address provided from external to the nonvolatile memory device. The at least one bad sub-block and the at least one normal sub-block are adjacent each other.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: July 14, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seung-Bum Kim
  • Patent number: 10705908
    Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: July 7, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hoi-Ju Chung, Sang-Uhn Cha, Ho-Young Song, Hyun-Joong Kim
  • Patent number: 10705912
    Abstract: Data and error correction information may involve accessing multiple data channels (e.g., 8) and one error detection and correction channel concurrently. This technique requires a total of N+1 row requests for each access, where N is the number of data channels (e.g., 8 data row accesses and 1 error detection and correction row access equals 9 row accesses.) A single (or at least less than N) data channel row may be accessed concurrently with a single error detection and correction row. This reduces the number of row requests to two (2)—one for the data and one for the error detection and correction information. Because, row requests consume power, reducing the number of row requests is more power efficient.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: July 7, 2020
    Assignee: Rambus Inc.
    Inventors: Michael Miller, Stephen Magee, John Eric Linstadt
  • Patent number: 10700711
    Abstract: Segments of a local range can appear multiple times in the sequence of erasure sets in a manifest without the data being duplicated. A subset of the content of an erasure set can be included in the logical object. It is not required that all erasure sets in an object use the same encoding. A manifest can indicate one or more portions of the logical object for which no data has been provided, and for which a “fill” pattern is specified. A portion of data can be inserted at any point inside the object by inserting a reference to one or more segment sets containing that data into the manifest. If the desired insertion point is within an existing segment set, then that manifest set can be “split” by incorporating two references to it, with the first specifying the range of data before the insertion point, and the second specifying the range of data after the insertion point. Many operations are thus enabled on an erasure-coded object in Object Storage such as “append”, “insert,” “overwrite” and “merge.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: June 30, 2020
    Assignee: CARINGO INC.
    Inventors: Thomas William Cook, Andrew David Klager, Tom Teugels, Patrick Murphy Ray, Donald George Baker
  • Patent number: 10698364
    Abstract: Methods and systems (terminals, devices) for the generation, the retrieval and the display of computer-generated holographic images through a head-mounted display. The holographic images may be used as virtual retrievable tags for display in augmented reality.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: June 30, 2020
    Assignee: Essilor International
    Inventors: Samuel Archambeau, Jerôme Ballet, Aude Bouchier, Jean-Paul Cano, David Escaich, Stephane Perrot
  • Patent number: 10691533
    Abstract: Methods, systems, and devices for an error correcting code scrub scheme are described. A memory device may correct an error associated with a first data bit or a first parity bit of a plurality of data bits and a plurality of parity bits, respectively. The memory device may correct the error by reading each of the plurality of data bits and the plurality of parity bits from a memory array, and determining that an error associated with a single bit exists. The memory device may then correct the determined single-bit error, and may write the corrected bit directly back to the memory array.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: June 23, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Jongtae Kwak
  • Patent number: 10671321
    Abstract: A data storage device includes a storage unit configured to include a storage area divided into a plurality of blocks, a buffer memory unit configured to temporarily store data inputted/outputted from/to the storage unit, and a controller configured to write data in the storage unit or read the data from the storage unit at a request of a host device, and to determine disturbance risk for each of the plurality of blocks based on a prescribed reference and control a block determined as a disturbance risk block not to be accessed in a read operation when the data is read from the storage unit.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: June 2, 2020
    Assignee: SK hynix Inc.
    Inventor: Min Gu Kang
  • Patent number: 10658063
    Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, a read circuit, a correcting circuit and a write circuit. The read circuit is configured to read first data from the memory cell by receiving a first command. The correcting circuit is configured to generate second data by correcting an error included in the first data. The write circuit is configured to write the second data to the memory cell in response to receiving a second command.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: May 19, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hiromi Noro, Kenji Tsuchida
  • Patent number: 10658066
    Abstract: Described herein are embodiments related to first-pass continuous read level calibration (cRLC) operations on memory cells of memory systems. A processing device determines that a first programming pass of a programming operation has been performed on a memory cell of a memory component. The processing device performs a cRLC operation on the memory cell to calibrate a read level threshold between a first first-pass programming distribution and a second first-pass programming distribution before a second programming pass of the programming operation is performed on the memory cell.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: May 19, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Michael Sheperek, Larry J. Koudele, Bruce A. Liikanen
  • Patent number: 10651874
    Abstract: The present invention is directed to data communication systems and methods thereof. According to various embodiments, the present invention provides a communication with a reconfigurable forward-error-correction (FEC) module. The FEC module processes data received from two or more communication lanes, and depending on the mode of operation, the FEC module can combine data from the two or more communication lanes and perform error correction on the combined data, or the FEC module can processes data from the two communications lanes separately and perform error correction independently for the each of the data communication lanes. There are other embodiments as well.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: May 12, 2020
    Assignee: INPHI CORPORATION
    Inventor: Volodymyr Shvydun
  • Patent number: 10643719
    Abstract: A method is described, which includes reading first raw data from a set of memory cells at an indicated address and determining a number of errors in the first raw data. In response to determining that the number of errors is greater than a threshold, the set of memory cells are flagged for rereading. In response to flagging the set of memory cells for rereading, second raw data is read from the set of memory cells and a comparison is performed based on the first raw data and the second raw data to determine a number of non-read disturbance errors. In response to the comparison, the threshold is modified based on the number of non-read disturbance errors.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: May 5, 2020
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Samuel E. Bradshaw
  • Patent number: 10635524
    Abstract: An error management system for a data storage device can generate soft-decision log-likelihood ratios (LLRs) using multiple reads of memory locations. Bit patterns provided by multiple reads of reference memory locations can be counted and used to generate probability data that is used to generate possible LLR values for decoding target pages. Possible LLR values are stored in one or more look-up tables.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: April 28, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Guangming Lu, Kent D. Anderson, Anantha Raman Krishnan, Shafa Dahandeh
  • Patent number: 10635514
    Abstract: A storage device includes a receiving circuit including a correction circuit configured to correct an input signal from a host system based on correction factors and output the corrected input signal as an output signal containing a data value that is to be stored in the storage device, an interface controller configured to adjust the correction factors based on a difference value generated by the correction circuit using the output signal, and a transmission circuit configured to transmit the correction factors to the host system.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: April 28, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masayoshi Sato, Ichirou Hara
  • Patent number: 10635400
    Abstract: Apparatuses, systems, methods, and computer program products are disclosed for seed generation. An apparatus includes a memory element. An apparatus includes a scrambler component. A scrambler component includes a random seed generation circuit that generates a random seed. A scrambler component includes a deterministic seed generation circuit that generates a deterministic seed based on a physical address of a memory element for storing data. A scrambler component includes a computation circuit that forms a computed seed based on a random seed and a deterministic seed. Data is scrambled using a computed seed before data is stored.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: April 28, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Eran Sharon, Yoav Weinberg, Karin Inbar, Omer Fainzilber, Stella Achtenberg, Nika Yanuka
  • Patent number: 10635312
    Abstract: A method for execution by a dispersed storage and task (DST) client module includes issuing a read threshold number of read slice requests are issued to storage units of the set of storage units. One or more encoded slices of a selected read threshold number of encoded slices are received. When a next encoded data slice of a decode threshold number of encoded data slices is received within a response timeframe, outputting of the next encoded data slice is initiated. When the next encoded data slice is not received within the response timeframe, receiving of another decode threshold number of encoded slices of the set of encoded slices is facilitated. The other decode threshold number of encoded slices are decoded to produce recovered encoded data slices, where the recovered encoded data slices includes at least a recovered next encoded data.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: April 28, 2020
    Assignee: PURE STORAGE, INC.
    Inventors: Bruno H. Cabral, Wesley B. Leggette
  • Patent number: 10628045
    Abstract: Apparatus and method for managing data in a hybrid data storage device. In some embodiments, the hybrid data storage device has a hard disc drive (HDD) controller circuit coupled to non-volatile rotatable storage media and a solid state drive (SSD) controller circuit coupled to non-volatile solid state memory. A local memory stores a map structure which identifies logical addresses of current version data sets stored in the solid state memory. A top level controller circuit operates responsive to the map structure to direct a selected host data transfer access command to the HDD or SSD controller circuit. The map structure may be arranged as a plurality of discrete logical address sequences, where a gap is provided between each adjacent pair of the discrete logical address sequences in the map structure.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: April 21, 2020
    Assignee: Seagate Technology LLC
    Inventors: John E. Moon, Stanton M. Keeler, Leata M. Blankenship, Greg D. Larrew
  • Patent number: 10613795
    Abstract: A characteristic data pre-processing system includes a data acquisition device that collects characteristic data including first cell distribution data defined according to first default read levels, and second cell distribution data defined according to second default read levels, a data pre-processing apparatus that merges the first cell distribution data and the second cell distribution data according crop ranges to generate training data, wherein the crop ranges are defined according to the first default levels and the second default levels, and a database that stores the training data communicated from the data pre-processing apparatus.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: April 7, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun Ko Oh, Seung Kyung Ro, Hye Ry No, Jin Baek Song, Dong Gi Lee, Hee Won Lee, Dong Hoo Lim
  • Patent number: 10607712
    Abstract: A method of managing errors in a plurality of storage drives includes receiving, at a memory controller coupled to at least one storage medium in an SSD, a read command from a host interface. The method also includes retrieving, from the storage medium, read data corresponding to a plurality of data chunks to be retrieved in response to the read command, and determining that at least one data chunk of the plurality of data chunks is unable to be read, the at least one data chunk corresponding to a failed data chunk. And in response to determining the failed data chunk, sending to the host interface the read data including the failed data chunk or excluding the failed data chunk. And in response to the read command sending to the host interface status information about all data chunks.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: March 31, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Neil Buxton, Shigehiro Asano, Steven Wells, Mark Carlson
  • Patent number: 10606692
    Abstract: An embodiment includes a method for use in operating a memory chip, the method comprising: operating the memory chip with an increased burst length relative to a standard burst length of the memory chip; and using the increased burst length to access metadata during a given operation of the memory chip. Another embodiment includes a memory module, comprising a plurality of memory chips, each memory chip being operable with an increased burst length relative to a standard burst length of the memory chip, the increased burst length being used to access metadata during a given operation of the memory module.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: March 31, 2020
    Assignee: International Business Machines Corporation
    Inventors: Paul W. Coteus, Kyu-hyoun Kim, Luis A. Lastras-Montano, Warren E. Maule, Patrick J. Meaney, James A. O'Connor, Barry M. Trager
  • Patent number: 10592120
    Abstract: Memory modules, systems, memory controllers and associated methods are disclosed. In one embodiment, a memory module includes a module substrate having first and second memory devices. Buffer circuitry disposed on the substrate couples to the first and second memory devices via respective first and second secondary interfaces. The buffer circuitry includes a primary signaling interface for coupling to a group of signaling links associated with a memory controller. The primary signaling interface operates at a primary signaling rate and the first and second secondary data interfaces operate at a secondary signaling rate. During a first mode of operation, the primary interface signaling rate is at least twice the secondary signaling rate. A first time interval associated with a transfer of first column data via the first secondary interface temporally overlaps a second time interval involving second column data transferred via the second secondary interface.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: March 17, 2020
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Ely Tsern
  • Patent number: 10585751
    Abstract: A method includes detecting an encoded data slice of a set of encoded data slices that requires rebuilding. A storage unit of the DSN includes a local memory and cloud-based alternative memory. The storage unit stores at least one of first and second encoded data slices of the set of encoded data slices in the cloud-based alternative memory. The method further includes determining whether to rebuild the encoded data slice using a full rebuild operation or partial rebuild operation. When determined to rebuild the encoded data slice using the partial rebuild operation, a partial rebuild request is sent to the storage unit. The storage unit then generates partial rebuilding data based on the first and second encoded data slices. The rebuilding module then creates a rebuilt encoded data slice from the partial rebuilding data and other partial rebuilding data from other storage units.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: March 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Greg R. Dhuse, Ravi V. Khadiwala
  • Patent number: 10585732
    Abstract: Systems and methods are disclosed for categorizing error types encountered in data access operations based on bit information from a data segment. An example apparatus includes a circuit configured to perform error recovery for one or more data segments including determining an error recovery operation of a plurality of error recovery operations to perform based on bit information of the one or more data segments. The example circuit also performs the determined error recovery operation.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: March 10, 2020
    Assignee: Seagate Technology LLC
    Inventors: Seokhun Jeon, MinGyeong Son, Seung Youl Jeong
  • Patent number: 10587288
    Abstract: Systems and methods for decoding a product code is provided. The system comprises a media, a first buffer, a second buffer, and a decoder. The media stores a plurality of codewords of a first code of the product code. The first buffer temporarily stores at least one codeword that has failed to be decoded. The second buffer temporarily stores soft information to be used in decoding. The decoder is configured to decode the plurality of codewords, determine if a first count of the at least one failed codeword exceeds a designed maximum number of codewords recoverable using the decoding method. In response to determining that the first count does not exceed the predefined threshold, the decoder iteratively process each failed codeword of the at least one failed codeword with the soft information, and attempt to decode at least one of each failed codeword that has been iteratively processed.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: March 10, 2020
    Assignee: Marvell International Ltd.
    Inventors: Shashi Kiran Chilappagari, Phong Sy Nguyen