Memory Access Patents (Class 714/763)
  • Patent number: 11983066
    Abstract: The present disclosure provides a data storage device. The data storage device includes a first area configured to store a first data; a second area configured to store a second data. The second data is associated with the first data, and the first data and/or the second data exclude an ECC.
    Type: Grant
    Filed: May 5, 2022
    Date of Patent: May 14, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chun-Lu Lee
  • Patent number: 11978525
    Abstract: A base die is configured to: receive first data in a writing phase, perform error correction code encoding processing to generate encoded data, and transmit second data to a memory die in the writing phase, wherein the second data includes the first data and the encoded data; and receive the second data from the memory die in a reading phase, perform error checking and correction processing, and transmit third data in the reading phase, wherein the third data is the first data after the error checking and correction processing.
    Type: Grant
    Filed: May 4, 2022
    Date of Patent: May 7, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Shu-Liang Ning
  • Patent number: 11977444
    Abstract: An apparatus comprising a memory array including a plurality of memory cells arranged in a plurality of columns and a plurality of rows is provided. The apparatus further comprises circuitry configured to perform an error detection operation on the memory array to determine a raw count of detected errors, to compare the raw count of detected errors to a threshold value to determine an over-threshold amount, to scale the over-threshold amount according to a scaling algorithm to determine a scaled error count, and to store the scaled error count in a user-accessible storage location.
    Type: Grant
    Filed: May 22, 2023
    Date of Patent: May 7, 2024
    Inventors: Matthew A. Prather, Randall J. Rooney
  • Patent number: 11977443
    Abstract: Methods, systems, and devices for a dynamic parity scheme are described. A memory system may include a memory device with multiple blocks of memory cells, where each block includes a first quantity of pages of memory cells storing data and a second quantity of pages of memory cells storing parity information associated with the data. In some cases, the memory system may increase the quantity of pages in a block of memory cells storing parity information to improve a reliability of the data stored in the block of memory cells. For example, the memory system may increase the quantity of pages storing parity information at the block of memory cells after performing a threshold quantity of access operations at the block of memory cells or in response to detecting more than a threshold quantity of errors in data stored at the block of memory cells.
    Type: Grant
    Filed: August 15, 2022
    Date of Patent: May 7, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Gennaro Schettino, Luca Porzio
  • Patent number: 11977743
    Abstract: A storage unit is disclosed. The storage unit may include storage for a component codeword. The component codeword may be stored in a block in the storage. The block may also store a block codeword. An interface may receive a read request for a chunk of data from a host and may send the chunk of data to the host. A circuit may read the component codeword from the block in the storage. An error correcting code (ECC) decoder may determine the chunk of data based at least in part on the component codeword.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: May 7, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Zongwang Li, Jing Yang, Marie Mai Nguyen, Mehran Elyasi, Rekha Pitchumani
  • Patent number: 11966813
    Abstract: Embodiments are provided for error mitigation in quantum programs. In some embodiments, a system can include a processor that executes computer-executable components stored in memory. The computer-executable components include a compilation component that causes encoding of one or more qubits according to a circular repetition code at a time after operations on the one or more qubits and before readout.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: April 23, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Panagiotis Barkoutsos, Jakob Max Guenther, Francesco Tacchino, James Robin Wootton, Ivano Tavernelli
  • Patent number: 11960398
    Abstract: Methods, systems, and devices for enhanced data reliability in multi-level memory cells are described. For a write operation, a host device may identify a first set of data to be stored by a set of memory cells at a memory device. Based on a quantity of bits within the first set of data being less than a storage capacity of the set of memory cells, the host device may generate a second set of data and transmit a write command including the first and second sets of data to the memory device. For a read operation, the host device may receive a first set of data from the memory device in response to transmitting a read command. The memory device may extract a second set of data from the first set of data and validate a portion of the first set of data using the second set of data.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: April 16, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Deping He, David Aaron Palmer
  • Patent number: 11960361
    Abstract: A method for execution by a storage network includes receiving a request pertaining to a data object. Metadata associated with the data object is determined and used to identify data segments associated with the data object and a set of storage units associated with the data segments. Based on a set of query requests, a response is received from a storage unit from the set of storage units. When the response indicates a storage environment that is unfavorable as compared to predetermined performance metrics, the storage network facilitates migration of encoded data slices associated with the storage unit to another storage unit.
    Type: Grant
    Filed: October 21, 2022
    Date of Patent: April 16, 2024
    Assignee: Pure Storage, Inc.
    Inventors: Ahmad Alnafoosi, Andrew D. Baptist, Greg R. Dhuse, Jason K. Resch, Ilya Volvovski
  • Patent number: 11960351
    Abstract: Systems and methods for propagating poison information are provided. Embodiments include receiving write data having a poison flag asserted indicating the data to be written to a memory device is erroneous. Embodiments further include converting the write data to a pre-fixed data pattern and generating a parity code, based upon, at least in part, the pre-fixed data pattern. Embodiments may also include injecting a correctable error into the write-data or parity code and writing the write data and parity code into the memory device. The correctable error injection may occur in the data or in the parity code and during the read the comparison may occur accordingly.
    Type: Grant
    Filed: August 29, 2022
    Date of Patent: April 16, 2024
    Assignee: Cadence Design Systems, Inc.
    Inventors: Dipakkumar Trikamlal Modi, Bikram Banerjee, Maddula Balakrishna Chaitanya
  • Patent number: 11954336
    Abstract: Methods, systems, and devices for dynamic memory management operation are described. A memory system may store data in a first block that includes a first type of memory cells configured to store a single bit of information (e.g., single level cells (SLCs)). The memory system may set a flag associated with the data indicating whether the data includes secure information and is to remain in a block that includes SLCs after a memory management operation (e.g., a garbage collection operation). The memory system may store, as part of the memory management operation for the first block and based on the flag, valid data of the first block in a second block that includes SLCs or a third block that includes a second type of memory cells configured to store two or more bits of information.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: April 9, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Xing Wang, Liu Yang, Xiaolai Zhu, Bin Zhao
  • Patent number: 11949440
    Abstract: A wireless transmit/receive unit (WTRU) may receive a constellation symbol that includes indications that each are associated with a respective WTRU of a plurality of WTRUs. The WTRU may determine that a first weight associated with a first indication of the indications is different than a second weight associated with a second indication of the indications. The indications may comprise indications of bits modulated at a multi-user constellation bit division multiple access modulator (MU-CBDMAM).
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: April 2, 2024
    Assignee: InterDigital Patent Holdings, Inc.
    Inventors: Fengjun Xi, Yuan Sheng Jin, Pengfei Xia, Oghenekome Oteri, Hanqing Lou, Nirav B. Shah, Robert L. Olesen
  • Patent number: 11947423
    Abstract: A method of operating a distributed storage system, the method includes identifying missing chunks of a file. The file is divided into stripes that include data chunks and non-data chunks. The method also includes identifying non-missing chunks available for reconstructing the missing chunks and reconstructing missing data chunks before reconstructing missing non-data chunks using the available non-missing chunks.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: April 2, 2024
    Assignee: Google LLC
    Inventors: Lidor Carmi, Christian Eric Schrock, Steven Robert Schirripa
  • Patent number: 11947409
    Abstract: An integrated circuit (IC) device for detecting errors within a register, the IC device includes registers and parity checking circuitry. The parity checking circuitry is coupled to the registers and comprises a first parity circuitry, a second parity circuit, and error detection circuitry. The first parity circuit receives first register values from the registers and determine a first value from the first register values. The second parity circuit is receives second register values from the registers and determines a second value from the second register values. The error detection circuitry compares the first value and the second value to detect a first error within the registers, and output an error signal indicating the first error.
    Type: Grant
    Filed: January 12, 2022
    Date of Patent: April 2, 2024
    Assignee: XILINX, INC.
    Inventors: Sarosh I. Azad, Aditi R. Ganesan
  • Patent number: 11947819
    Abstract: A method and device for testing a conversion relationship between different reading manners in a flash memory chip and a readable storage medium are provided. Block reading is respectively performed, a bit error rate file is recorded, a test starting point, a test ending point and a test step length are is set in a block, the bit error rate file of the number of times of corresponding page reading is respectively recorded, and the number of times of page reading that is closest to the proportion of block error codes are found from the proportion of page error codes, a conversion of the number of times of block reading and the number of times of page reading is completed, conversion coefficients of the block reading and the page reading can be calculated for blocks in different states of a life cycle.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: April 2, 2024
    Assignee: INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD.
    Inventor: Dong Li
  • Patent number: 11934581
    Abstract: The present disclosure provides a terminal vibration evaluation method performed by an electronic device. The method includes: acquiring an actual vibration curve of a target terminal when a target game scenario is displayed; acquiring a predefined vibration description file associated with the target game scenario, and determining a predefined vibration curve according to the predefined vibration description file; determining target deviation data between the actual vibration curve and the predefined vibration curve; and determining, according to the target deviation data, whether vibration of the target terminal matches the target game scenario. The present disclosure provides a measurement solution used for determining whether terminal vibration matches a game scenario (for example, a game sound and a game picture), which helps improve a matching degree between terminal vibration and the game scenario, thereby improving a sense of substitution of the game and a sense of immersion of a player.
    Type: Grant
    Filed: November 8, 2022
    Date of Patent: March 19, 2024
    Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Yanhui Lu, Kai Hong, Shili Xu, Haiyang Wu, Qitian Zhang, Jingjing Chen, Zhuan Liu
  • Patent number: 11934269
    Abstract: Multiple independent point-to-point memory channels are operated, by at least one controller, in parallel to form a wider memory channel. The memory components on these point-to-point channels include the ability to connect to multiple (e.g., 2) instances of these independent memory channels. The controller operates multiple instances of the wider channels with the memory components configured in a clamshell mode. A single memory component is also operated in clamshell mode to provide error correction code information, independently of the other wider channels, to multiple instances of the wider memory channel.
    Type: Grant
    Filed: February 16, 2023
    Date of Patent: March 19, 2024
    Assignee: Cadence Design Systems, Inc.
    Inventors: Amit Kedia, Kartik Dayalal Kariya, Sreeja Menon, Steven C. Woo
  • Patent number: 11934670
    Abstract: Systems and methods are described for efficiently performing various operations at the granularity of a consistency group (CG) within a cross-site storage solution. An example of one of the various operations includes an independent and parallel resynchronization approach that independently brings individual volumes of a CG to a steady state of in-synchronization (InSync), thereby contributing to scalability of CGs by supporting CGs having a large number of member volumes without requiring a change to the resynchronization process. Another example includes preserving dependent write-order consistency when a remote mirror copy goes out-of-synchronization (OOS) for any reason by driving all member volumes OOS responsive to any member volume becoming OOS. Yet another example includes independent creation of snapshots by member volumes to support efficient and on-demand creation by an application of a common snapshots of all or a subset of peered member volumes of a CG with which the application is associated.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: March 19, 2024
    Assignee: NetApp, Inc.
    Inventors: Murali Subramanian, Akhil Kaushik, Anoop Vijayan, Omprakash Khandelwal, Arun Kumar Selvam
  • Patent number: 11928018
    Abstract: Methods, systems, and devices for coordinated error protection are described. A set of data and an indication of whether a first management procedure performed by a memory device on the set of data detected one or more errors in the set of data may be received at a host device. At the host device, a second error management procedure may be performed on the set of data received from the memory device. Based on the received indication and the second error management procedure, multiple bits indicating whether one or more errors associated with the set of data were detected at the memory device, the host device, or both may be generated. The set of data may be validated or discarded based on the multiple bits.
    Type: Grant
    Filed: August 16, 2022
    Date of Patent: March 12, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Schaefer, Aaron P. Boehm
  • Patent number: 11929136
    Abstract: A memory-testing circuit configured to perform a test of reference bits in a memory. In a read operation, outputs of data bit columns are compared with one or more reference bit columns. The memory-testing circuit comprises: a test controller and association adjustment circuitry configurable by the test controller to associate another one or more reference bit columns or one or more data bit columns with the data bit columns in the read operation. The test controller can determine whether the original one or more reference bit columns have a defect based on results from the two different association.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: March 12, 2024
    Assignee: Siemens Industry Software Inc.
    Inventors: Jongsin Yun, Benoit Nadeau-Dostie, Harshitha Kodali
  • Patent number: 11928027
    Abstract: Embodiments include receiving fixed size error checking and correction data blocks and metadata at a memory controller. Embodiments may include performing data to symbol mapping based upon the fixed size data blocks and providing an output of the data to symbol mapping to a first encoder without metadata configured for full detection correction of single device error and to a second encoder with metadata configured for partial detection correction of single device error. Embodiments may include receiving data at a memory based upon an output from the first encoder and the second encoder and receiving data from the memory at a first decoder without metadata configured for full detection correction of single device error and at a second decoder with metadata configured for partial detection correction. Embodiments may include re-mapping symbol data from the first decoder and the second decoder to actual data and generating output data blocks and metadata.
    Type: Grant
    Filed: September 26, 2022
    Date of Patent: March 12, 2024
    Assignee: Cadence Design Systems, Inc.
    Inventors: Modi Dipakkumar Trikamlal, Maddula Balakrishna Chaitanya
  • Patent number: 11928019
    Abstract: A first serial management interface device includes one or more input/output pins and a controller coupled to the one or more input/output pins. The controller receives a first frame from a second serial management interface device via a first input/output pin and generates a first error code based on the first frame received from the second serial management interface device. The controller receives a second frame from the second serial management interface device via a second input/output pin subsequent to receiving the first frame. The second frame includes a second error code. The controller compares the first error code to the second error code to determine whether first error code and the second error code match.
    Type: Grant
    Filed: September 2, 2022
    Date of Patent: March 12, 2024
    Assignee: MARVELL ASIA PTE LTD
    Inventors: Dance Wu, Chuanhai Zhou, Hong Yu Chou
  • Patent number: 11924354
    Abstract: A method for ingesting data artifacts into a recovery pod may include: identifying, by a first controller, a data artifact for ingestion; pulling, by the first controller, the data artifacts into the first datastore; confirming, by second controller, that a first airlock between the first zone and the second zone and a second airlock between a third zone and the second zone are closed; opening, by the second controller, the first airlock; identifying, by the second controller, the data artifacts in the first datastore; pulling, by the second controller, the data artifacts into a second datastore; confirming that the first airlock and the second airlock are closed; opening, by the second controller, the second airlock; identifying, by a third controller, the data artifacts in the second zone datastore; pulling, by the third controller, the data artifacts into a third zone datastore; and closing, by the second controller, the second airlock.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: March 5, 2024
    Assignee: JPMORGAN CHASE BANK, N.A.
    Inventors: Nick Rosenberg, Jonathan Elvers, Antonio G. Jarufe, Scott D. Valentine
  • Patent number: 11922015
    Abstract: A storage network operates by: issuing a read threshold number of read slice requests to storage units of a set of storage units, where the read threshold number of read slice requests identifies a read threshold number of encoded slices of a set of encoded slices corresponding to a data segment; when one or more other encoded data slices of the read threshold number of encoded slices is not received within a time threshold, facilitating receiving a decode threshold number of encoded slices of the set of encoded slices; decoding the decode threshold number of encoded slices to produce recovered encoded data slices, wherein a number of the recovered encoded data slices corresponds to the read threshold number minus a number of the encoded slices received within the time threshold; and outputting the recovered encoded data slices and the encoded slices of the read threshold number of encoded slices received within the time threshold.
    Type: Grant
    Filed: October 11, 2022
    Date of Patent: March 5, 2024
    Assignee: Pure Storage, Inc.
    Inventors: Bruno H. Cabral, Wesley B. Leggette
  • Patent number: 11914887
    Abstract: A storage device and a data accessing method are disclosed, wherein the storage device includes a memory circuit and a control circuit. The memory circuit includes a plurality of multi-level cells, and each of the multi-level cells is configured to store at least a first bit, a second bit and a third bit in at least a first page, a second page and a third page. The control circuit is configured to read the first bits according to a one-time reading operation related to the first bits, read the second bits according to M-times reading operations related to the second bits, and read the third bits according to N-times reading operations related to the third bits, wherein the difference between M and N is less than or equal to one.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: February 27, 2024
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yung-Chun Li, Han-Wen Hu, Bo-Rong Lin, Huai-Mu Wang
  • Patent number: 11916570
    Abstract: The present disclosure generally relates to a codeword format for data storage and to methods and circuits for generating a codeword based on data to be written in memory and extracting data from a codeword read from memory. In an example, an integrated circuit includes a memory system and a controller circuit. The controller circuit is communicatively coupled to the memory system and is configured to: receive multi-bit data; generate a codeword based on the multi-bit data; and transmit to the memory system the codeword for writing to memory. The codeword has a format that includes first bit positions for the multi-bit data, second bit positions for a bitwise inversion of the multi-bit data, a third bit position for an odd parity value, and a fourth bit position for an even parity value. The odd and even parity values indicate an odd and even parity, respectively, of the multi-bit data.
    Type: Grant
    Filed: November 11, 2022
    Date of Patent: February 27, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Dominik Stefan Gerl, Annabelle Arnold
  • Patent number: 11915776
    Abstract: A method can include receiving a request to read data from a block of a memory device, identifying a block family associated with the block of the memory device, identifying a voltage distribution parameter value associated with the block family, wherein the voltage distribution parameter value reflects an aggregate value of a corresponding voltage distribution associated with a plurality of memory cells of the block family, and determining a set of read levels associated with the voltage distribution parameter value, wherein each read level in the set of read levels corresponds to a respective voltage distribution of at least one memory cell comprised by the block of the memory device. The block family can be identified using a data structure that maps block identifiers to corresponding block family identifiers. The voltage distribution parameter value can be identified using a data structure that maps block family identifiers to corresponding voltage parameter values.
    Type: Grant
    Filed: September 12, 2022
    Date of Patent: February 27, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Michael Sheperek, Kishore Kumar Muchherla, Shane Nowell, Mustafa N Kaynak, Larry J Koudele
  • Patent number: 11915778
    Abstract: A semiconductor memory device includes: a core unit including first and second memory cell groups; and a control circuit. The control circuit is configured to, in response to a read command including designation of a first address and designation of a second address, read first data from the first memory cell group, read second data from the second memory cell group, and output third data and fourth data in parallel. The first and second addresses correspond to the first and second memory cell groups, respectively. The designation of the second address is made after the designation of the first address. The third data corresponds to the read first data. The fourth data corresponds to the read second data.
    Type: Grant
    Filed: March 15, 2022
    Date of Patent: February 27, 2024
    Assignee: Kioxia Corporation
    Inventors: Daisuke Arizono, Akio Sugahara, Mitsuhiro Abe, Mitsuaki Honma
  • Patent number: 11901913
    Abstract: An error correction coding apparatus that performs error correction coding using, as an error correction code sequence, a frame of m bits×n symbols input in m-bit parallel, where m and n are positive integers, includes: an error correction coding circuit that performs error correction coding using, as information bits, m bits×n symbols including known bits assigned to a bit sequence specified in the error correction code sequence and generate error correction coded parity bits; and a selector that replaces the known bits of the error correction code sequence with the parity bits.
    Type: Grant
    Filed: August 31, 2022
    Date of Patent: February 13, 2024
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Hideo Yoshida, Tsuyoshi Yoshida, Yoshiaki Konishi, Kenji Ishii
  • Patent number: 11899531
    Abstract: A storage device and an operating method thereof are provided. The storage device includes a non-volatile memory and a storage controller. The storage controller includes a command and address generator, an error detection module, and an interface circuit. The command and address generator generates a first command, an address, and a second command, the second command including an error detection signal for detecting a communication error in the first command and the address. The error detection module generates the error detection signal from the first command and the address. The interface circuit sequentially transmits the first command, the address, and the second command to the non-volatile memory. The first command indicates a type of a memory operation to be performed in the non-volatile memory, and the second command corresponds to a confirm command.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: February 13, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sungwon Jeong, Moonsang Kwon, Younghoi Heo, Jaeshin Lee, Eun Jung
  • Patent number: 11899954
    Abstract: A memory system includes a main memory, an auxiliary memory, a redundancy circuit, an extension control terminal, and a multiplexer. The main memory has a line width, and includes a write data input. The auxiliary memory has the same line width as the main memory, and includes a write data input. The redundancy circuit includes and input and an output. The input is coupled to the write data input of the main memory. The multiplexer includes a first input, a second input, a control input, and an output. The first input is coupled to the write data input of the main memory. The second input is coupled to the output of the redundancy circuit. The control input is coupled to the extension control terminal. The output of the multiplexer is coupled to the write data input of the auxiliary memory.
    Type: Grant
    Filed: February 2, 2022
    Date of Patent: February 13, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Shobhit Singhal, Ruchi Shankar, Sverre Brubaek, Praveen Kumar N
  • Patent number: 11892909
    Abstract: A system and method for managing a reduction in capacity of a memory sub-system. An example method involving a memory sub-system: detecting a failure of at least one memory device of the set, wherein the failure affects stored data; notifying a host system of a change in a capacity of the set of memory devices; receiving from the host system an indication to continue at a reduced capacity; and updating the set of memory devices to change the capacity to the reduced capacity.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: February 6, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Luca Bert
  • Patent number: 11886289
    Abstract: A display device includes an external memory device which stores a first integrated circuit (“IC”) driving information, an internal memory device which stores a second IC driving information generated by copying the first IC driving information, a buffer which receives the second IC driving information and detects an electrostatic discharge current, an error correction code calculator which determines a first error correction code of the first IC driving information and a second error correction code of the second IC driving information when the electrostatic discharge current is detected, and an error correction code comparator which compares the first error correction code and the second error correction code. The internal memory device selectively updates the second IC driving information to the first IC driving information based on a result of a comparison of the first error correction code and the second error correction code.
    Type: Grant
    Filed: September 12, 2022
    Date of Patent: January 30, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Sang Kuk Kim
  • Patent number: 11886286
    Abstract: Generating data checksum for a data object including multiple data units comprises, for each data unit, obtaining a corresponding address of the data unit, and rotating the data unit based on said corresponding address of the data unit to generate a rotated data unit. A checksum value for the data object is determined based on said rotated data units.
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: January 30, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jonathan M. Haswell
  • Patent number: 11870498
    Abstract: A server that performs optical transmission using an optical transmission line includes a transmitter that transmits an optical signal to another server, a receiver that receives the optical signal from the other server, a storage device that stores data and an error correction code (ECC) added to the data, and a control unit that controls conversion of the data and the ECC into the optical signal, conversion of the optical signal into the data and the ECC, and error correction of the data using the ECC, and a transmission distance of the optical transmission line is a transmission distance for which an error rate does not exceed an allowable value of the error rate before correction which makes the error rate after correction based on the error correction using the ECC be equal to or less than a reference error rate.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: January 9, 2024
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Toshiya Matsuda, Kana Masumoto, Kazuyuki Matsumura
  • Patent number: 11868211
    Abstract: The present disclosure includes apparatuses, methods, and systems for error detection and correction in memory. An embodiment includes a memory having a group of self-selecting memory cells which store data corresponding to a codeword from an error correcting code, and circuitry configured to perform a sense operation on the group of self-selecting memory cells, identify, based on the sense operation, memory cells of the group that cannot store data, mark data sensed from the identified memory cells as erasures and perform an error correction operation on data sensed from the group of self-selecting memory cells with the data sensed from the identified memory cells marked as erasures.
    Type: Grant
    Filed: September 26, 2022
    Date of Patent: January 9, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Joseph M. McCrate, Robert J. Gleixner
  • Patent number: 11861191
    Abstract: Methods, systems, and devices for parameter table protection for a memory system are described. Upon booting a memory system for a first time, the memory system or a host system may generate an error control code associated with parameter data stored to the memory system. The error control code may be stored to the memory system and may be configured to correct one or more errors in the parameter data upon subsequent boot sequences of the memory system. Accordingly, upon booting the memory system for a second or a subsequent time, the error control code may be used to identify and correct errors in the parameter data, which may reduce the quantity of copies of parameter data stored to the memory system and may prevent the memory system from experiencing a system crash.
    Type: Grant
    Filed: October 13, 2021
    Date of Patent: January 2, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Binbin Huo
  • Patent number: 11861209
    Abstract: A memory system includes a memory device, a system memory, and a controller. The memory device includes a page storing a first chunk including first user data and first meta data and a second chunk including second user data and second meta data. The system memory stores an address map table for a physical address of the page in which the first chunk and the second chunk are stored and a logical address mapped to the physical address. The controller is configured to perform a read operation of the page by recovering the first meta data using the physical address of the first chunk and the address map table, and outputting the second user data using the second meta data of the second chunk on which an error correction operation has passed, when an error correction operation on the first chunk has failed.
    Type: Grant
    Filed: October 1, 2021
    Date of Patent: January 2, 2024
    Assignee: SK hynix Inc.
    Inventors: Hyo Byung Han, Jin Woo Kim, Jin Won Jang, Young Wu Choi
  • Patent number: 11860714
    Abstract: Methods, systems, and devices for error notification using an external channel are described. In some cases, a memory system having a host-driven logical block interface may issue a notification of a detected error using an out of band channel. For example, after receiving a data unit from a host system but prior to storing the data in a memory array of the memory system, the memory system may transmit an acknowledgment to host system to indicate that the data was successfully received. As part of storing the data, the memory system may transfer the data along data paths between various components and perform parity checks at each component. If the memory system detects an error along a data path, the memory system may issue a notification of the error to the host system over the out of band channel.
    Type: Grant
    Filed: October 20, 2022
    Date of Patent: January 2, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Yoav Weinberg, Chandrakanth Rapalli, Tal Sharifie
  • Patent number: 11847342
    Abstract: An apparatus for data storage, includes circuitry and a plurality of memory cells. The circuitry is configured to store data in a group of multiple memory cells by writing multiple respective input storage values to the memory cells in the group, to read respective output storage values from the memory cells in the group after storing the data, to generate for the output storage values multiple respective confidence levels, to produce composite data that includes the output storage values, to test a predefined condition that depends on the confidence levels, upon detecting that the condition is met, to compress the confidence levels to produce compressed soft data, and include the compressed soft data in the composite data, and to transfer the composite data over an interface to a memory controller.
    Type: Grant
    Filed: October 28, 2021
    Date of Patent: December 19, 2023
    Assignee: APPLE INC.
    Inventor: Nir Tishbi
  • Patent number: 11847022
    Abstract: Computation, placement, and accessing of error correcting codes (ECC) in a computer system data cache enabling partial reads and writes to each line of data in the cache. For storing multiple compressed blocks, received at differing time periods, in a single cache line, the ECC for the first compressed block is stored in the ECC field of the cache and the ECC for the second and subsequently received compressed blocks is appended to the compressed data. Additionally, an auxiliary ECC cache may be constructed for temporarily holding a partial ECC for a partial read/write, and a new ECC for the partial read/write is computed using the partial ECC.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: December 19, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bulent Abali, Alper Buyuktosunoglu, Brian Robert Prasky, Deanna Postles Dunn Berger
  • Patent number: 11837284
    Abstract: According to one embodiment, a semiconductor storage device includes a first memory cell capable of storing n-bit data (n is a natural number not less than 4). When receiving first data, including first and second bits of the n-bit data, from a controller, the semiconductor storage device writes the received first data to the first memory cell. After receiving the first data, when the semiconductor storage device receives second data including third and fourth bits of the n-bit data, the semiconductor storage device reads the first and second bits from the first memory cell and writes the n-bit data to the first memory cell based on the read first and second bits and the received second data.
    Type: Grant
    Filed: November 17, 2022
    Date of Patent: December 5, 2023
    Assignee: Kioxia Corporation
    Inventors: Masanobu Shirakawa, Takayuki Akamine
  • Patent number: 11838127
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for improving adaptive satellite communication. In some implementations, a method includes receiving, by a receiver and from a transmitter, code blocks transmitted according to a first set of parameters that comprises one or more of a first modulation used to transmit the code blocks or a first coding used to encode the code blocks for transmission. A number of corrupted code blocks and a number of parity blocks in a series of the code blocks received are determined. The number of corrupted code blocks are compared with the number of parity blocks. A second set of parameters are determined based on the comparison of the number of corrupted code blocks with the number of parity blocks. The second set of parameters are communicated to the transmitter for subsequent transmissions.
    Type: Grant
    Filed: March 11, 2022
    Date of Patent: December 5, 2023
    Assignee: Hughes Network Systems, LLC
    Inventors: Lin-nan Lee, Mustafa Eroz, Rohit Iyer Seshadri
  • Patent number: 11831332
    Abstract: Certain aspects of the present disclosure generally relate to techniques for puncturing of structured low-density parity-check (LDPC) codes. Certain aspects of the present disclosure generally relate to methods and apparatus for a high-performance, flexible, and compact LDPC code. Certain aspects can enable LDPC code designs to support large ranges of rates, blocklengths, and granularity, while being capable of fine incremental redundancy hybrid automatic repeat request (IR-HARD) extension while maintaining good floor performance, a high-level of parallelism to deliver high throughout performance, and a low description complexity.
    Type: Grant
    Filed: November 1, 2022
    Date of Patent: November 28, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Thomas Joseph Richardson, Shrinivas Kudekar
  • Patent number: 11822426
    Abstract: A memory system includes a memory device including a plurality of memory blocks, each block having a plurality of pages to store data; and a controller suitable for: selecting error-prone pages each having a number of errors, which exceeds a threshold, among the plurality of pages, based on the number of errors of each of the plurality of pages; ranking the error-prone pages based on the numbers of errors therein; and performing a test read operation on the error-prone pages based on the ranking.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: November 21, 2023
    Assignee: SK hynix Inc.
    Inventor: Jong-Min Lee
  • Patent number: 11798611
    Abstract: A memory access controller includes a request issuing circuit to issue a user request in response to a memory request, issue a refresh request at first issuing intervals, and issue a scrubbing request at second issuing intervals; and a command issuing circuit to issue a first active to a memory via a row command bus and issue M reads to the memory via a column command bus after the first active is issued, when memory access for the user request is to be executed, issue refresh to the memory via the row command bus when the memory access for the refresh request is executed, and issue a second active to the memory via the row command bus and issues N (>M) reads to the memory via the column command bus after the second active is issued, when the memory access for the scrubbing request is to be executed.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: October 24, 2023
    Assignee: FUJITSU LIMITED
    Inventor: Yuji Kondo
  • Patent number: 11799564
    Abstract: An approach is described for a method for a base station in a fifth generation (5G) wireless communication or a new radio (NR) system that includes the following steps. The method includes determining base initial seeds and a time parameter. The method further includes generating actual initial seeds based on the base initial seeds and the time parameter; generating a Pseudo-Noise (PN) sequence based on one of the actual initial seeds; and generating a remote interference management reference signal (RIM-RS) sequence based on the PN sequence. The method further includes transmitting the RIM-RS sequence to a remote base station.
    Type: Grant
    Filed: February 16, 2020
    Date of Patent: October 24, 2023
    Assignee: Apple Inc.
    Inventors: Hassan Ghozlan, Dawei Ying, Qian Li, Geng Wu
  • Patent number: 11789818
    Abstract: Methods, systems, and devices for coordinated error correction are described. A memory device indicates, to an external device, that errors were detected in data that was stored by the memory device and requested by the external device based on a comparison between an error correction code stored when the data was written to a memory array and an error correction code generated when the data is read from the memory array. Based on a result of the comparison, an indication of whether the compared error correction codes match is provided to the external device. The external device uses the indication to detect errors in the received version of the data, to manage data storage in the memory device, or both.
    Type: Grant
    Filed: March 9, 2022
    Date of Patent: October 17, 2023
    Inventors: Scott E. Schaefer, Aaron P. Boehm
  • Patent number: 11782787
    Abstract: Methods, systems, and devices for a dynamic error control configuration for memory systems are described. The memory system may receive a read command and retrieve a set of data from a location of the memory system based on the read command. The memory system may perform a first type of error control operation on the set of data to determine whether the set of data includes one or more errors. If the set of data includes the one or more errors, the memory system may retrieve a second set of data from the location of the memory system and determine whether a syndrome weight satisfies a threshold. The memory system may perform a second type of error control operation on the second set of data based on determining that the syndrome weight satisfies the threshold.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: October 10, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Deping He, Zhengang Chen
  • Patent number: 11775444
    Abstract: Driving address translations in a microprocessor system by sending a rejected Lx+1 cache request from a first set of caches of a first level Lx to a central request unit, transferring an Lx+1 cache request having a translation of a virtual address into a physical address stored in a first buffer, from the central request unit to the at least one Lx+1 cache, and keeping an Lx+1 cache request lacking a translation of a virtual address into a physical address stored in the first buffer, pending in the central request unit.
    Type: Grant
    Filed: March 15, 2022
    Date of Patent: October 3, 2023
    Assignee: International Business Machines Corporation
    Inventors: Willm Hinrichs, Markus Kaltenbach, Simon Hermann Friedmann, Joerg Deutschle, Thomas G. Koehler
  • Patent number: 11775384
    Abstract: In general, according to one embodiment, a memory system includes: a memory; and a memory controller including an error detection code circuit configured to generate a first error detection code from first data and generate a second error detection code from second data containing the first error detection code. The memory controller is configured to: convert the first data and the second error detection code by a first method and generate third data; and write the third data into the memory.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: October 3, 2023
    Assignee: Kioxia Corporation
    Inventor: Shinichi Kanno