Abstract: Methods, systems, and devices for error detection and classification at a host device are described. A host device may communicate a read command for a codeword stored at a memory device. In response to communicating the read command, the host device may receive the codeword and an error indication bit that indicates whether the memory device detected an error in the codeword. The host device may use the codeword to generate a set of syndrome bits. The host device may determine an error status of the codeword based on the error indication bit for the codeword and the set of syndrome bits for the codeword.

Abstract: An operation method of a memory controller, which is configured to control a memory module including a plurality of memory devices and at least one error correction code (ECC) device, is provided. The method includes reading a data set including user data stored in the plurality of memory devices and ECC data stored in the at least one ECC device, based on a read command and a first address, and writing uncorrectable data in a memory area, which is included in each of the plurality of memory devices and the at least one ECC device and corresponds to the first address, when an error of the user data is not corrected based on the ECC data.

Abstract: A processing device receives a request to write data to a memory device. The processing device generates a codeword based on the data. The codeword comprises the data and error correction code. The processing device generates a compressed codeword by compressing the codeword. The processing device stores the compressed codeword on a page of the memory device.

Abstract: Embodiments of the present disclosure relate to an UFS device and an operating method thereof. According to the embodiments of the present disclosure, the UFS device may collect status information of the UFS device, create an Acknowledgement and Flow Control (AFC) frame including the collected status information, and transmit the AFC frame to a host performing communication with the UFS device.

Abstract: An integrated circuit (IC) device includes an error correction code (ECC) encoder circuitry configured to receive input data, determine min-terms in a Hamming matrix (H-Matrix) corresponding to the input data, and generate ECC data based on the min-terms and an output codeword based on the ECC data, and an error correction circuitry configured to generate a corrected output codeword based on the output codeword.

Abstract: A memory system having an interconnect configured to receive commands from a system to read data from and/or write data to a memory device. The memory system also has a bridge configured to receive the commands from the interconnect, to manage ECC data and to perform address translation between system addresses and physical memory device addresses by calculating a first ECC memory address for a first ECC data block that is after and adjacent to a first data block having a first data address, calculating a second ECC memory address that is after and adjacent to the first ECC block, and calculating a second data address that is after and adjacent to the second ECC block. The bridge may also check and calculate ECC data for a complete burst of data, and/or cache ECC data for a complete burst of data that includes read and/or write data.

Abstract: A processing system of a storage network operates by receiving a write request associated with a data object; identifying dispersed storage error encoding parameters; and determining a number of available storage units. When the number of available storage units is determined to exceed a first number, the processing system operates by: determining a first write threshold number in accordance with the dispersed storage error encoding parameters; dispersed error encoding the data object to produce a first write threshold number of encoded data slices; and writing, to available storage units, the first write threshold number of encoded data slices.

Abstract: Methods, systems, and devices for read window management in a memory system are described. A memory system may determine, for a set of memory cells, a first value for a read window that is associated with a set of one or more threshold voltages each representing a different multi-bit value. The memory system may then use the first value for the read window to predict a second value for the read window. Based on the second value for the read window, the memory system may predict an error rate for the set of memory cells. The memory system may then set a value for an offset for a threshold voltage of the set of one or more threshold voltages based on the error rate.

Abstract: Methods, apparatus, systems and articles of manufacture to reduce bank pressure using aggressive write merging are disclosed. An example apparatus includes a first cache storage; a second cache storage; a store queue coupled to at least one of the first cache storage and the second cache storage and operable to: receive a first memory operation; process the first memory operation for storing the first set of data in at least one of the first cache storage and the second cache storage; receive a second memory operation; and prior to storing the first set of data in the at least one of the first cache storage and the second cache storage, merge the first memory operation and the second memory operation.

Abstract: The application provides a method for accessing data of a NAND FLASH file, a device and a storage medium. The method comprises: dividing a specified storage space assigned for specified NAND FLASH files into a first storage space and a second storage space; storing the management data of the specified NAND FLASH files in the first storage space, and storing the valid data of the specified NAND FLASH files in the second storage space; reading the valid data of the specified NAND FLASH files stored in the second storage space according to the management data of the specified NAND FLASH files stored in the first storage space. The present application can simplify the reading process of the specified NAND FLASH file data, reduce the reading time and improve the reading efficiency.

Abstract: A memory device having on-die error checking and correction (ECC) circuitry can provide uncorrected data in response to a read command. The ECC circuitry can perform error correction for errors detected, generating the corrected data in parallel with providing the uncorrected data. The memory device stores the corrected data internally to the memory device. When an error is detected, the memory device provides an indication to the memory controller, which can then request the corrected data.

Abstract: A method for execution in a storage network begins by performing a key derivation function on a password to produce a key and issuing a set of passwords based on the key to a set of storage units, where a data object is dispersed error encoded in accordance with dispersed error encoding parameters to produce a set of encoded data slices and the set of encoded data slices are stored in the set of storage units. The method continues, by receiving at least a decode threshold number of confidential information responses from the set of storage units and regenerating a set of keys for the confidential information responses. The method then continues by decrypting the confidential information responses using the set of keys to reproduce a set of encoded data slices and dispersed storage error decoding a decode threshold number of the set of encoded data slices to produce recovered data.

Abstract: Systems, methods, and apparatuses of using biometric information to authenticate a first device of a user to a second device are described herein. A method includes storing, by the first device, a first key share of a private key and a first template share of a biometric template of the user. The second device stores a public key, and one or more other devices of the user store other key shares and other template shares. The first device receives a challenge message from the second device, measures biometric features of the user to obtain a measurement vector, and sends the measurement vector and the challenge message to the other devices. The first device receives partial computations, generated using a respective template share, key share, and the challenge message, from the other devices, uses them to generate a signature of the challenge message and send the signature to the second device.

Abstract: A program startup method, an electronic system, and a non-transitory storage medium are disclosed in the embodiments of the present disclosure. The method includes detecting a startup requirement for a program, startup codes of the program being at least partially stored in an external memory, and a part of the startup codes stored in the external memory comprising a plurality of code segments; and performing an operation of loading one of the code segments of the external memory to a RAM and running the one of the code segments multiple times. The one of the code segments loaded each time is different with each other. A size of each code segment is less than or equal to a size of an area of the RAM capable of executing each code segment.

Abstract: A memory device and a system that implements a single symbol correction, double symbol detection (SSC-DSD+) error correction scheme are provided. The scheme is implemented by calculating four syndrome symbols in accordance with a Reed-Solomon (RS) codeword; determining three location bytes in accordance with three corresponding pairs of syndrome symbols in the four syndrome symbols; and generating an output based on a comparison of the three location bytes. The output may include: corrected data responsive to determining that the three location bytes match; an indication of a detected-and-corrected error (DCE) responsive to determining that two of the three location bytes match; or an indication of a detected-yet-uncorrected error (DUE) responsive to determining that none of the three location bytes match. A variant of the SSC-DSD+ decoder may be implemented using a carry-free subtraction operation to perform sanity checking.

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit, a fault address register, a scrubbing control circuit and a control logic circuit. The memory cell array includes memory cell rows. The scrubbing control circuit generates scrubbing addresses based on refresh operations performed on the memory cell array. The control logic circuit controls the ECC circuit such that the ECC circuit performs an error detection operation on a plurality of sub-pages in a first memory cell row to count a number of error occurrences, and determines whether to correct a codeword in which an error is detected based on the number of error occurrences. An uncorrected or corrected codeword is written back, and a row address of the first memory cell row may be stored in the fault address register as a row fault address based on the number of error occurrences.

Abstract: Apparatuses including a graphics processing unit, graphics multiprocessor, or graphics processor having an error detection correction logic for cache memory or shared memory are disclosed. In one embodiment, a graphics multiprocessor includes cache or local memory for storing data and error detection correction circuitry integrated with or coupled to the cache or local memory. The error detection correction circuitry is configured to perform a tag read for data of the cache or local memory to check error detection correction information.

Abstract: Methods, systems, and devices for error status determination at a memory device are described. A memory device may generate, based on syndrome bits for a codeword read from a memory, an error detection signal for the codeword that indicates whether an error has been detected in the codeword. The memory device may generate, based on the syndrome bits, an error correction signal for the codeword that indicates whether an error has been corrected in the codeword. And the memory device may provide an indication of the error detection signal and an indication of the error correction signal to a host device.

Abstract: A data processing system includes a controller configured to receive a first encoded data item and a write request from a host, the first encoded data item being encoded based on a hamming code. The controller is further configured to store the first encoded data item in a write buffer, decode the first encoded data item stored in the write buffer based on the hamming code to detect and correct a first error in the first encoded data item to obtain a first error-corrected data item, encode the first error-corrected data item based on an error correction code to generate a second encoded data item, and transmit the second encoded data item to program the second encoded data item in a non-volatile memory device.

Abstract: In an embodiment, an error correction code circuit is provided. The error correction code circuit includes an error correction code engine and data processing circuit. The error correction code engine is configured to generate a second parity signal and syndrome information by performing an operation on operation source data and a first parity signal. The data processing circuit is configured to output write data as the operation source data and output an internally generated dummy parity signal as the first parity signal during a write operation, and to output read data as the operation source data and output a read parity signal as the first parity signal during a read operation.

Abstract: The embodiments of the present disclosure provide a method and an Internet of Things (IoT) system for operation and management of a smart gas data center. The method is implemented by a smart gas management platform, comprising: obtaining gas data to be stored and downstream user features corresponding to the gas data to be stored; determining a data redundancy level of the gas data to be stored based on the gas data to be stored and the downstream user features; generating redundant data blocks of the gas data to be stored based on the data redundancy level; and storing the gas data to be stored and the redundant data blocks in at least one target region of the smart gas data center.

Abstract: The present disclosure is drawn to, among other things, a method for programming a memory device comprising a plurality of memory arrays. The method may include receiving a command to program one or more of the plurality of memory arrays and programming the one or more of the plurality of memory arrays based on the command. The method may optionally include erasing the one or more of the plurality of memory arrays prior to the programming.

Abstract: The methods and systems improve uncorrectable error (UE) and silent data corruption (SDC) rates for memory chips and improve error correction of the memory chips. The systems may include a memory bank with a plurality of memory chips in communication with a memory controller. The memory bank may use one additional memory chip that stores a bitwise parity of the data stored in the remaining memory chips of the memory bank. The parity bits are used to rebuild corrupted data when a UE occurs. The parity bits are also used to detect whether a SDC occurred in the data.

Abstract: A quantum computer uses interactions between atomic ensembles mediated by an optical cavity mode to perform quantum computations and simulations. Using the cavity mode as a bus enables all-to-all coupling and execution of non-local gates between any pair of qubits. Encoding logical qubits as collective excitations in ensembles of atoms enhances the coupling to the cavity mode and reduces the experimental difficulty of initial trap loading. By using dark-state transfers via the cavity mode to enact gates between pairs of qubits, the gates become insensitive to the number of atoms within each collective excitation, making it possible to prepare an array of qubits through Poissonian loading without feedback.

Abstract: Systems, apparatuses and methods may provide for technology that programs a first plurality of error correction codewords to a first set of pages in a block of non-volatile memory, wherein the first plurality of error correction codewords are programmed at a first density. The technology may also program a second plurality of error correction codewords to a second set of pages in the block, wherein the second plurality of error correction codewords are programmed at a second density. The first density and the second density are different from one another.

Abstract: Aspects of the present disclosure configure a system component, such as memory sub-system controller, to dynamically decode read data for zone-based memory allocations. The memory sub-system controller reads an entire memory block or zone. The memory sub-system controller decodes a first portion of the memory block or zone using a first decoding process. The memory sub-system controller determines that a second portion of the memory block or zone satisfies a criterion. In response, the memory sub-system controller applies a second decoding process to decode the second portion.

Abstract: Systems, methods, and instrumentalities are disclosed for retrieving information from tapes. The first group of read elements may be positioned adjacent to the first track and the second group of read element may be adjacent to the second track. In some embodiments, the system may include a second read sensor. Multiple readings of the electromagnetic fields generated by the first track may be collected using multiple read elements of the first group, A composite interpretation of a set of data encoded on the first track may be generated based on the multiple readings of the electromagnetic fields generated by the first track that are collected by the multiple read elements of the first group.

Abstract: A memory controller includes a request pipeline and a retry control circuit. The request pipeline receives an input of a request to a memory output from a processor core, stores the request, and causes the memory to process the request in order of storage. The retry control circuit stops a new request input to the request pipeline when an error occurs in the memory, and re-inputs, to the request pipeline, requests to be retried that includes the request in which the error has occurred and a subsequent request stored in the request pipeline.

Abstract: An error reporting system utilizes a parity checker to receive data results from execution of an original instruction and a parity bit for the data. A decoder receives an error correcting code (ECC) for data resulting from execution of a shadow instruction of the original instruction, and data error correction is initiated on the original instruction result on condition of a mismatch between the parity bit and the original instruction result, and the decoder asserting a correctable error in the original instruction result.

Abstract: Disclosed are a method for managing data and a storage device thereof. The storage device includes at least one memory including a plurality of planes, each plane includes a plurality of blocks, and peer blocks in different planes are belonged to operate in a multi-plane mode. The plurality of blocks are detected to find a unavailable block. Then, available blocks corresponding to the unavailable block in planes other than the plane where the unavailable block is located are marked as backup blocks that do not operate in the multi-plane mode. A first block with effective data is selected from the plurality of blocks operating in the multi-plane mode. Data of the first block is moved to a backup block in the same plane.

Abstract: A memory controller can include media controllers respectively coupled to memory devices. A first set of media controllers can be enabled during a first operating mode of the memory controller and a second set of media controller can be enabled during a second operating mode of the memory controller, during which some features, such as low-power features, can be disabled. Data accessed by each media controller of the first set can be aligned prior to being further transmitted to other circuitries of the memory controller that are dedicated, for example, for the low-power features.

Abstract: Implementations described herein relate to command address fault detection. A memory device may receive, from a host device via a command address (CA) bus, a plurality of CA bits associated with a command signal or an address signal. The memory device may receive, from the host device via the CA bus, a first set of parity bits that is based on the plurality of CA bits and a select parity generation process. The memory device may generate a second set of parity bits, based on the plurality of CA bits, using the select parity generation process. The memory device may compare the first set of parity bits and the second set of parity bits. The memory device may selectively transmit an alert signal to the host device based on comparing the first set of parity bits and the second set of parity bits.

Abstract: A method includes generating parity data corresponding to a plurality of word lines coupled to blocks of a memory device and generating additional parity data for a block based on a physical location of the block. The method can further include performing a data recovery operation based on the parity data, the additional parity data, or a combination thereof.

Abstract: Embodiments relate to detecting a timeout error on receipt of valid pixel data from an image sensor by a sensor interface circuit. When the valid pixel data is not timely received at the sensor interface circuit, a timeout error signal is generated by the sensor interface circuit. A time limit for determining the timeout error signal may be defined by a global clock that provides a clock signal to the sensor interface circuit and other circuits. As a result, the sensor interface circuit generates a dummy frame and sends out the dummy frame to subsequent circuits so that the timeout error does not bottleneck subsequent processing stages. In contrast, if the valid pixel data is timely received, sensor data received from the image sensor is unpacked into a frame of pixels.

Abstract: A memory system includes a semiconductor memory device and a memory controller configured to control the semiconductor memory device. The semiconductor memory device includes a memory cell array including a plurality of memory cells configured to store data, a refresh controller configured to control a refresh operation with respect to the plurality of memory cells, and an error monitoring circuit configured to generate error information by monitoring an error in the data stored in the memory cell array based on refresh sensing data provided from the memory cell array during the refresh operation. The memory controller includes an error correction code (ECC) circuit and is further configured to correct the error in the data stored in the memory cell array using the ECC circuit based on the error information.

Abstract: A system includes a memory component and a processing device, operatively coupled with the memory component, to generate a physical presence security identification (PSID) for the memory component using a statistically random number generator. The processing device, operatively coupled with the memory component, can securely retrieve the PSID and revert the memory component to an original state using the PSID.

Abstract: A system includes: a processor; a register configured to store a plurality of words, non-volatile memory having a plurality of cells, each cell corresponding to one of the words of the register, and wherein the each cell of the plurality of cells are set to an initial reset value; a first controller that in response to a loss in power: determines the word stored by the register; and changes the initial reset value of the cell of the non-volatile memory corresponding to the determined word stored by the register to a set value; a second controller that in response to detecting a restoration in power: identifies the cell having the set value; writes the word corresponding to the identified cell to the register; and resets the cells of the non-volatile memory to the initial reset value.

Abstract: In a wireless communication network, a wireless access node receives an encrypted slice certificate from a wireless user device and transfers the encrypted slice certificate to a network control-plane. The network control-plane decrypts the encrypted slice certificate and determines a correspondence between expected characteristics and the slice characteristics from the decrypted slice certificate. The network control-plane authorizes the wireless user device for the wireless network slice based on the correspondence. In response to the authorization, the network control-plane transfers user context for the wireless network slice to the wireless access node and a network user-plane. The wireless access node exchanges user data between the wireless user device and the network user-plane per the user context. The network user-plane exchanges the user data between the wireless access node and a data system per the user context.

Abstract: Disclosed is a method for preforming the data mirror comprising: receiving from an application executing on a computing device a request to write data to a first local persistence memory of the computing device; issuing an async write operation to mirror the write request to write a same data to a second local persistence memory of the computing device; performing a write operation to write the data to the first local persistence memory by using a central processing unit (CPU) from the processing resource of the computing device; determining, by an additional CPU, a status completion result indicating whether the async write operation is complete; and in response to determining the async write operation is complete, determining, by the additional CPU, a status check result indicating whether the async write operation is successful.

Abstract: The disclosure relates to a method of determining complexities and/or quality of video segments of a video program and providing data indicating the quality of video segments to user devices. Such data may be included in a manifest file of the video program. Based on the data indicating the complexities and/or quality of video segments, a user device or the system may choose a bitrate version for each video segment that minimizes network bandwidth usage while providing sufficient video quality.

Abstract: A storage unit is disclosed. The storage unit may include storage for a component codeword. The component codeword may be stored in a block in the storage. The block may also store a block codeword. An interface may receive a read request for a chunk of data from a host and may send the chunk of data to the host. A circuit may read the component codeword from the block in the storage. An error correcting code (ECC) decoder may determine the chunk of data based at least in part on the component codeword.

Abstract: An error detection circuit and method for performing cyclic redundancy check on a clock gated register signal is disclosed. The error detection circuit comprise a first register, a second register, a third register and an error detection module. The first register is a clock gated register and is configured to be updated with a data signal (x) in response to a clock enabling signal. The second register is configured to be updated with a check bit (c) based on the data signal (x). The check bit is calculated by a check bit calculation unit. The third register is configured to be updated with a current value (b) of the clock enabling signal. The error detection module is configured for calculating an indication bit (I) based on at least the output of the first register, the output of the second register and the output of the third register.

Abstract: A memory system includes a memory including nonvolatile memory cells, and a controller configured to set read voltages for reading data stored in the nonvolatile memory cells. The controller stores first shift patterns relating to a plurality of read voltages, first index information associating to a first shift pattern with each of a plurality of memory cell groups, second shift patterns relating to differences between read voltages and read voltages set according to a first shift pattern, and second index information associating a second shift pattern with each memory cell group. The controller generates read voltages of a target memory cell group based on the first shift pattern voltages and the second shift pattern voltages.

Abstract: A channel encoder for encoding a frame includes a multi-mode redundancy encoder for redundancy encoding the frame in accordance with a certain coding mode from a set of different coding modes, wherein the coding modes are different from each other with respect to an amount of redundancy added to the frame, wherein the multi-mode redundancy encoder is configured to output a coded frame including at least one code word; and a colorator for applying a coloration sequence to the at least one code word; wherein the coloration sequence is such that at least one bit of the code word is changed by the application of the at least one of coloration sequence, wherein the specific coloration sequence is selected in accordance with the certain coding mode.

Abstract: Disclosed are an online program update method and device for an optical amplifier. The method comprises: when a program update instruction is sent, a Microcontroller Unit MCU receiving update programs of MCU and a programmable logic device FPGA, storing them in a program memory device, and sending an update instruction to FPGA; FPGA terminating; operations of a digital-to-analog converter DAC according to the instruction and a current state remaining unchanged; MCU loading new codes of MCU and FPGA while DAC remains in state of halting refreshing; and after MCU and FPGA run the new codes, reading previously stored data, and starting switching from a previous operation state to enter normal operation state. On basis of conventional optical amplifier control, the invention combines characteristics of MCU and FPGA, and ensures uninterrupted service of optical amplifiers, achieving smooth transition of services, thereby improving stability and reliability of whole optical communications systems.

Abstract: A memory system is provided. The memory system includes an error correction code circuit configured to correct a maximum of N error bits in each of multiple read data and a monitor circuit configured to monitor multiple fail word addresses associated with M error bits, and further configured to output a first word address in the fail word addresses to replace first memory locations corresponding to the first word address. Each of the fail word addresses corresponds to one of multiple counter values, and the first word address corresponds to a maximum value of the counter values.

Abstract: Systems, apparatus, and methods related to configurable data protection circuitry. A memory includes a plurality of memory devices and a memory controller that can be coupled to the memory via a plurality of channels. The channels comprise respective subsets of the plurality of memory devices. The memory controller comprises data protection circuitry to accommodate a first codeword configuration of a number of codewords responsive to the plurality of memory devices having a first operating mode corresponding to a first input/output (I/O) width and accommodate a second codeword configuration of the number of codewords responsive to the plurality of memory devices having a second operating mode corresponding to a second I/O width, as well as switch between the first operating mode of the plurality of memory devices and the second operating mode of the plurality of memory devices.

Abstract: Systems and methods of the present disclosure may be used to improve equalization module architectures for NAND cell read information. For example, embodiments of the present disclosure may provide for de-noising of NAND cell read information using a Multiple Shallow Threshold-Expert Machine Learning Models (MTM) equalizer. An MTM equalizer may include multiple shallow machine learning models, where each machine learning model is trained to specifically solve a classification task (e.g., a binary classification task) corresponding to a weak decision range between two possible read information values for a given NAND cell read operation. Accordingly, during inference, each read sample with a read value within a weak decision range is passed through a corresponding shallow machine learning model (e.g., a corresponding threshold expert) that is associated with (e.g., trained for) the particular weak decision range.

Abstract: An electronic circuit and method for self-diagnosis of a data memory (RAM) is described comprising/using a first error correction code unit (ECCGEN1) for generating an error correction code (ECCIN) from user data (DIN) to be written into the data memory (RAM). The electronic circuit is arranged to feed the user data (DIN) written into the memory and the related error correction code (ECCIN) into the error check unit (ECCCHK/CORR) in the write cycle when writing the user data and the related error correction code (ECCIN) into the data memory (RAM) to provide a Latent Fault flag in case of a determined difference between the error correction code (ECCIN) and the countercheck code (CCCIN) calculated from the user data (DIN) by the error check unit (ECCCHK/CORR).

Abstract: A memory system includes a memory device and a memory controller. The memory device includes a plurality of memory cells. The memory controller includes an error correction code (ECC) circuit. The ECC circuit is configured to determine data rows of first write data that are not all zeros and store the determined data rows in buffer rows of a buffer along with corresponding row indexes. The memory controller is configured to write second data based on the buffer to the memory device.