Memory Access Patents (Class 714/763)
  • Patent number: 11567671
    Abstract: Embodiments of the present disclosure relate to a method, an electronic device, and a computer program product for storage management. The method for storage management includes determining the data volume of corresponding failed data in a plurality of candidate sub-storage spaces of a disk, the plurality of candidate sub-storage spaces being formed by dividing the original storage space of the disk and having consecutive physical addresses, and the size of one candidate sub-storage space being associated with the size of the storage space of at least one block that constitutes the disk; and selecting a target sub-storage space to be released from the plurality of candidate sub-storage spaces based at least on the data volume of the corresponding failed data. As such, since the operation of moving valid data in an SSD block to a new SSD block is reduced, the WAF of a storage system, especially an SSD, can be effectively reduced, and the service life of the SSD can be prolonged.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: January 31, 2023
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Yi Wang, Jun Tang, Qingxiao Zheng
  • Patent number: 11561730
    Abstract: Managing input/output (‘I/O’) queues in a data storage system, including: receiving, by a host that is coupled to a plurality of storage devices via a storage network, a plurality of I/O operations to be serviced by a target storage device; determining, for each of a plurality of paths between the host and the target storage device, a data transfer maximum associated with the path; determining, for one or more of the plurality of paths, a cumulative amount of data to be transferred by I/O operations pending on the path; and selecting a target path for transmitting one or more of the plurality of I/O operations to the target storage device in dependence upon the cumulative amount of data to be transferred by I/O operations pending on the path and the data transfer maximum associated with the path.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: January 24, 2023
    Assignee: Pure Storage, Inc.
    Inventors: Ronald Karr, John Mansperger
  • Patent number: 11561857
    Abstract: A method for the secured storing of a data element to be stored by a computer program in an external memory, which is connected to a microcontroller, the microcontroller including an interface module, which is configured to calculate error correction values for data elements including, when creating the computer program, during a determination of memory addresses of the computer program, determining a memory address in the external memory for the data element, a shared memory space requirement of data element and associated error correction value being taken into account; and during execution of the computer program, receiving the data element by the interface module; calculating an error correction value for the data element by the interface module; and writing, starting at the memory address, the data element and immediately thereafter the calculated error correction value within one addressing phase by the interface module.
    Type: Grant
    Filed: May 11, 2021
    Date of Patent: January 24, 2023
    Assignee: Robert Bosch GmbH
    Inventors: Martin Assel, Axel Aue, Matthias Schreiber
  • Patent number: 11562101
    Abstract: A programmable logic device verifies that configuration data permissibly programs the programmable logic device. The programmable logic device includes a programmable fabric having partitions to be programmed by the configuration data, a secure device manager that may generate masks based on the configuration data, and a local sector manager. The masks determine that the configuration data is configured to permissibly program the permitted partitions or that the permitted partitions have been permissibly programmed. The local sector manager applies the masks to generate an interleaved result, compares the interleaved result to an expected result, and sends an indication that the configuration data is configured to permissibly program the permitted partitions or permissibly programmed the permitted partitions in response to determining that the interleaved result is the expected result, or sends an alert to stop programming in response to determining that the interleaved result is not the expected result.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: January 24, 2023
    Assignee: Intel Corporation
    Inventors: Scott J. Weber, Sean R. Atsatt, Andrew Martyn Draper, David Samuel Goldman
  • Patent number: 11556267
    Abstract: A method includes performing a copyback operation comprising transferring, using an internal processing device, user data and header data corresponding to the user data from a first block of memory in a memory device to a register in the memory device, decoupling the user data from the header data, performing an error correction code (ECC) operation on updated header data using an external processing device, transferring, via the external processing device, the updated header data to the register, and transferring the user data and the updated header data from the register to a second block of memory in the memory device.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: January 17, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kishore K. Muchherla, Niccolo′ Righetti, Jeffrey S. McNeil, Jr., Akira Goda, Todd A. Marquart, Mark A. Helm, Gil Golov, Jeremy Binfet, Carmine Miccoli, Giuseppina Puzzilli
  • Patent number: 11551776
    Abstract: A memory device includes a memory cell array including memory cells arranged in a plurality of rows; an ECC engine configured to detect an error in first data that is read from the memory cell array in response to a read command and a read address, to output a first error occurrence signal, and to correct the error in the first data; a row fail detector configured to output a fail row address, which indicates a fail row among the plurality of rows; and a flag generator configured to receive the read address, the first error occurrence signal, and the fail row address, and to generate a decoding state flag, which indicates whether an error is detected and whether an error is corrected, and a fail row flag, which indicates that a read row address included in the read address is the fail row address.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: January 10, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Rae Kim, Myung Kyu Lee, Ki Jun Lee, Jun Jin Kong, Yeong Geol Song, Jin-Hoon Jang
  • Patent number: 11546000
    Abstract: A mobile electronic device may include a memory device and a memory controller including an error correction code (ECC) encoder to encode data, a constrained channel encoder configured to encode an output of the ECC encoder based on one or more constraints, a reinforcement learning pulse programming (RLPP) component configured to identify a programming algorithm for programming the data to the memory device, an expectation maximization (EM) signal processing component configured to receive a noisy multi-wordline voltage vector from the memory device and classify each bit of the vector with a log likelihood ration (LLR) value, a constrained channel decoder configured to receive a constrained vector from the EM signal processing component and produce an unconstrained vector, and an ECC decoder configured to decode the unconstrained vector. A machine learning interference cancellation component may operate based on or independent of input from the EM signal processing component.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: January 3, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Amit Berman, Ariel Doubchak, Eli Haim, Evgeny Blaichman
  • Patent number: 11538534
    Abstract: Calibration of soft bit reference levels in a non-volatile memory system is disclosed. When the soft bit reference levels are to be calibrated, encoded data is read from a group of the memory cells. The encoded data is decoded and error corrected. Therefore, the original data that was programmed into the memory cells is recovered. The group of memory cells are sensed at candidate soft bit reference levels, and possibly other reference levels. For each candidate soft bit reference level, mutual information between the original programmed data and the data for that candidate soft bit reference level is determined. The mutual information serves as a good measure for how well the candidate soft bit reference level will aid in decoding the data. In an aspect, a soft bit reference level having the highest mutual information out of several candidates is selected as the calibrated soft bit reference level.
    Type: Grant
    Filed: June 8, 2021
    Date of Patent: December 27, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ran Zamir, Alexander Bazarsky, Eran Sharon
  • Patent number: 11527294
    Abstract: A system includes a memory device including a plurality of groups of memory cells and a processing device that is operatively coupled to the memory device. The processing device is to receive a request to determine a reliability of the plurality of groups of memory cells. The processing device is further to perform, in response to receipt of the request, a scan operation on a sample portion of the plurality of groups of memory cells to determine a reliability of the sample portion that is representative of the reliability of the plurality of groups of memory cells.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: December 13, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Vamsi Pavan Rayaprolu, Karl D. Schuh, Jeffrey S. McNeil, Jr., Kishore K. Muchherla, Ashutosh Malshe, Jiangang Wu
  • Patent number: 11520486
    Abstract: A backup data storage system includes non-volatile memory units, a disk interface coupled to at least some of the non-volatile memory units, a connection component that facilitates exchanging data with the backup data storage system, and a smart network interface controller, coupled to the disk interface and the connection component to provide tape emulation to a host coupled to the backup data storage system. The disk interface, the connection component, and the smart network interface controller may be coupled using a PCIe bus. Tape data written to the backup storage device may be stored on the non-volatile memory units. A processor coupled to the smart network interface controller and the disk interface may receive the data from the smart network interface controller and may provide the data to the disk interface to store the data on the non-volatile memory units. The connection component may be a FICON connection component.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: December 6, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Adnan Sahin, Douglas E. LeCrone, Ian Wigmore
  • Patent number: 11515897
    Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: November 29, 2022
    Assignee: SK hynix Inc.
    Inventors: Kyoung Lae Cho, Soo Jin Kim, Naveen Kumar, Aman Bhatia, Yi-Min Lin, Chenrong Xiong, Fan Zhang, Yu Cai, Abhiram Prabahkar
  • Patent number: 11514175
    Abstract: When a client requests a data import job, a remote storage service provider provisions a shippable storage device that will be used to transfer client data from the client to the service provider for import. The service provider generates security information for the data import job, provisions the shippable storage device with the security information, and sends the shippable storage device to the client. The service provider also sends client-keys to the client, separate from the shippable storage device (e.g., via a network). The client receives the device, encrypts the client data and keys, transfers the encrypted data and keys onto the device, and ships it back to the service provider. The remote storage service provider authenticates the storage device, decrypts client-generated keys using the client-keys stored at the storage service provider, decrypts the data using the decrypted client-side generated keys, and imports the decrypted data.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: November 29, 2022
    Assignee: Amazon Technologies, Inc.
    Inventors: Frank Paterra, Firat Basarir
  • Patent number: 11508399
    Abstract: According to one embodiment, a magnetic disk device includes a disk, a head, and a controller setting a rewrite threshold value for executing a rewrite process of different tracks in a first sector group including at least one first sector continuous from a first parity sector in which error correction processing in units of tracks is executable based on the first parity sector and including the first parity sector, and a second sector group including at least one second sector continuous in which the error correction processing in units of tracks is unexecutable, and rewriting the first sector group and the second sector group with different frequencies.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: November 22, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Nobuhiro Maeto
  • Patent number: 11500721
    Abstract: A reading method for solid-state disk returns data and/or information depending on state information. A data unit stored in the solid-state disk comprises metadata and a plurality of sectors including at least two sectors of user data, the metadata comprising a sector state set indicating state information of each of the sectors in the data unit, and the state information comprising a valid state and an invalid state. In response to receiving a read command from a host to read at least one of the sectors in the data unit, the solid-state disk returns actual data to the host for one or more of the sectors in the valid state, and returns information indicating a read error to the host for one or more of the sectors in the invalid state, according to the sector state set stored in the metadata of the data unit.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: November 15, 2022
    Assignee: INNOGRIT TECHNOLOGIES CO., LTD.
    Inventors: Zhengtian Feng, Jie Chen, Ke Wei, Jing Gao, Tao Wei
  • Patent number: 11494107
    Abstract: Disclosed herein are techniques for managing parity information for data stored on a storage device. A method includes (1) receiving a request to store data into the storage device, (2) storing portions of the data in data pages included in stripes in a band of the storage device, where a respective data page is stored on a respective different die of a respective stripe, (3) determining primary parity information for a first stripe including a subset of the data pages, (4) storing the primary parity information in a primary parity page included in a second stripe in the stripes in the band, where the primary parity page is disposed on a next available die relative to dies storing the data pages, (5) determining secondary parity information for the second stripe, and (6) storing the secondary parity information in a secondary parity page included in the stripes in the band.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: November 8, 2022
    Assignee: Apple Inc.
    Inventors: Alexander Paley, Andrew W. Vogan, Evgeny Televitckiy
  • Patent number: 11487614
    Abstract: A semiconductor storing apparatus capable of shortening a ECC processing time of a readout operation is provided, including a flash memory includes: a memory cell array; a page buffer/sense circuit holding data read out from a selected page of the memory cell array; an error correcting code circuit receiving data from the page buffer/sense circuit and holding error address information of the data; an output circuit selecting data from the page buffer/sense circuit based on a column address, and outputting the selected data to a data bus; and an error correction part correcting data of the data bus based on the error address information.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: November 1, 2022
    Assignee: Winbond Electronics Corp.
    Inventor: Makoto Senoo
  • Patent number: 11487544
    Abstract: The present disclosure generally relates to a method and device for simultaneously decoding data. Rather than sending data to be decoded to a single decoder, the data can be sent to multiple, available decoders so that the data can be decode in parallel. The data decoded from the first decoder that completes decoding of the data will be delivered to the host device. All remaining decoded data that was decoded in parallel will be discarded. The decoders operating simultaneously in parallel can operate using different parameters such as different calculation precision (power levels). By utilizing multiple decoders simultaneously in parallel, the full functionality of the data storage device's decoding capabilities are utilized without increasing latency.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: November 1, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Shay Benisty, Eran Banani, Yuri Ryabinin
  • Patent number: 11487610
    Abstract: Systems and methods are described, in which a parity error alert timing interlock is provided by first waiting for a timer to count a configured parity error pulse width value and then waiting for any in-progress memory operations to complete before deasserting a parity error alert signal that was asserted in response to the detection of a parity error in a command or address.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: November 1, 2022
    Assignee: Micron Technology, Inc.
    Inventors: William C. Waldrop, Vijayakrishna J. Vankayala, Scott E. Smith
  • Patent number: 11483013
    Abstract: Error correction procedures for a memory device including a memory die having an array of memory cells including a plurality of banks are described. The memory die includes a first error correcting code (ECC) circuit coupled with a first bank of memory cells, where the first ECC circuit is configured to perform operations associated with a first access operation (e.g., write operation) of the first bank of memory cells. The memory die further includes a second ECC circuit coupled with the first bank of memory cells, where the second ECC circuit is configured to perform ECC operations associated with a second access operation (e.g., read operation) of the first bank. In some cases, the first ECC circuit is located under the footprint of the array and the second ECC circuit is located outside the footprint of the array.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: October 25, 2022
    Assignee: Micron Technology, Inc.
    Inventor: John David Porter
  • Patent number: 11481151
    Abstract: A method performed by a controller of a solid state drive comprising receiving from a host a read request for read data stored in nonvolatile semiconductor storage devices of the solid state drive. The method also comprises identifying a first codeword and a second codeword, the first codeword and the second codeword comprising the read data corresponding to the read request. Responsive to the read request, the method comprises reading a first portion of the read data contained in the first codeword and reading a second portion of the read data contained in the second codeword, assembling the first portion and the second portion as assembled read data, and transferring the assembled read data to the host responsive to the read request. The first and second codewords are adjacently stored, and the assembled read data has a length that is greater than the length of the first and second codewords.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: October 25, 2022
    Assignee: Kioxia Corporation
    Inventors: Amit Jain, Gyan Prakash, Ashwini Puttaswamy
  • Patent number: 11482296
    Abstract: Technology for error correcting data stored in memory dies is disclosed. Codewords, which may contain data bits and parity bits, are stored on a memory die. The memory die is bonded to a control die through bond pads that allow communication between the memory die and the control die. The codewords are decoded at the control die based on the parity bits. If the control die successfully decodes a codeword, the control die may send the data bits but not the parity bits to a memory controller. By not sending the parity bits to the memory controller, substantial bandwidth is saved. Also, substantial power may be saved. For example, the interface between the control die and the memory controller could be a high speed interface.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: October 25, 2022
    Assignee: SanDisk Technologies LLC
    Inventors: Idan Alrod, Eran Sharon
  • Patent number: 11482294
    Abstract: A method of managing errors in a plurality of storage drives includes receiving, at a memory controller coupled to at least one storage medium in an SSD, a read command from a host interface. The method also includes retrieving, from the storage medium, read data corresponding to a plurality of data chunks to be retrieved in response to the read command, and determining that at least one data chunk of the plurality of data chunks is unable to be read, the at least one data chunk corresponding to a failed data chunk. And in response to determining the failed data chunk, sending to the host interface the read data including the failed data chunk or excluding the failed data chunk. And in response to the read command sending to the host interface status information about all data chunks.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: October 25, 2022
    Assignee: Kioxia Corporation
    Inventors: Neil Buxton, Shigehiro Asano, Steven Wells, Mark Carlson
  • Patent number: 11483435
    Abstract: A method is disclosed. For example, the method executed by a processor of a multi-function device (MFD) includes tracking a machine state of the MFD, predicting a potential defect based on a determination that the machine state is associated with a defect class of a plurality of different defect classes, determining a maintenance routine associated with the defect class, and executing the maintenance routine to prevent the potential defect.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: October 25, 2022
    Assignee: Xerox Corporation
    Inventors: Stuart A. Schweid, Martin L. Frachioni, David A. Vankouwenberg, David M. Gurak, Christopher Mieney
  • Patent number: 11468959
    Abstract: A memory device to program a group of memory cells to store multiple bits per memory cell. Each bit per memory cell in the group from a page. After determining a plurality of read voltages of the group of memory cells, the memory device can read the multiple pages of the group using the plurality of read voltages. For each respective page in the multiple pages, the memory device can determine a count of first memory cells in the respective page that have threshold voltages higher than a highest read voltage, among the plurality of read voltages, used to read the respective page. The count of the first memory cells can be compared with a predetermined range of a fraction of memory cells in the respective page to evaluate the plurality of read voltages (e.g., whether any of the read voltages is in a wrong voltage range).
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: October 11, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Sivagnanam Parthasarathy, James Fitzpatrick, Patrick Robert Khayat, AbdelHakim S. Alhussien
  • Patent number: 11467902
    Abstract: According to one general aspect, an apparatus may include a memory configured to store both data and metadata, such that for portions of data associated with the metadata, the data and metadata are interleaved such that a unit of metadata succeeds each power of two contiguous units of data. The apparatus may also include a memory manager circuit. The memory management circuit may be configured to receive a data access to the memory, wherein the data access includes a public memory address. The memory management circuit may be configured to determine if the public memory address is associated with metadata. The memory management circuit may be configured to, if so, convert the public memory address to a private memory address. The memory management circuit may be configured to complete the data access at the private memory address.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: October 11, 2022
    Inventor: Bryan D. Marietta
  • Patent number: 11461177
    Abstract: A data storage device may include a storage and a controller. The storage configured to store data. The controller configured to perform a normal read operation based on a default read voltage in accordance with a read request of a host device and to perform a read retry operation using at least one retry read voltage when the normal read operation fails. The controller may comprises a hit ratio table configured to store read success records as hit ratios of retry read voltages in association with workloads, each workload being associated with a set of retry read voltages, and a read voltage determiner configured to determine the workload when the normal read operation fails and to select the set of retry read voltages associated with the determined workload, the retry read voltages in the selected set being ordered from a highest hit ratio to a lowest hit ratio.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: October 4, 2022
    Assignee: SK hynix Inc.
    Inventor: Hyoung Lee Lee
  • Patent number: 11462291
    Abstract: Counters may be provided for individual word lines of a memory for tracking word line accesses. In some examples, multiple counters may be provided for individual word lines. In some examples, the counters may be included on the word lines. The counters may be incremented responsive to word line accesses in some examples. In some examples, the counters may be incremented responsive for a time period for which a word line is held open. In some examples, the counters may be incremented responsive to both word line accesses and time periods for which the word line is held open. In some examples, count values for the counters may be written back to the counters after incrementing. In some examples, the count values may be written back prior to receiving a precharge command.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: October 4, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Dong Pan
  • Patent number: 11461174
    Abstract: An integrated circuit includes an error correction code (ECC) encoder configured to generate a first set of check bits in response to a first set of data, a first set of inverters coupled to the ECC encoder and being configured to generate a second set of check bits in response to the first set of check bits, and a first memory cell array. The second set of check bits is inverted from the first set of check bits. The first memory cell array includes a first portion of memory cells configured to store the first set of data, and a second portion of memory cells coupled to the first set of inverters, and configured to store the second set of check bits.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: October 4, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Shih-Lien Linus Lu
  • Patent number: 11461017
    Abstract: A memory device includes a memory component that stores data. The memory device also includes a processor that receives a signal indicating that the memory component is coupled to the processor and retrieves information from the memory component. The information may include one or more algorithms capable of being performed by the memory component. The processor may then receive one or more packets associated with one or more data operations regarding the memory component. The processor may then perform the one or more data operations by using the memory component to employ the one or more algorithms.
    Type: Grant
    Filed: January 20, 2020
    Date of Patent: October 4, 2022
    Assignee: Micron Technology, Inc.
    Inventor: J. Thomas Pawlowski
  • Patent number: 11455210
    Abstract: The present disclosure includes apparatuses, methods, and systems for error detection and correction in memory. An embodiment includes a memory having a group of self-selecting memory cells which store data corresponding to a codeword from an error correcting code, and circuitry configured to perform a sense operation on the group of self-selecting memory cells, identify, based on the sense operation, memory cells of the group that cannot store data, mark data sensed from the identified memory cells as erasures and perform an error correction operation on data sensed from the group of self-selecting memory cells with the data sensed from the identified memory cells marked as erasures.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: September 27, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Joseph M. McCrate, Robert J. Gleixner
  • Patent number: 11450382
    Abstract: A memory cell can have a state in a valley between adjacent data states. A determination can be made whether a state of a memory cell is in a valley between adjacent distributions of states associated with respective data states. A signal indicative of a data state of the memory cell and whether the state of the memory cell is in the valley can be transmitted.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: September 20, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Sivagnanam Parthasarathy, Patrick R. Khayat, Mustafa N. Kaynak, Robert B. Eisenhuth
  • Patent number: 11444636
    Abstract: A quantum computing system and associated methods. An exemplary method includes generating a specification from a binary matrix and at least one quantum check operator. The binary matrix is based at least in part on a classical error correcting code and the quantum check operator(s) is/are based on at least one multiple-qubit Pauli operator. The specification indicates which ancilla qubits are to be coupled to which data qubits. The data qubits are prepared as a plurality of multiple-qubit entangled states. The exemplary method also includes directing quantum hardware components of the quantum computing system to couple each of selected ones of the data qubits to one or more of the ancilla qubits in accordance with the couplings indicated in the specification. Each of the plurality of multiple-qubit entangled states is coupled to a plurality of the ancilla qubits.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: September 13, 2022
    Assignee: ERROR CORP.
    Inventor: Dennis Lucarelli
  • Patent number: 11436083
    Abstract: A method, an apparatus, and a system for data address management in non-volatile memory. Write data is allocated to each of a plurality of multi-level pages configured for storage on a page of a non-volatile memory array. A digest is associated with the write data of one multi-level page based on an attribute for that multi-level page. This attribute differs from the attributes of at least one of the other multi-level pages. An amount of redundancy data to be stored with write data on the multi-level page is reduced to account for the associated digest. A digest may be distributed among a plurality of ECC codewords of a multi-level page. The reduced redundancy data, the digest, and the write data for the multi-level page are stored on the page along with the write data for each of the other multi-level pages of the plurality of multi-level pages.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: September 6, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventor: Vimal Kumar Jain
  • Patent number: 11437115
    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, row fault detector circuitry and control logic circuitry. The memory cell array includes a plurality of memory cell rows. The control logic circuitry controls the ECC engine circuitry to perform a plurality of error detection operations on each of the memory cell rows. The control logic circuitry controls the row fault detector circuitry to store an error parameter associated with each of a plurality of codewords in each of which at least one error is detected by accumulating the error parameter for each of a plurality of defective memory cell rows. The row fault detector circuitry determines whether a row fault occurs in each of the plurality of defective memory cell rows based on a number of changes of the error parameter.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: September 6, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sungrae Kim, Kijun Lee, Myungkyu Lee, Hoyoun Kim, Suhun Lim, Sunghye Cho
  • Patent number: 11431692
    Abstract: The present disclosure relates to implementations of computing systems. Specifically, the disclosure describes implementations of computing systems that use ternary states for implementing security systems.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: August 30, 2022
    Assignee: ARIZONA BOARD OF REGENTS ON BEHALF OF NORTHERN ARIZONA UNIVERSITY
    Inventors: Paul Flikkema, Bertrand Francis Cambou
  • Patent number: 11429485
    Abstract: Memories using end-to-end data protection using physical location checks are described. In one aspect, a storage device includes non-volatile memory and a controller coupled to the memory. The controller may receive a write instruction including a data word and a logical address, include metadata with the word including error correction data, identify a physical address in a mapping table based on the logical address, generate a tag corresponding to the physical address, and replace the error correction data with the generated tag or a value based thereon before writing the data word to memory. In one embodiment, the controller may generate the tag concurrently with performing a logical error check using the error correction data.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: August 30, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Atif Hussain, Robert Ellis, Vivek Shivhare, Stephen Gold
  • Patent number: 11424002
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory including a plurality of cell units, each of the plurality of cell units including a plurality of memory cells, and a memory controller. The memory controller is configured to: read first data from a first cell unit, using a first correction amount of a read voltage; identify an address of an error bit in the first data; update the first correction amount to a second correction amount, based on the first data and the address of the error bit of the first data; and read second data from a second cell unit different from the first cell unit, using a third correction amount based on the second correction amount.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: August 23, 2022
    Assignee: Kioxia Corporation
    Inventors: Naomi Takeda, Ryo Yamaki, Masanobu Shirakawa
  • Patent number: 11409597
    Abstract: An error reporting system utilizes a parity checker to receive data results from execution of an original instruction and a parity bit for the data. A decoder receives an error correcting code (ECC) for data resulting from execution of a shadow instruction of the original instruction, and data error correction is initiated on the original instruction result on condition of a mismatch between the parity bit and the original instruction result, and the decoder asserting a correctable error in the original instruction result.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: August 9, 2022
    Assignee: NVIDIA Corp.
    Inventors: Michael Sullivan, Siva Hari, Brian Zimmer, Timothy Tsai, Stephen W. Keckler
  • Patent number: 11393519
    Abstract: The present disclosure relates to a semiconductor memory device. The semiconductor memory device includes memory cell array, error correction code (ECC) engine, refresh control circuit and control logic circuit. The memory cell array includes memory cell rows. The refresh control circuit performs a refresh operation on the memory cell rows. The control logic circuit controls the ECC engine such that the ECC engine generates an error generation signal by performing ECC decoding on sub-pages in at least one first memory cell row during a read operation. The control logic circuit compares an error occurrence count of the first memory cell row with a threshold value and provides the refresh control circuit with a first address of the first memory cell row as an error address based on the comparison. The refresh control circuit increases a number of refresh operations performed in the first memory cell row during a refresh period.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: July 19, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yunkyeong Jeong, Chulhwan Choo
  • Patent number: 11386970
    Abstract: A memory system includes a plurality of memory cells, and the memory cells are multiple-level cells. The memory system performs program operations to program the memory cells. After each program operation, at least one threshold voltage test is performed to determine if threshold voltages of the memory cells are greater than the verification voltage. When the threshold voltage of a first memory cell is determined to be greater than a first verification voltage, the first memory cell will be inhibited from being programmed during the next program operation. When the threshold voltage of a second memory cell is determined to newly become greater than a second verification voltage, where the second verification voltage is greater than the first verification voltage, the second memory cell will be programmed again during the next program operation.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: July 12, 2022
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Haibo Li, Man Lung Mui
  • Patent number: 11387993
    Abstract: Methods, systems, and apparatus for transmitting qubits encoding quantum information with reduced risk of interception from an eavesdropper. In one aspect, a method includes encoding quantum information into an information qubit; encrypting the information qubit, comprising performing i) a parity operation on the information qubit and a parity control qubit and ii) a phase operation on the information qubit and a phase control qubit; performing, by a sender party, a sequence of one or more quantum logic gates on the phase control qubit; sending the information qubit, parity control qubit, and phase control qubit to a recipient party; and sending data identifying the sequence of one or more quantum logic gates to the recipient party, wherein the recipient party obtains the quantum information encoded into the information qubit using the information qubit, parity control qubit, phase control qubit, and data identifying the sequence of one or more quantum logic gates.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: July 12, 2022
    Assignee: Accenture Global Solutions Limited
    Inventors: Benjamin Glen McCarty, Malek Ben Salem
  • Patent number: 11379366
    Abstract: Memory devices might include an input/output (I/O) node, a termination device, an array of memory cells in communication with the I/O node through the termination device, and control circuitry, wherein the control circuitry is configured to compare an address received by the memory device to a plurality of instances of address information stored in the memory device. Each instance of address information of the plurality of instances of address information might correspond to a respective termination value stored in the memory device. In response to the memory device receiving an address matching an instance of address information stored in the memory device, the control circuitry might further be configured to activate the termination device using the respective termination value corresponding to the instance of address information matching the received address.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: July 5, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Terry Grunzke
  • Patent number: 11381252
    Abstract: A method for decoding a codeword includes partitioning the codeword into a plurality of component codewords where each of the component codewords comprising a respective plurality of bits. The respective plurality of bits in each of the plurality of component codewords are interleaved. Each of the plurality of interleaved component codewords are decoded along two dimensions to produce (i) a set of first decoding results and (ii) a set of second decoding results. A short error event is then detected and corrected based on (i) the set of first decoding results and (ii) the set of second decoding results.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: July 5, 2022
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Nedeljko Varnica, Mats Oberg
  • Patent number: 11372717
    Abstract: Methods and apparatuses for a system error-correcting code function are presented. The apparatus includes a memory configured to communicate with a host. The memory includes a memory array configured to store data. The memory is configured to provide the data stored in the memory array to the host in performing computing functions and configured to provide an error-correction code (ECC) associated with the data to the host. The ECC is not stored in the memory array in a first configuration of the memory and is stored in the memory array in a second configuration of the memory.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: June 28, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Jungwon Suh, Michael Hawjing Lo, Dexter Tamio Chun, Xavier Loic Leloup, Laurent Rene Moll
  • Patent number: 11372715
    Abstract: Error correction code (ECC) hardware includes write generation (Gen) ECC logic and a check ECC block coupled to an ECC output of a memory circuit with read Gen ECC logic coupled to an XOR circuit that outputs a syndrome signal to a syndrome decode block coupled to a single bit error correction block. A first MUX receives the write data is in series with an input to the write Gen ECC logic or a second MUX receives the read data from the memory circuit in series with an input of the read Gen ECC logic. A cross-coupling connector couples the read data from the memory circuit to a second input of the first MUX or for coupling the write data to a second input of the second MUX. An ECC bit comparator compares an output of the write Gen ECC logic to the read Gen ECC logic output.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: June 28, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Saket Jalan, Indu Prathapan, Abhishek Ganapati Karkisaval
  • Patent number: 11366717
    Abstract: A method for error correction and a system. The method may include opening a selected row of a memory bank out of multiple memory banks of a dynamic memory module; and while the selected row is open: (i) receiving selected data sub-blocks that are targeted to be written to the selected row, (ii) calculating selected error correction code sub-blocks that are related to the selected data sub-blocks, (iii) caching the selected error correction code sub-blocks in a cache memory that differs from the dynamic memory module and (iv) writing, to the selected row, the selected error correction code sub-blocks.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: June 21, 2022
    Assignee: Mobileye Vision Technologies Ltd.
    Inventors: Leonid Smolyansky, Boris Shulman, Yosef Kreinin
  • Patent number: 11366715
    Abstract: A device includes a first component having a data input and a data output. The deice further includes an error correction code (ECC) generation circuit having an input coupled to the data input of the first component. The ECC generation circuit has an output. A second component has a data input coupled to the output of the ECC generation circuit. The second component has a data output. An ECC error detection circuit has a first data input coupled to the data output of the first component, and a second data input coupled to the data output of the second component.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: June 21, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Desmond Fernandes, Indu Prathapan, Jasbir Singh, Prathap Srinivasan, Rishav Karki
  • Patent number: 11347583
    Abstract: A method of correcting errors in a data storage system including a first node, a second node, and shared persistent storage (the first and second nodes being configured to process data storage requests) is provided. The method includes (a) reading cached pages from a first cache disposed within the first node, the cached pages being cached versions of respective persistent pages stored in the shared persistent storage; (b) in response to determining that one of the cached pages is corrupted, requesting that the second node return to the first node a corresponding remote page from a second cache disposed within the second node, the cached page and the remote page each caching a same persistent page of the shared persistent storage; and (c) in response to determining that the remote page received from the second node by the first node is not corrupted, correcting the cached page using the remote page.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: May 31, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Philippe Armangau, Vamsi K. Vankamamidi, Geng Han, Xinlei Xu
  • Patent number: 11349498
    Abstract: A memory device having a Low-Density Parity-Check (LDPC) decoder that is energy efficient and has a low error floor. The decoder is configured to determine syndromes of bits in a codeword, select bits in the codeword based at least in part on the syndromes according to a first mode, and flip the selected bits in the codeword. The decoder can repeat the bit selection and flipping operations to iteratively improve the codeword and reduce parity violations. Further, the decoder can detect a pattern in parity violations of the codeword in its iterative bit flipping operations. In response, the decoder can change from the first mode to a second mode in bit selection for flipping. For example, the decoder can transmit from a dynamic syndrome mode to a static syndrome mode in response to the pattern of repeating a cycle of bit flipping iterations.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: May 31, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Mustafa N. Kaynak, Sivagnanam Parthasarathy
  • Patent number: 11347582
    Abstract: A method for the self-diagnosis of RAM error detection logic of a powertrain controller includes: idling, by a first core, an operation of a second core; testing an error correction code (ECC) module corresponding to a RAM operating by the second core; idling, by the second core, an operation of a core of a plurality of un tested cores; and testing an ECC module corresponding to a RAM operating by the core of the plurality of untested cores.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: May 31, 2022
    Assignee: HYUNDAI AUTOEVER CORP.
    Inventor: Byung-Jin Min