Memory Access Patents (Class 714/763)
  • Patent number: 12386698
    Abstract: This disclosure discloses a memory chip and an operating method thereof. The operating method incudes: determining whether a quantity of one or more written memory units in a storage space of the one or more storage spaces is less than or equal to a preset quantity or a write address corresponding to a write instruction is smaller than one of storage addresses of the storage space; in response to determining that the quantity of the one or more written memory units in the storage space is less than or equal to the preset quantity or the write address corresponding to the write instruction is smaller than the one of storage addresses of the storage space, determining an operating state of the storage space as a part programmed state; and disabling an error correction mechanism for the storage space in the part programmed state.
    Type: Grant
    Filed: December 19, 2023
    Date of Patent: August 12, 2025
    Inventor: Bin Wu
  • Patent number: 12367945
    Abstract: A memory system includes a plurality of memories, each including a plurality of data input terminals; and a memory controller configured to continuously transfer a first codeword and a second codeword to the data input terminals of the memories during a write operation.
    Type: Grant
    Filed: February 13, 2023
    Date of Patent: July 22, 2025
    Assignee: SK hynix Inc.
    Inventors: Sang Woo Yoon, Hoiju Chung, Yoonna Oh
  • Patent number: 12360703
    Abstract: A memory control method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: sending a plurality of read command sequences configured to instruct a rewritable non-volatile memory module to read a first physical unit by using a plurality of read voltage levels; after the read command sequences are sent, receiving first data from the rewritable non-volatile memory module, where the first data includes replacement data corresponding to a plurality of first bits reflecting a read result of a first memory cell by using the read voltage levels, and a data amount of the first data is less than a total data amount of the first bits; after the first data is received, performing data restoration on the first data to obtain a plurality of second bits; performing a decoding operation according to the second bits.
    Type: Grant
    Filed: January 2, 2024
    Date of Patent: July 15, 2025
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Yu-Hsiang Lin
  • Patent number: 12339742
    Abstract: Systems, apparatuses and methods may provide for memory controller technology including first logic to trigger, via an initial request, a hard-read and a soft-read, wherein the hard-read is to generate hard-bit information and the soft-read is to generate first soft-bit information and second soft-bit information, conduct a first error correction on the hard-bit information, and issue a subsequent request for at least the second soft-bit information if the first error correction is unsuccessful. Additionally, memory device technology may include a plurality of memory cells and second logic to conduct the hard-read and the soft-read from a memory cell in the plurality of memory cells in response to the initial request, send the hard-bit information to the controller, and withhold at least the second soft-bit information from the controller until the subsequent request is received.
    Type: Grant
    Filed: June 9, 2021
    Date of Patent: June 24, 2025
    Inventors: Ali Khakifirooz, George Kalwitz, Anand Ramalingam, Ravi Motwani, Renjie Chen
  • Patent number: 12332733
    Abstract: A first circuitry may have a first interface. A response circuitry having a system interface may connect to the first circuitry. The response circuitry may receive an input selection that determines an error handling mode used to respond to an error (e.g., in a lockstep system, the error could be a difference between an output at the first interface and a second output at a second interface identified by comparing the first output to the second output). In some implementations, the error handling mode may cause the response circuitry to provide the output to the system interface and send an indication to software based on detecting the error. In some implementations, the error handling mode may cause the response circuitry to contain at least a portion of the output by disabling at least a portion of the system interface for multiple clock cycles based on detecting the error.
    Type: Grant
    Filed: May 2, 2023
    Date of Patent: June 17, 2025
    Assignee: SiFive, Inc.
    Inventors: Cameron Mcnairy, Michael Klinglesmith
  • Patent number: 12314599
    Abstract: A data accessing method, a memory controlling circuit unit, and a memory storage device are provided. The method includes: reading a codeword stored in a physical programming unit, and calculating a bit change ratio of a bit value change in dummy data included in the codeword; adjusting a read voltage level or a log likelihood ratio according to the bit change ratio; and performing a decoding operation on the codeword by using the adjusted read voltage level or the adjusted log likelihood ratio.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: May 27, 2025
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Yu-Siang Yang, Wei Lin, Shih-Jia Zeng, An-Cheng Liu, Yu-Cheng Hsu
  • Patent number: 12301252
    Abstract: This application is directed to compressing check node data for an electronic device. The electronic device identifies a check node corresponding to a subset of codeword symbols in a block of data and determines check node data that indicates a likelihood of the subset of codeword symbols being erroneous. A set of data bits are determined based on a value combination of data items of the check node data to uniquely identify the value combination among a set of selected value combinations according to a predefined relationship. The electronic device stores, in a memory block, the set of data bits representing the data items of the check node data of the check node. Each data item requires more data bits to represent all possible values of the respective data item than data bits of the set of data bits.
    Type: Grant
    Filed: July 13, 2023
    Date of Patent: May 13, 2025
    Assignee: SK Hynix NAND Product Solutions Corp.
    Inventor: Zion Kwok
  • Patent number: 12301253
    Abstract: This application is directed to compressing check node data for an electronic device. The electronic device identifies a check node corresponding to a subset of codeword symbols in a block of data and determines check node data that indicates a likelihood of the subset of codeword symbols being erroneous. A set of data bits are determined based on a value combination of data items of the check node data to uniquely identify the value combination among a set of selected value combinations according to a predefined relationship. The electronic device stores, in a memory block, the set of data bits representing the data items of the check node data of the check node. Each data item requires more data bits to represent all possible values of the respective data item than data bits of the set of data bits.
    Type: Grant
    Filed: August 22, 2023
    Date of Patent: May 13, 2025
    Assignee: SK Hynix NAND Product Solutions Corp.
    Inventor: Zion Kwok
  • Patent number: 12301254
    Abstract: A processing device in a memory sub-system determines a syndrome weight for a sense word read from a memory device and determines whether the syndrome weight for the sense word satisfies a threshold criterion. Responsive to the syndrome weight for the sense word satisfying a respective threshold criterion associated with a next iteration of a first decoding operation, bypassing the first decoding operation and initiating a second decoding operation for the sense word, wherein the second decoding operation has a higher error correction capability than the first decoding operation.
    Type: Grant
    Filed: June 1, 2022
    Date of Patent: May 13, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Eyal En Gad, Mustafa N. Kaynak, Yoav Weinberg, Zhengang Chen, Sivagnanam Parthasarathy
  • Patent number: 12299302
    Abstract: A method for storing data may include receiving user data at a group of storage devices, wherein the storage devices are interconnected, erasure coding the user data into redundancy blocks at the group of storage devices, and storing the redundancy blocks on at least two of the storage devices. The erasure encoding may be distributed among at least two of the storage devices. The redundancy blocks may be arranged in reliability groups. The redundancy blocks may be grouped by the storage devices independently of the partitioning of the user data by the user. The method may further include recovering data based on redundancy blocks. A storage device may include a storage medium, a network interface configured to communicate with one or more other storage devices, and a storage processing unit configured to erasure code user data into redundancy blocks cooperatively with the one or more other storage devices.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: May 13, 2025
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Rekha Pitchumani, Yang Seok Ki
  • Patent number: 12292798
    Abstract: Apparatuses, systems, and methods for module level error correction. Multiple memory devices a packaged together in a memory module. The module includes a module error correction code (ECC) circuit which pools information multiple memory devices on the module. In an example read operation, multiple memory devices each provide a codeword which includes data bits and parity bits. The codewords may include data bits provided along a data bus and parity bits provided along a parity bus. The ECC circuit pools the codewords and detects errors in the pooled codewords.
    Type: Grant
    Filed: August 29, 2022
    Date of Patent: May 6, 2025
    Assignee: Micron Technology, Inc.
    Inventor: Sujeet Ayyapureddi
  • Patent number: 12277072
    Abstract: Aspects of the disclosure provide the memory system having a memory apparatus and a memory controller coupled with the memory apparatus. The memory apparatus includes at least one memory chip having a plurality of memory planes, each memory plane includes a plurality of pages, a plurality of pages located at the same position in each of the memory planes of the at least one memory chip form a page line, the memory apparatus includes a plurality of tag groups, each tag group includes a plurality of page lines. The memory controller can be configured to, when the memory apparatus is powered down and then powered on, respectively perform, in sequence, a recoding operation on all pages of which the states are programmed states in each tag group, and according to an encoding result corresponding to each tag group, respectively determine whether check data corresponding to each tag group is abnormal.
    Type: Grant
    Filed: December 29, 2022
    Date of Patent: April 15, 2025
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventor: Xianwu Luo
  • Patent number: 12277028
    Abstract: An apparatus comprises a storage configured to store data items associated with error correction codes (ECCs); data retrieval circuitry responsive to a data retrieval request specifying a retrieval address to retrieve a retrieved data item and an associated ECC from a storage location corresponding to the retrieval address; and ECC decoding circuitry to generate a syndrome value by performing an ECC decoding operation on a decoding input value comprising data bits of the retrieved data item, code bits of the associated ECC, and address bits of the retrieval address, and to determine based on the syndrome value whether an error condition has occurred. Each bit of the syndrome value depends on a different combination of bits of the decoding input value. For each data bit of the decoding input value, an odd number of bits of the syndrome value depend on that data bit. For each address bit of the decoding input value, an even number of bits of the syndrome value depend on that address bit.
    Type: Grant
    Filed: August 3, 2023
    Date of Patent: April 15, 2025
    Assignee: Arm Limited
    Inventors: Siddharth Gupta, Antony John Penton
  • Patent number: 12260914
    Abstract: Control logic in a memory device identifies a set of a plurality of memory cells configured as multi-level cell (MLC) memory to be programmed during a program operation and causes, at a first time during a program operation, a first programming pulse to be applied to a memory cell of the memory array to be programmed to a first programming level. The control logic further performs a program verify operation corresponding to the first programming level and compares a threshold voltage of the memory cell to one or more program verify voltage levels of the program verify operation to determine whether a condition is satisfied. The control logic further executes a level shifting operation in response to the condition to be satisfied.
    Type: Grant
    Filed: February 18, 2022
    Date of Patent: March 25, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Sheyang Ning, Lawrence Celso Miranda
  • Patent number: 12254218
    Abstract: An apparatus includes a control circuit configured connect to non-volatile memory cells. The control circuit is configured to receive a read command directed to data stored in non-volatile memory cells of a first word line and determine that a second word line adjacent to the first word line is sanitized. The control circuit is further configured to select an adjusted read voltage for a read operation directed to the non-volatile memory cells of the first word line based on the determination.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: March 18, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Md Raquibuzzaman, Sujjatul Islam, Ravi J. Kumar
  • Patent number: 12249388
    Abstract: A memory system includes a nonvolatile memory and a control circuit. The nonvolatile memory includes a plurality of word lines, a plurality of bit lines, and a plurality of storage elements. The control circuit includes an ECC circuit that detects and corrects a data error stored in the plurality of storage elements, acquires first data by reading data stored in the plurality of storage elements of a page connected to the same word line with a first read voltage, acquires second data obtained by correcting the first data when the first data can be corrected by the ECC circuit, and writes data based on the second data to the plurality of storage elements of the page.
    Type: Grant
    Filed: August 15, 2022
    Date of Patent: March 11, 2025
    Assignee: KIOXIA CORPORATION
    Inventor: Katsuhiko Iwai
  • Patent number: 12248690
    Abstract: A method for storing data may include receiving user data at a group of storage devices, wherein the storage devices are interconnected, erasure coding the user data into redundancy blocks at the group of storage devices, and storing the redundancy blocks on at least two of the storage devices. The erasure encoding may be distributed among at least two of the storage devices. The redundancy blocks may be arranged in reliability groups. The redundancy blocks may be grouped by the storage devices independently of the partitioning of the user data by the user. The method may further include recovering data based on redundancy blocks. A storage device may include a storage medium, a network interface configured to communicate with one or more other storage devices, and a storage processing unit configured to erasure code user data into redundancy blocks cooperatively with the one or more other storage devices.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: March 11, 2025
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Rekha Pitchumani, Yang Seok Ki
  • Patent number: 12241647
    Abstract: A building system that operates to receive a plurality of data samples from building equipment of the building and identity whether one or more data samples of the plurality of data samples are anomalous indicating that one or more pieces of the building equipment are possibly experiencing a fault. The building system operates to generate one or more data health scores for the building equipment based on whether the one or more data samples are anomalous, the one or more data health scores indicating quality levels of the plurality of data samples and generate user interface data configured to cause a user device to display a user interface providing indications of the one or more pieces of building equipment that are possibly experiencing the fault and the one or more data health scores.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: March 4, 2025
    Assignee: TYCO FIRE & SECURITY GMBH
    Inventors: Shawn D. Schubert, Vineet Binodshanker Sinha, Mohammad N. Elbsat, Michael J. Wenzel, Kirk H. Drees
  • Patent number: 12244678
    Abstract: A server system for managing electronic content receives the electronic content at a data flow adapter. The electronic content is to be stored at a data storage system. The server system attempts to transmit the electronic content from the data flow adapter to the data storage system but receives a notification indicating that the data storage system will not store the electronic content. In response to the notification, the server system temporarily stores the electronic content at a data staging memory. A staging data adapter polls the data staging memory for electronic content awaiting to be stored at the data storage system. The server system detects the electronic content stored at the data staging memory and, in response, causes the staging data adapter to move the electronic content from the data staging memory to the data storage system when the data storage system will store the electronic content.
    Type: Grant
    Filed: May 11, 2023
    Date of Patent: March 4, 2025
    Assignee: T-Mobile USA, Inc.
    Inventors: Vaishali Vijay Patil, Seshama Naidu Enaganti, Loganathan Kulanthaisamy, Ramkishan Sadasivam
  • Patent number: 12236104
    Abstract: An operation method of a memory controller, which is configured to control a memory module including a plurality of memory devices and at least one error correction code (ECC) device, is provided. The method includes reading a data set including user data stored in the plurality of memory devices and ECC data stored in the at least one ECC device, based on a read command and a first address, and writing uncorrectable data in a memory area, which is included in each of the plurality of memory devices and the at least one ECC device and corresponds to the first address, when an error of the user data is not corrected based on the ECC data.
    Type: Grant
    Filed: August 16, 2022
    Date of Patent: February 25, 2025
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dae-Jeong Kim, Tae-Kyeong Ko, Nam Hyung Kim, Do-Han Kim, Deokho Seo, Ho-Young Lee, Insu Choi
  • Patent number: 12237844
    Abstract: Methods, systems, and devices for error detection and classification at a host device are described. A host device may communicate a read command for a codeword stored at a memory device. In response to communicating the read command, the host device may receive the codeword and an error indication bit that indicates whether the memory device detected an error in the codeword. The host device may use the codeword to generate a set of syndrome bits. The host device may determine an error status of the codeword based on the error indication bit for the codeword and the set of syndrome bits for the codeword.
    Type: Grant
    Filed: October 7, 2022
    Date of Patent: February 25, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Aaron P. Boehm, Scott E Schaefer
  • Patent number: 12222805
    Abstract: A processing device receives a request to write data to a memory device. The processing device generates a codeword based on the data. The codeword comprises the data and error correction code. The processing device generates a compressed codeword by compressing the codeword. The processing device stores the compressed codeword on a page of the memory device.
    Type: Grant
    Filed: February 16, 2023
    Date of Patent: February 11, 2025
    Assignee: Micron Technology, Inc.
    Inventor: David Matthew Springberg
  • Patent number: 12216940
    Abstract: Embodiments of the present disclosure relate to an UFS device and an operating method thereof. According to the embodiments of the present disclosure, the UFS device may collect status information of the UFS device, create an Acknowledgement and Flow Control (AFC) frame including the collected status information, and transmit the AFC frame to a host performing communication with the UFS device.
    Type: Grant
    Filed: July 13, 2023
    Date of Patent: February 4, 2025
    Assignee: SK hynix Inc.
    Inventor: Moon Soo Choi
  • Patent number: 12212337
    Abstract: An integrated circuit (IC) device includes an error correction code (ECC) encoder circuitry configured to receive input data, determine min-terms in a Hamming matrix (H-Matrix) corresponding to the input data, and generate ECC data based on the min-terms and an output codeword based on the ECC data, and an error correction circuitry configured to generate a corrected output codeword based on the output codeword.
    Type: Grant
    Filed: March 30, 2023
    Date of Patent: January 28, 2025
    Assignees: XILINX, INC., Advanced Micro Devices, Inc.
    Inventors: Kumar Rahul, John J. Wuu, Santosh Yachareni
  • Patent number: 12204443
    Abstract: A memory system having an interconnect configured to receive commands from a system to read data from and/or write data to a memory device. The memory system also has a bridge configured to receive the commands from the interconnect, to manage ECC data and to perform address translation between system addresses and physical memory device addresses by calculating a first ECC memory address for a first ECC data block that is after and adjacent to a first data block having a first data address, calculating a second ECC memory address that is after and adjacent to the first ECC block, and calculating a second data address that is after and adjacent to the second ECC block. The bridge may also check and calculate ECC data for a complete burst of data, and/or cache ECC data for a complete burst of data that includes read and/or write data.
    Type: Grant
    Filed: August 14, 2023
    Date of Patent: January 21, 2025
    Assignee: Texas Instruments Incorporated
    Inventors: Denis Roland Beaudoin, Ritesh Dhirajlal Sojitra, Samuel Paul Visalli
  • Patent number: 12197768
    Abstract: A processing system of a storage network operates by receiving a write request associated with a data object; identifying dispersed storage error encoding parameters; and determining a number of available storage units. When the number of available storage units is determined to exceed a first number, the processing system operates by: determining a first write threshold number in accordance with the dispersed storage error encoding parameters; dispersed error encoding the data object to produce a first write threshold number of encoded data slices; and writing, to available storage units, the first write threshold number of encoded data slices.
    Type: Grant
    Filed: August 8, 2022
    Date of Patent: January 14, 2025
    Assignee: Pure Storage, Inc.
    Inventors: Jason K. Resch, Andrew D. Baptist, Niall J. McShane, Greg R. Dhuse, Thomas F. Shirley, Jr., Gregory Palinckx, Russell P. Kennedy, S. Christopher Gladwin, Robert C. McCammon, James Sherer
  • Patent number: 12197347
    Abstract: Methods, apparatus, systems and articles of manufacture to reduce bank pressure using aggressive write merging are disclosed. An example apparatus includes a first cache storage; a second cache storage; a store queue coupled to at least one of the first cache storage and the second cache storage and operable to: receive a first memory operation; process the first memory operation for storing the first set of data in at least one of the first cache storage and the second cache storage; receive a second memory operation; and prior to storing the first set of data in the at least one of the first cache storage and the second cache storage, merge the first memory operation and the second memory operation.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: January 14, 2025
    Assignee: Texas Instruments Incorporated
    Inventors: Naveen Bhoria, Timothy David Anderson, Pete Michael Hippleheuser
  • Patent number: 12198777
    Abstract: Methods, systems, and devices for read window management in a memory system are described. A memory system may determine, for a set of memory cells, a first value for a read window that is associated with a set of one or more threshold voltages each representing a different multi-bit value. The memory system may then use the first value for the read window to predict a second value for the read window. Based on the second value for the read window, the memory system may predict an error rate for the set of memory cells. The memory system may then set a value for an offset for a threshold voltage of the set of one or more threshold voltages based on the error rate.
    Type: Grant
    Filed: July 14, 2022
    Date of Patent: January 14, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Li-Te Chang, Murong Lang, Zhenming Zhou, Ting Luo
  • Patent number: 12182434
    Abstract: The application provides a method for accessing data of a NAND FLASH file, a device and a storage medium. The method comprises: dividing a specified storage space assigned for specified NAND FLASH files into a first storage space and a second storage space; storing the management data of the specified NAND FLASH files in the first storage space, and storing the valid data of the specified NAND FLASH files in the second storage space; reading the valid data of the specified NAND FLASH files stored in the second storage space according to the management data of the specified NAND FLASH files stored in the first storage space. The present application can simplify the reading process of the specified NAND FLASH file data, reduce the reading time and improve the reading efficiency.
    Type: Grant
    Filed: March 23, 2021
    Date of Patent: December 31, 2024
    Assignee: HANGZHOU EZVIZ SOFTWARE CO., LTD.
    Inventors: Shixiong Xu, Lei Guo, Dongfeng Zhou
  • Patent number: 12181966
    Abstract: A memory device having on-die error checking and correction (ECC) circuitry can provide uncorrected data in response to a read command. The ECC circuitry can perform error correction for errors detected, generating the corrected data in parallel with providing the uncorrected data. The memory device stores the corrected data internally to the memory device. When an error is detected, the memory device provides an indication to the memory controller, which can then request the corrected data.
    Type: Grant
    Filed: April 8, 2021
    Date of Patent: December 31, 2024
    Assignee: Intel Corporation
    Inventors: Kuljit S. Bains, Narasimha Lanka
  • Patent number: 12170717
    Abstract: A method for execution in a storage network begins by performing a key derivation function on a password to produce a key and issuing a set of passwords based on the key to a set of storage units, where a data object is dispersed error encoded in accordance with dispersed error encoding parameters to produce a set of encoded data slices and the set of encoded data slices are stored in the set of storage units. The method continues, by receiving at least a decode threshold number of confidential information responses from the set of storage units and regenerating a set of keys for the confidential information responses. The method then continues by decrypting the confidential information responses using the set of keys to reproduce a set of encoded data slices and dispersed storage error decoding a decode threshold number of the set of encoded data slices to produce recovered data.
    Type: Grant
    Filed: August 8, 2023
    Date of Patent: December 17, 2024
    Assignee: Pure Storage, Inc.
    Inventors: Jason K. Resch, Greg R. Dhuse, Bart R. Cilfone
  • Patent number: 12166890
    Abstract: Systems, methods, and apparatuses of using biometric information to authenticate a first device of a user to a second device are described herein. A method includes storing, by the first device, a first key share of a private key and a first template share of a biometric template of the user. The second device stores a public key, and one or more other devices of the user store other key shares and other template shares. The first device receives a challenge message from the second device, measures biometric features of the user to obtain a measurement vector, and sends the measurement vector and the challenge message to the other devices. The first device receives partial computations, generated using a respective template share, key share, and the challenge message, from the other devices, uses them to generate a signature of the challenge message and send the signature to the second device.
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: December 10, 2024
    Assignee: Visa International Service Association
    Inventors: Shashank Agrawal, Saikrishna Badrinarayanan, Payman Mohassel, Pratyay Mukherjee
  • Patent number: 12159147
    Abstract: A program startup method, an electronic system, and a non-transitory storage medium are disclosed in the embodiments of the present disclosure. The method includes detecting a startup requirement for a program, startup codes of the program being at least partially stored in an external memory, and a part of the startup codes stored in the external memory comprising a plurality of code segments; and performing an operation of loading one of the code segments of the external memory to a RAM and running the one of the code segments multiple times. The one of the code segments loaded each time is different with each other. A size of each code segment is less than or equal to a size of an area of the RAM capable of executing each code segment.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: December 3, 2024
    Assignee: AutoChips Inc.
    Inventor: Zhengpeng Li
  • Patent number: 12147302
    Abstract: Apparatuses including a graphics processing unit, graphics multiprocessor, or graphics processor having an error detection correction logic for cache memory or shared memory are disclosed. In one embodiment, a graphics multiprocessor includes cache or local memory for storing data and error detection correction circuitry integrated with or coupled to the cache or local memory. The error detection correction circuitry is configured to perform a tag read for data of the cache or local memory to check error detection correction information.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: November 19, 2024
    Assignee: Intel Corporation
    Inventors: Vasanth Ranganathan, Joydeep Ray, Abhishek R. Appu, Nikos Kaburlasos, Lidong Xu, Subramaniam Maiyuran, Altug Koker, Naveen Matam, James Holland, Brent Insko, Sanjeev Jahagirdar, Scott Janus, Durgaprasad Bilagi, Xinmin Tian
  • Patent number: 12148494
    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit, a fault address register, a scrubbing control circuit and a control logic circuit. The memory cell array includes memory cell rows. The scrubbing control circuit generates scrubbing addresses based on refresh operations performed on the memory cell array. The control logic circuit controls the ECC circuit such that the ECC circuit performs an error detection operation on a plurality of sub-pages in a first memory cell row to count a number of error occurrences, and determines whether to correct a codeword in which an error is detected based on the number of error occurrences. An uncorrected or corrected codeword is written back, and a row address of the first memory cell row may be stored in the fault address register as a row fault address based on the number of error occurrences.
    Type: Grant
    Filed: February 28, 2023
    Date of Patent: November 19, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kiheung Kim, Sanguhn Cha, Junhyung Kim, Sungchul Park, Hyojin Jung, Kyung-Soo Ha
  • Patent number: 12149259
    Abstract: A memory device and a system that implements a single symbol correction, double symbol detection (SSC-DSD+) error correction scheme are provided. The scheme is implemented by calculating four syndrome symbols in accordance with a Reed-Solomon (RS) codeword; determining three location bytes in accordance with three corresponding pairs of syndrome symbols in the four syndrome symbols; and generating an output based on a comparison of the three location bytes. The output may include: corrected data responsive to determining that the three location bytes match; an indication of a detected-and-corrected error (DCE) responsive to determining that two of the three location bytes match; or an indication of a detected-yet-uncorrected error (DUE) responsive to determining that none of the three location bytes match. A variant of the SSC-DSD+ decoder may be implemented using a carry-free subtraction operation to perform sanity checking.
    Type: Grant
    Filed: September 21, 2022
    Date of Patent: November 19, 2024
    Assignee: NVIDIA Corporation
    Inventors: Michael Brendan Sullivan, Nirmal R. Saxena, Stephen William Keckler
  • Patent number: 12141028
    Abstract: Methods, systems, and devices for error status determination at a memory device are described. A memory device may generate, based on syndrome bits for a codeword read from a memory, an error detection signal for the codeword that indicates whether an error has been detected in the codeword. The memory device may generate, based on the syndrome bits, an error correction signal for the codeword that indicates whether an error has been corrected in the codeword. And the memory device may provide an indication of the error detection signal and an indication of the error correction signal to a host device.
    Type: Grant
    Filed: October 4, 2022
    Date of Patent: November 12, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Scott E Schaefer
  • Patent number: 12125549
    Abstract: A data processing system includes a controller configured to receive a first encoded data item and a write request from a host, the first encoded data item being encoded based on a hamming code. The controller is further configured to store the first encoded data item in a write buffer, decode the first encoded data item stored in the write buffer based on the hamming code to detect and correct a first error in the first encoded data item to obtain a first error-corrected data item, encode the first error-corrected data item based on an error correction code to generate a second encoded data item, and transmit the second encoded data item to program the second encoded data item in a non-volatile memory device.
    Type: Grant
    Filed: August 1, 2023
    Date of Patent: October 22, 2024
    Assignee: MIMIRIP LLC
    Inventor: In Jong Jang
  • Patent number: 12126357
    Abstract: In an embodiment, an error correction code circuit is provided. The error correction code circuit includes an error correction code engine and data processing circuit. The error correction code engine is configured to generate a second parity signal and syndrome information by performing an operation on operation source data and a first parity signal. The data processing circuit is configured to output write data as the operation source data and output an internally generated dummy parity signal as the first parity signal during a write operation, and to output read data as the operation source data and output a read parity signal as the first parity signal during a read operation.
    Type: Grant
    Filed: December 20, 2022
    Date of Patent: October 22, 2024
    Assignee: SK hynix Inc.
    Inventors: Seon Woo Hwang, Seong Jin Kim, Jung Hwan Ji
  • Patent number: 12120179
    Abstract: The embodiments of the present disclosure provide a method and an Internet of Things (IoT) system for operation and management of a smart gas data center. The method is implemented by a smart gas management platform, comprising: obtaining gas data to be stored and downstream user features corresponding to the gas data to be stored; determining a data redundancy level of the gas data to be stored based on the gas data to be stored and the downstream user features; generating redundant data blocks of the gas data to be stored based on the data redundancy level; and storing the gas data to be stored and the redundant data blocks in at least one target region of the smart gas data center.
    Type: Grant
    Filed: September 11, 2023
    Date of Patent: October 15, 2024
    Assignee: CHENGDU QINCHUAN IOT TECHNOLOGY CO., LTD.
    Inventors: Zehua Shao, Yong Li, Bin Liu, Guanghua Huang
  • Patent number: 12112067
    Abstract: The present disclosure is drawn to, among other things, a method for programming a memory device comprising a plurality of memory arrays. The method may include receiving a command to program one or more of the plurality of memory arrays and programming the one or more of the plurality of memory arrays based on the command. The method may optionally include erasing the one or more of the plurality of memory arrays prior to the programming.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: October 8, 2024
    Assignee: Everspin Technologies, Inc.
    Inventors: Syed M. Alam, Iftekhar Rahman, Pedro Sanchez
  • Patent number: 12111726
    Abstract: The methods and systems improve uncorrectable error (UE) and silent data corruption (SDC) rates for memory chips and improve error correction of the memory chips. The systems may include a memory bank with a plurality of memory chips in communication with a memory controller. The memory bank may use one additional memory chip that stores a bitwise parity of the data stored in the remaining memory chips of the memory bank. The parity bits are used to rebuild corrupted data when a UE occurs. The parity bits are also used to detect whether a SDC occurred in the data.
    Type: Grant
    Filed: March 14, 2023
    Date of Patent: October 8, 2024
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventor: Monish Shah
  • Patent number: 12106815
    Abstract: Systems, apparatuses and methods may provide for technology that programs a first plurality of error correction codewords to a first set of pages in a block of non-volatile memory, wherein the first plurality of error correction codewords are programmed at a first density. The technology may also program a second plurality of error correction codewords to a second set of pages in the block, wherein the second plurality of error correction codewords are programmed at a second density. The first density and the second density are different from one another.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: October 1, 2024
    Assignee: Intel Coproration
    Inventors: Ravi Motwani, Pranav Kalavade, Rohit Shenoy, Rifat Ferdous
  • Patent number: 12106181
    Abstract: A quantum computer uses interactions between atomic ensembles mediated by an optical cavity mode to perform quantum computations and simulations. Using the cavity mode as a bus enables all-to-all coupling and execution of non-local gates between any pair of qubits. Encoding logical qubits as collective excitations in ensembles of atoms enhances the coupling to the cavity mode and reduces the experimental difficulty of initial trap loading. By using dark-state transfers via the cavity mode to enact gates between pairs of qubits, the gates become insensitive to the number of atoms within each collective excitation, making it possible to prepare an array of qubits through Poissonian loading without feedback.
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: October 1, 2024
    Assignees: Massachusetts Institute of Technology, President and Fellows of Harvard College
    Inventors: Vladan Vuletic, Joshua Ramette, Zachary Vendeiro, Mikhail Lukin
  • Patent number: 12106788
    Abstract: Systems, methods, and instrumentalities are disclosed for retrieving information from tapes. The first group of read elements may be positioned adjacent to the first track and the second group of read element may be adjacent to the second track. In some embodiments, the system may include a second read sensor. Multiple readings of the electromagnetic fields generated by the first track may be collected using multiple read elements of the first group, A composite interpretation of a set of data encoded on the first track may be generated based on the multiple readings of the electromagnetic fields generated by the first track that are collected by the multiple read elements of the first group.
    Type: Grant
    Filed: August 7, 2023
    Date of Patent: October 1, 2024
    Assignee: ChannelScience, LLC
    Inventor: Charles Sobey
  • Patent number: 12107602
    Abstract: Aspects of the present disclosure configure a system component, such as memory sub-system controller, to dynamically decode read data for zone-based memory allocations. The memory sub-system controller reads an entire memory block or zone. The memory sub-system controller decodes a first portion of the memory block or zone using a first decoding process. The memory sub-system controller determines that a second portion of the memory block or zone satisfies a criterion. In response, the memory sub-system controller applies a second decoding process to decode the second portion.
    Type: Grant
    Filed: June 6, 2022
    Date of Patent: October 1, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Curtis W. Egan
  • Patent number: 12099413
    Abstract: A memory controller includes a request pipeline and a retry control circuit. The request pipeline receives an input of a request to a memory output from a processor core, stores the request, and causes the memory to process the request in order of storage. The retry control circuit stops a new request input to the request pipeline when an error occurs in the memory, and re-inputs, to the request pipeline, requests to be retried that includes the request in which the error has occurred and a subsequent request stored in the request pipeline.
    Type: Grant
    Filed: January 26, 2023
    Date of Patent: September 24, 2024
    Assignee: Fujitsu Limited
    Inventor: Yasuhiro Kitamura
  • Patent number: 12099407
    Abstract: An error reporting system utilizes a parity checker to receive data results from execution of an original instruction and a parity bit for the data. A decoder receives an error correcting code (ECC) for data resulting from execution of a shadow instruction of the original instruction, and data error correction is initiated on the original instruction result on condition of a mismatch between the parity bit and the original instruction result, and the decoder asserting a correctable error in the original instruction result.
    Type: Grant
    Filed: May 5, 2022
    Date of Patent: September 24, 2024
    Assignee: NVIDIA CORP.
    Inventors: Michael Sullivan, Siva Kumar Sastry Hari, Brian Matthew Zimmer, Timothy Tsai, Stephen W. Keckler
  • Patent number: 12093549
    Abstract: Disclosed are a method for managing data and a storage device thereof. The storage device includes at least one memory including a plurality of planes, each plane includes a plurality of blocks, and peer blocks in different planes are belonged to operate in a multi-plane mode. The plurality of blocks are detected to find a unavailable block. Then, available blocks corresponding to the unavailable block in planes other than the plane where the unavailable block is located are marked as backup blocks that do not operate in the multi-plane mode. A first block with effective data is selected from the plurality of blocks operating in the multi-plane mode. Data of the first block is moved to a backup block in the same plane.
    Type: Grant
    Filed: October 7, 2022
    Date of Patent: September 17, 2024
    Assignee: RayMX Microelectronics, Corp.
    Inventors: Hui Wang, Chun Yan Tang, Lin Su
  • Patent number: 12079078
    Abstract: Implementations described herein relate to command address fault detection. A memory device may receive, from a host device via a command address (CA) bus, a plurality of CA bits associated with a command signal or an address signal. The memory device may receive, from the host device via the CA bus, a first set of parity bits that is based on the plurality of CA bits and a select parity generation process. The memory device may generate a second set of parity bits, based on the plurality of CA bits, using the select parity generation process. The memory device may compare the first set of parity bits and the second set of parity bits. The memory device may selectively transmit an alert signal to the host device based on comparing the first set of parity bits and the second set of parity bits.
    Type: Grant
    Filed: August 16, 2022
    Date of Patent: September 3, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Melissa I. Uribe, Steffen Buch