Abstract: Disclosed herein are techniques to provide forward error correction for a high-speed interconnect symbol stream, such as, DisplayPort. The symbol stream may be split into FEC blocks and parity bits generated for each of the FEC blocks. The parity bits may be interleaved, encoded, and transmitted over an interconnect along with the symbol stream to provide forward error correction for the symbol stream.

Abstract: A memory system includes a nonvolatile semiconductor memory and a controller. The controller is configured to maintain a plurality of log likelihood ratio (LLR) tables for predicting a value of data read from the nonvolatile semiconductor memory, count a number of times that each of write operations, erase operations, and read operations have been carried out with respect to each unit storage region of the nonvolatile semiconductor memory, determine an order in which the LLR tables are referred to, based on the counted number of the read operations and one of the counted number of the write operations and the counted number of the erase operations, which correspond to a target unit storage region of a read operation, and carry out decoding of data read from the target unit storage region of the read operation, using one of the LLR tables selected according to the determined order.

Abstract: According to one embodiment, a memory controller includes an encoder, a randomizing circuit, and an interface. The encoder subjects first data received from an external device to error correction coding. The randomizing circuit randomizes second data output from the encoder. The interface transmits third data output from the randomizing circuit to a nonvolatile semiconductor memory and controls write/read of the nonvolatile semiconductor memory. The interface transmits data of a size larger than or equal to a size of a write unit of the nonvolatile semiconductor memory to the nonvolatile semiconductor memory in a write sequence.

Abstract: A semiconductor device in which unwanted change in the secondary data which must be reliable is suppressed and the need for a considerable increase in the capacity of a memory unit can be avoided. Also it ensures efficient data processing by asymmetric access to the memory unit. It includes a memory unit having a first memory without an error correcting function, a second memory with an error correcting function, and a plurality of access nodes for the memories. A plurality of buses is coupled to the access nodes and a plurality of data processing modules can asymmetrically access the memory unit through the buses. The first memory stores primary data before data processing by the data processing modules, and the second memory stores secondary data after data processing by the data processing modules.

Abstract: A method is provided that includes performing first decoding operations on data obtained from a plurality of units of memory using soft information values for the plurality of units of memory, where the plurality of units of memory includes an error correction stripe. The method further includes determining that two or more units of memory have uncorrectable errors. The method further includes updating a soft information value for a first unit of memory in accordance with a magnitude of a soft information value for a second unit and a direction based on parity of the error correction stripe excluding the first unit, where the first unit of memory and the second unit of memory are included in the two or more units of memory that have uncorrectable errors. The method further includes performing a second decoding operation on data obtained from the first unit using the updated soft information value.

Abstract: A semiconductor device correcting data errors using a hamming code is provided. The hamming code is realized by an error check matrix, and the error check matrix includes a first sub-matrix and a second sub-matrix. The first sub-matrix includes column vectors having an odd weight. The second sub-matrix includes an up matrix and a down matrix. Each of the up matrix and the down matrix includes column vectors having an odd weight.

Abstract: A parity check circuit may include a first signal combination unit for generating first to Nth combination signals by combining first to Nth signals, wherein a Kth (K is a natural number of 2?K?N) combination signal of the first to Nth combination signals is obtained by combining the first to Kth signals of the first to Nth signals, a parity check unit for detecting whether an error is present in the first to Nth signals in response to the Nth combination signal, a second signal combination unit for generating first to Nth reconstruction signals by combining the first to Nth combination signals, wherein a Kth reconstruction signal of the first to Nth reconstruction signals is obtained by combining a (K?1)th combination signal and the Kth combination signal of the first to Nth combination signals, and a signal storage unit for storing the first to Nth reconstruction signals.

Abstract: A parity check circuit may include a first signal combination unit for generating first to Nth combination signals by combining first to Nth signals, wherein a Kth (K is a natural number of 2?K?N) combination signal of the first to Nth combination signals is obtained by combining the first to Kth signals of the first to Nth signals, a parity check unit for detecting whether an error is present in the first to Nth signals in response to the Nth combination signal, a second signal combination unit for generating first to Nth reconstruction signals by combining the first to Nth combination signals, wherein a Kth reconstruction signal of the first to Nth reconstruction signals is obtained by combining a (K?1)th combination signal and the Kth combination signal of the first to Nth combination signals, and a signal storage unit for storing the first to Nth reconstruction signals.

Abstract: A method and apparatus is disclosed herein for low delay access to key-value based storage systems. In one embodiment, the method for putting data into a key-value store comprising dividing the data into K portions, where K is an integer; selecting an erasure coding to apply to the K portions as a function of delay performance of the key-value based storage system including determining a number of parity blocks to generate to satisfy one or both of a delay target of putting the object into the key-value store and a delay target of subsequent read requests based on an offline performance simulation of delay performance when different numbers of parity blocks are used given the delay distributions obtained through measurements for different request types and object sizes; applying the erasure coding to the K portions to create N blocks of data; sending the N write requests to write blocks of data to the storage system, where each block is assigned a unique key in the key-value store.

Abstract: Embodiments of the present invention relate to an apparatus, method, and/or sequence for a distributed ECC that may be used in a storage system. In another embodiment of the invention, an apparatus for handling distributed error correction code (ECC) operations, includes: a plurality of ECC engines configured to perform ECC operations in parallel on multiple data parts; the plurality of ECC engines distributed in parallel to receive some of the multiple data parts that are read from storage media devices and to receive some of the other multiple data parts that are to be written to the storage media devices; and the plurality of ECC engines configured to use respective ECC bytes corresponding to respective ones of the multiple data parts.

Abstract: A low-density parity check (LDPC) decoder is provided for decoding low-density parity check (LDPC) encoded data wherein the processing order of the layers of the LDPC parity check matrix are rearranged during the decode process in an attempt to avoid error mechanisms brought about by the iterative nature of the LDPC belief propagation decoding process, such as stopping sets and trapping sets.

Abstract: A semiconductor memory chip including error correction circuitry configured to receive data words from an external device, each data word comprising a binary number of data bits, and configured to error encode each data word to form a corresponding coded word comprising a non-binary number of data bits including the data bits of the data word and a plurality of error correction code bits. At least one memory cell array is configured to receive and store the coded word and partitioned based on the non-binary number of bits of the coded word so as to have a non-binary number of wordlines and provide the memory chip with an aspect ratio other than a 2:1 aspect ratio.

Abstract: A communications system includes a source, a destination, and multiple relays. In a first time period, the source emits a first transmission and a first relay retransmits a prior source transmission. Then, in a second, subsequent time period, the source node emits a second transmission and a second relay transmits the source transmission from the first time period. Optionally, the transmission from the second relay also includes the message from the first relay during the first time period. Similarly, in a third time period, the first relay transmits a message that includes the second relay's transmission and the second source transmission from the second time period. Alternatively, the source node transmit in a first frequency band, the first and second relays receive only in the first frequency band, and retransmit in a second frequency band, and the destination receives in both the first and second frequency bands.

Abstract: An error correction code (ECC) decoder processing data read from a storage media includes a plurality of processing elements for detecting an error in at least one of a plurality of channel data, wherein the plurality of channel data is received via a plurality of channels, and wherein the plurality of processing elements are driven independently from the plurality of channels.

Abstract: In one aspect, a memory device includes a memory cell array, parallel internal data paths which transmit internal data to and from the memory cell array, a data driver which transmits and receives external data, and a data buffer which delays and transfers the external data received by the data driver to the internal data paths, and which delays and transfers the internal data transmitted from the memory cell array to the data driver. The memory device further includes an error correction code generator which generates an error correction code (EC) based on the internal data transmitted on the internal data paths, an EC buffer which delays the error correction code generated by the error correction code generator, an EC driver which transmits the error correction codes delayed by the EC buffer, and a latency controller which variably controls a delay time of at least one of the data buffer and the EC buffer.

Abstract: According to one embodiment, there is provided a magnetic recording apparatus configured to record data subjected to error correcting coding according to a shingled recording scheme, the magnetic recording apparatus including a magnetic recording medium in which unit bits of the data subjected to error correcting coding are recorded with phase shifted between adjacent tracks, a read head having a width covering a plurality of tracks and configured to read data from the plurality of tracks, and a recording controller configured to record the data subjected to error correcting coding and a parity for the data in the plurality of tracks covered by the read head, in a divided manner.

Abstract: A flexible and relatively hardware efficient LDPC encoder is described. The encoder can be implemented with a level of parallelism which is less than the full parallelism of the code structure used to control the encoding process. Each command of a relatively simple microcode used to describe the code structure can be stored and executed multiple times to complete the encoding of a codeword. Different codeword lengths can be supported using the same set of microcode instructions but with the code being implemented a different number of times depending on the lifting factor selected to be used. The LDPC encoder can switch between encoding codewords of different lengths, without the need to change the stored code description information, by simply changing a code lifting factor used to control the encoding processes. When coding codewords shorter than the maximum supported codeword length some block storage locations and/or registers may go unused.

Abstract: A method is described for packing variable-length entropy coded data into a fixed rate data stream along with resolution enhancement data, the method providing tightly constrained propagation of transmission channel errors and graceful degradation of signal resolution as entropy-coded data rate increases. An application to a multiband ADPCM audio codec is also described.

Abstract: A semiconductor memory chip including error correction circuitry configured to receive data words from an external device, each data word comprising a binary number of data bits, and configured to error encode each data word to form a corresponding coded word comprising a non-binary number of data bits including the data bits of the data word and a plurality of error correction code bits. At least one memory cell array is configured to receive and store the coded word and partitioned based on the non-binary number of bits of the coded word so as to have a non-binary number of wordlines and provide the memory chip with an aspect ratio other than a 2:1 aspect ratio.

Abstract: According to an embodiment, a programmable logic device includes a plurality of logic blocks, memory and a logic unit. The logic blocks are grouped into one or more partitions. The memory stores authentication and partition information uploaded to the programmable logic device prior to partition programming. The logic unit authenticates programming access to the one or more partitions based on the authentication information and controls programming of the one or more partitions based on the partition information.

Abstract: Erasure-encoded data is stored across a plurality of storage devices in a data storage system. The erasure-encoded data includes k data elements to store on k data storage devices and m parity elements to store on m parity storage devices, wherein for a given minimum Hamming distance d of the data storage system and m?(d?1), data elements are assigned only to corresponding unique combinations of parity elements of size (d?1).

Abstract: A detection apparatus detecting an error component contained in two signals (A, B) approximated by a cosine and sine functions representing an object position, the detection apparatus including an arithmetic portion (3, 4) which reduces an error contained in the signals (A, B) based on an error prediction value to output two error correction signals (A*, B*), a phase arithmetic portion (5) which calculates a phase (?) based on the error correction signals (A*, B*), an arithmetic storage unit (9, 10) which stores the error correction signals (A*, B*) and a plurality of sampling values of the phase (?), and a Fourier transform portion (11, 12) which obtains coefficients ?k, ?k, ?k, and ?k in the following two expressions: A*=?0+?1 cos ?+?1 sin ?+ . . . +?k cos k?+?k sin k? B*=?0+?1 cos ?+?1 sin ?+ . . . +?k cos k?+?k sin k? (k?2) wherein the arithmetic portion (3, 4) updates the error prediction value using the coefficients.

Abstract: A method comprises receiving a sequence of unique memory addresses associated with concatenated, convolutionally encoded data elements. The method also comprises identifying each of the unique memory addresses as being included in one group of a plurality of address groups. Each address group substantially includes an equivalent number of unique addresses. The method also comprises, in parallel, accessing at least one memory address associated with each group of the plurality of address groups to operate upon the respective concatenated, convolutionally encoded data elements associated with each of the unique memory addresses being accessed.

Abstract: A method and apparatus to achieve a resource optimized, class of Reed Solomon decoders, featuring balanced pipelined stages and parallel algorithmic components. The Reed Solomon decoder has two pipeline stages, with one stage implementing syndrome computation and the second stage implementing error locator polynomial evaluation, error location and error correction. Since the second pipeline stage performs several tasks, these tasks can share resources with each other, resulting in a compact implementation. In addition, we present a technique that can be used to compute the level of parallelism required of two key algorithmic components (syndrome computation, error location) so that the RS decoder can handle inputs of variable rates, with minimal latency and resource consumption. We show that low latency, in itself, is an important consideration for Reed Solomon decoders, and can lead to reduced buffering, resulting in significant hardware savings.

Abstract: A method is described for packing variable-length entropy coded data into a fixed rate data stream along with resolution enhancement data, the method providing tightly constrained propagation of transmission channel errors and graceful degradation of signal resolution as entropy-coded data rate increases. An application to a multiband ADPCM audio codec is also described.

Abstract: A semiconductor integrated circuit device includes a first memory cell coupled to a first WL and one of a pair of BLs for information bits, a second memory cell coupled to the first WL and one of a pair of BLs for parity bits, a third memory cell coupled to a second WL and the other of the pair of BLs for information bits, a fourth memory cell coupled to the second WL and the other of the pair of BLs for parity bits, column switches which connect the pair of complementary BLs for parity bits to a pair of data lines for parity bits, and a logic correction circuit connected to one of the pair of data lines for parity bits. The logic correction circuit executes a parity bit rewrite operation.

Abstract: A system and method for communicating information in a wireless cooperative relay network of nodes, the nodes including a source, a set of relays, and a destination. The source broadcasts a code word encoded as a data stream using a rateless code. The relays receive the data stream, decode the data stream to recover the code word, and reencode and transmit the recovered code word as the data stream with the rateless code. The destination receives and decodes the reencoded data streams to recover the code word.

Abstract: A method for automatically calibrating intra-cycle timing relationships between command signals, data signals, and sampling signals for an integrated circuit device. The method includes generating command signals for accessing an integrated circuit component, accessing data signals for conveying data for the integrated circuit component, and accessing sampling signals for controlling the sampling of the data signals. A phase relationship between the command signals, the data signals, and the sampling signals is automatically adjusted to calibrate operation of the integrated circuit device.

Abstract: A method for error detection and correction (EDC) includes: generating a complete EDC code in response to a data packet; distributing the complete EDC code among the data packet to create a plurality of bytes, each including a data portion from the data packet and an EDC code portion from the complete EDC code; storing the bytes in a memory module; retrieving the bytes from the memory module; forwarding the data portions of the bytes retrieved from the memory module to a requesting device; providing the data portions of the bytes retrieved from the memory module to an EDC functional block; providing the EDC code portions of the bytes retrieved from the memory module to the EDC functional block; and performing error checking and correction in the EDC functional block upon receiving the complete EDC code from the provided EDC code portions.

Abstract: Error correction and error detection related to DRAM chip failures, particularly adapted server memory subsystems. It uses ×4 bit DRAM devices organized in a code word of 128 data bit words and 16 check bits. These 16 check bits are generated in such a way as to provide a code capable of 4 bit adjacent error correction within a family (i.e., in a ×4 DRAM) and double bit non-adjacent error detection across the entire 128 bit word, with single bit correction across the word as well. Each device can be thought of as a separate family of bits, errors occurring in more than one family are not correctable, but may be detected if only one bit in each of two families is in error. Syndrome generation and regeneration are used together with a specific large code word. Decoding the syndrome and checking it against the regenerated syndrome yield data sufficient for providing the features described.

Abstract: A system for computing a CRC value includes at least one memory for storing a data message, a current CRC value, and a plurality of lookup tables. The data message includes a plurality of words, with each word including a plurality of bytes. Each of the lookup tables stores a plurality of multi-byte CRC values. The system includes a processor for processing the message a word at a time. The processor is configured to update the current CRC value during processing each word based on an XOR of the word and the current CRC value, and based on a multi-byte CRC value retrieved from each one of the lookup tables.

Abstract: When the miniaturization of a DRAM advances, the capacity of a cell capacitor decreases, and further the voltage of a data line is lowered, the amount of read signals remarkably lowers, errors are produced during readout, and the yield of chips lowers. To solve the above problems, the present invention provides a DRAM that: has an error correcting code circuit for each sub-array; detects and corrects errors with said error correcting code circuit in both the reading and writing operations; and further has rescue circuits in addition to said error correcting code circuits and replaces a defective cell caused by hard error with a redundant bit.

Abstract: A client signal having a constant bit rate is segmented every a bytes to create code information blocks. The bit rate of the client signal is increased such that the client signal has the code information block and an empty area comprised of b bytes, and the ratio c/a is equal to or higher than 110% to create a code block 3 comprised of c bytes. The code information block in the code block is encoded such that an error correcting code is included therein to have an encoding gain of 6 dB or higher for a bit error ratio of 10?12. Associated check bits are placed in the empty area to eventually generate a super FEC signal.

Abstract: A parallel precoder circuit executes a differential encoding operation on an n-row parallel input information series, and outputs an n-row parallel output information series, where 2?n. Output sets of differential encoding operation circuits each of which having a largest column number from among differential encoding operation circuits disposed in first row to (n?1)th row become first-row to (n?1)th-row parallel outputs information series, and an output set of an nth-row delay circuit becomes nth-row parallel output information series.

Abstract: A parallel precoder circuit executes an EXOR operation on an n-row parallel input, and outputs an n-row parallel output, where 2?n. Outputs of EXOR circuits each of which having a largest column number from among EXOR circuits disposed in first to (n?1)th rows become first-row to (n?1)th-row parallel outputs, respectively. A output of an nth-row delay circuit becomes an nth-row parallel output.

Abstract: A semiconductor integrated circuit device includes a first memory cell coupled to a first WL and one of a pair of BLs for information bits, a second memory cell coupled to the first WL and one of a pair of BLs for parity bits, a third memory cell coupled to a second WL and the other of the pair of BLs for information bits, a fourth memory cell coupled to the second WL and the other of the pair of BLs for parity bits, column switches which connect the pair of complementary BLs for parity bits to a pair of data lines for parity bits, and a logic correction circuit connected to one of the pair of data lines for parity bits. The logic correction circuit executes a parity bit rewrite operation.

Abstract: A routing multiplexer system provide p outputs based on a selected permutation of p inputs. Each of a plurality of modules has two inputs, two outputs and a control input and is arranged to supply signals at the two inputs to the two outputs in a direct or transposed order based on a value of a bit at the control input. A first p/2 group of the modules are coupled to the n inputs and a second p/2 group of the modules provide the n outputs. A plurality of control bit tables each contains a plurality of bits in an arrangement based on a respective permutation. The memory is responsive to a selected permutation to supply bits to the respective modules based on respective bit values of a respective control bit table, thereby establishing a selected and programmable permutation of the inputs to the outputs.

Abstract: A method for parallelly processing data and ECC in the memory and associated apparatus are disclosed. The method includes the following steps: (1) reading the first data, and calculating the first syndrome based on the first data and the first ECC code, (2) correcting the first data according to the first syndrome, while reading the second data, and calculating the second syndrome based on the second data and the second ECC code, (3) and correcting the second data according to the second syndrome, while reading the third data and calculating the third syndrome based on the third data and the third ECC code.

Abstract: A memory subsystem comprising: a command register in operable communication with a plurality of memory devices via a plurality of command buses. The plurality of memory devices is arranged into symbol slices and each symbol slice is configured to be part of a single error correction code packet. Each command bus of the plurality of command buses is configured to interface between the command register and each memory device in a particular symbol slice. A method of command bus redundancy comprising: configuring a plurality of memory devices into symbol slices, each symbol slice configured to be part of a single error correction code packet; establishing a plurality of command buses, each command bus configured to interface with each memory device in a particular symbol slice; and configuring a command register with sufficient command bus drivers to support each command bus of the plurality of command buses.

Abstract: A codeword for use in error correction of digital optical media, the codeword having a plurality of data symbols and a plurality of parity symbols, and includes an augmented channel word which can be read as either a first value or a second alternate value. The augmented channel word is one of the plurality of data and parity symbols, wherein the augmented channel word retains its value irrespective of any error correction performed.

Abstract: A serial communication device bridging between a parallel bus and a serial bus, includes (a) a check bit producer which applies an error correcting code to parallel data transmitted through the parallel bus, (b) a parallel-serial converter which converts the parallel data output from the check bit producer, into serial data, (c) a serial-parallel converter which converts serial data transmitted through the serial bus, into parallel data, and (d) an error detector which checks an error correcting code applied to the serial data, and detects an error in the error correcting code.

Abstract: A decoding method and an apparatus operate by performing error correction on code words of an error correcting code block in one direction selected from a row direction and a column direction, indicating in error flags the remaining code words except at least some code words from code words having uncorrectable errors, and performing error correction on code words in the other direction based on the error flags. Accordingly, errors that have been conventionally considered as being uncorrectable may now be corrected.

Abstract: An ECC circuit (103) is located between I/O terminals (1040–1047) and page buffers (1020–1027). The ECC circuit (103) includes a coder configured to generate check bits (ECC) for error correcting and attach the check bits to data to be written into a plurality of memory cell areas (1010–1017), and a decoder configured to employ the generated check bits (ECC) for error correcting the data read out from the memory cell areas (1010–1017). The ECC circuit (103) allocates a set of 40 check bits (ECC) to an information bit length of 4224=(528×8) bits to execute coding and decoding by parallel processing 8-bit data, where data of 528 bits is defined as a unit to be written into and read out from one memory cell area (101j).

Abstract: Systems and methods are provided for detecting and correcting bit errors in data structures. A data block and/or data structure is partitioned into adjacent bit pair domains, such that a single adjacent bit pair from each memory device is assigned to a given adjacent bit pair domain. The adjacent bit pair domain data is transmitted over a bus having a plurality of data paths, such that data bits associated with a given memory device are transmitted over a same data path.

Abstract: A client signal having a constant bit rate is segmented every a bytes to create code information blocks. The bit rate of the client signal is increased such that the client signal has the code information block and an empty area comprised of b bytes, and the ratio c/a is equal to or higher than 110% to create a code block 3 comprised of c bytes. The code information block in the code block is encoded such that an error correcting code is included therein to have an encoding gain of 6 dB or higher for a bit error ratio of 10?12. Associated check bits are placed in the empty area to eventually generate a super FEC signal.

Abstract: For reducing time required for error correction in an error correction device, data are transferred from a buffer memory not only to a syndrome calculator but also to an error detector at the same time, and until the syndrome calculator detects an error-containing code, the error detector performs error detection in parallel with the syndrome calculation done by the syndrome calculator. During error detection after the error corrector corrects the error, mid-term results of the error detection obtained before an error-containing code is detected are used. Consequently, it becomes unnecessary to transfer all data from the buffer memory to the error detector, thereby making execution of an error detection process possible at a halfway point.

Abstract: A method and apparatus for reducing the information error rate of a communication network. The apparatus comprises a selector device coupled to a Framer and to an Interleaver. The selector device is configured to receive system information and the Framer is configured to receive user information. The apparatus is coupled to equipment which operate the communication network based on system parameters. The apparatus and method of the present invention improve the coding and effectively increase the interleaving depth applied to user information thus reducing the information error rate of the communication network without having to alter or modify any of the system parameters.

Abstract: A codeword and a method for generating a codeword is provided. The codeword may be used in error correction of digital optical media and DVDs, the codeword having a plurality of data symbols and a plurality of parity symbols, and includes an augmented channel word which can be read as either a first value or a second alternate value. The augmented channel word is one of the plurality of data and parity symbols, the augmented channel word retaining its value irrespective of any error correction performed.

Abstract: A method for combining a refresh operation with a parity validation for a DRAM-based content addressable memory (CAM) is disclosed. In an exemplary embodiment of the invention, the method includes implementing the memory refresh operation and examining a word included within the CAM. A determination is made as to whether data contained within the word constitutes valid data. If the data contained within the word does not constitute valid data, then the parity validation is bypassed. However, if the data contained within the word does constitute valid data, then the parity validation is implemented. The parity validation further includes reading the data contained within the word, generating a parity bit from the data contained within the word, and comparing the generated parity bit with a previously stored parity bit. If the parity validation is implemented and if the generated parity bit does not match the previously stored parity bit, then the data contained within the word is invalidated.

Abstract: A storage device, including: a non-volatile semiconductor memory which is electrically erasable; a system interface coupled with an external host system; and a controller reading data from the non-volatile semiconductor memory and transmitting data to the host system via the system interface in response to a read command received by the system interface from the host system; and wherein the controller starts reading (N+n)th sector data from the non-volatile semiconductor memory, while the controller transmits Nth sector data that has been read from the non-volatile semiconductor memory to the host system via the system interface, in response to the read command for successive sector data.