Abstract: Message faults are caused by network crowding and signal fading at high frequencies of 5G and 6G. Current error-detection and correction algorithms are computationally demanding, especially for new low-cost reduced-capability IoT devices. Disclosed are methods for (a) determining whether a message is faulted using a compact error-detection code, (b) localizing the most likely faulted message element(s) according to the waveform signal, and (c) determining the likely corrected version by back-calculating from the error-detection code. Other versions include testing various modulation substitutions for the most suspicious message elements, having the worst signal quality. The waveform parameters may include a deviation from an average amplitude, phase, frequency, or polarization, as well as an amount of amplitude variation and phase variation within the message element. Identification of the most likely faulted message elements may enable recovery of the message without a costly retransmission.

Abstract: A data processing device includes an average correction processor that corrects input data based on an average value of the input data and outputs average correction data, and reversibly encodes and decodes the average value to generate a decoded average value, an irreversible encoder/decoder that encodes and decodes the average correction data and outputs first and second decoded data, a binary predictor that predicts a magnitude of a restoration error included in the second decoded data based on the first decoded data and the decoded average value and outputs a prediction result as binary data, an error estimator that outputs an estimation error based on the first decoded data, the second decoded data, and the decoded average value, and an operation circuit that outputs output data based on the second decoded data, the binary data, the estimation error, and the decoded average value.

Abstract: A semiconductor memory device includes a memory cell array, a link error correction code (ECC) engine and on-die ECC engine. The memory cell array includes a plurality of volatile memory cells. The link ECC engine provides a main data by performing a first ECC decoding on a first codeword including the main data and a first parity data, and generates a first error flag based on a result of the first ECC decoding. The on-die ECC engine generates a second parity data by performing a first ECC encoding on the main data, provides a target page of the memory cell array with a second codeword including the main data and the second parity data in response to the first error flag being deactivated or generates a third codeword by changing at least one of bits of the second codeword in response to the first error flag being deactivated.

Abstract: Systems, methods and apparatus to determine, in response to a command to write data into a set of memory cells, a programming mode of a set of memory cell to optimize performance in retrieving the data back from the set of memory cells. For example, based on usages of a memory region containing the memory cell set, a predictive model can be used to identify a combination of an amount of redundant information to be stored into the memory cells in the set and a programming mode of the memory cells to store the redundant information. Increasing the amount of redundant information can increase error recovery capability but increase bit error rate and/or increase time to read. The predictive model is trained to predict the combination to optimize read performance.

Abstract: Embodiments are generally directed to message authentication code (MAC) based compression and decompression. An embodiment of an apparatus includes one or processors to process data; and a computer memory; wherein the one or more processors are to perform compression of a fixed transmission or storage unit, the transmission or storage unit including multiple slots, the compression of the transmission or storage unit including the one or more processors to calculate a MAC for data in the transmission or storage unit, determine whether a special value is present in any slot of the transmission or storage unit, and upon determining that the special value is present in a respective slot of the transmission or storage unit, remove the special value from the transmission or storage unit, shift remaining data of the transmission or storage unit to provide room in a first slot the transmission or storage unit, and insert the MAC in the first slot to generate a compressed transmission or storage unit.

Abstract: Described herein are systems, methods, and other techniques for compatible packet separation for communication networks. A block comprising a plurality of packets to be transmitted over a network is received. The block includes a set of batches, and the plurality of packets are distributed between the set of batches. A pseudo interleaver depth is calculated for each of the set of batches to produce a set of pseudo interleaver depths. Blockwise adaptive recoding is performed using the set of pseudo interleaver depths to produce a number of recoded packets for each of the set of batches. A transmission sequence is generated using the number of recoded packets for each of the set of batches.

Abstract: A system and method for polar code coding with information bits placed in particular bit indexes are disclosed herein. In one embodiment, a method for channel coding includes: associating, by a polar code encoder, a first bit sequence with first bit indexes of a polar code input; associating, by the polar code encoder, a second bit sequence with second bit indexes, wherein the first bit indexes have a higher reliability than the second bit indexes; and encoding, by the polar code encoder, both the first bit sequence and the second bit sequence using a generator matrix to generate encoded bits.

Abstract: Techniques are provided for automated adaptive endurance tuning of solid-state storage media. For example, a storage control system tracks usage metrics associated with utilization of solid-state storage devices of a storage system, wherein the storage system comprises an amount of over-provisioned capacity allocated in the solid-state storage devices according to an over-provisioning factor. The storage control system determines a current endurance value of the data storage system based at least in part on the usage metrics, and compares the current endurance value to a target endurance value to determine if the current endurance value differs from the target endurance value.

Abstract: An apparatus (100) for providing an joint error correction code (140) for a combined data frame (254) comprising first data (112) of a first data channel and second data (122) of a second data channel comprises a first error code generator (110) configured to provide, based on a linear code, information on a first error correction code (114a, 114b) using the first data (112). The apparatus further comprises a second error code generator (120) configured to provide, based on the linear code, information on a second error correction code (124) using the second data (122). The apparatus is configured to provide the joint error correction code (140) using the information on the first error correction code (114a, 114b) and the information on the second error correction code (124).

Abstract: A decoding device that includes a decoding determination unit to determine a procedure of recovering and decoding missing packets in consideration of a packet missing pattern in data including a set of media packets and redundant packets generated by a two-dimensional XOR-based FEC encoding method. Further, a decoding unit executes the recovery of the missing packets according to the procedure determined by the decoding determination unit.

Abstract: A system is provided to receive, by a controller, a first request to read a first page of data stored in a storage device which comprises a plurality of non-volatile memory units. The system accumulates, by a calculation module, a syndrome associated with the first page of data to obtain a syndrome weight. In response to determining that the syndrome weight is less than a predetermined threshold, the system writes, by the controller, the first page of data to a destination page of the storage device. In response to determining that the syndrome weight is greater than the predetermined threshold and that a current number of retries is less than a predetermined number: the system executes a retry process between the calculation module and a data flip engine of the controller to update the syndrome weight; and the system increments the current number of retries.

Abstract: Embodiment techniques map parity bits to sub-channels based on their row weights. In one example, an embodiment technique includes allocating, from a set of sub-channels, one or more sub-channels for one or more parity bits based on row weights for sub-channels in a subset of sub-channels within the set of sub-channels, mapping information bits to remaining sub-channels in the set of sub-channels based on a reliability of the remaining sub-channels without mapping any of the information bits to the one or more sub-channels allocated for the one or more parity bits, polar encoding the information bits and the one or more parity bits based on at least the mapping of the information bits to the remaining sub-channels to obtain encoded bits, and transmitting the encoded bits to another device.

Abstract: The present disclosure relates to a system and a method for data protection. In some embodiments, an exemplary method for data encoding includes: receiving a data bulk; performing an erasure coding (EC) encoding on the data bulk to generate one or more EC codewords; distributing a plurality of portions of each EC codeword of the one or more EC codewords across a plurality of solid-state drives (SSDs); performing, at each SSD of the plurality of SSDs, an error correction coding (ECC) encoding on portions of the one or more EC codewords distributed to the SSD to generate an ECC codeword; and storing, in each SSD of the plurality of SSDs, the ECC codeword.

Abstract: A wireless device generates a High Efficiency Signal B (HE-SIG-B) field by Block Convolution Code (BCC) encoding and rate-matching a BCC block of the HE-SIG-B field, generates a Physical Layer Protocol Data Unit (PPDU) including the HE-SIG-B field, and transmits the PPDU. A total number N is a total number of bits of the HE-SIG-B field that precede the BCC block, and is greater than 0. The BCC block has a puncturing pattern depending on the total number N. A wireless device receives a PPDU. The PPDU includes an HE-SIG-B field that includes an encoded BCC block. The wireless device de-rate-matches the encoded BCC block having a puncturing pattern depending on a total number N. The total number N is a total number of decoded bits of the HE-SIG-B field that preceded the BCC block, and the total number N is greater than 0.

Abstract: A programming and verifying method for a multi-level memory cell array includes following steps. In a step (a1), a first row of the multi-level memory cell array is set as a selected row, and A is set as 1. In a step (a2), memory cells in the selected row excluding the memory cells in the target storage state and bad memory cells are programmed to the A-th storage state. In a step (a3), if A is not equal to X, 1 is added to X and the step (a2) is performed again. In a step (a4), if A is equal to X, the program cycle is ended. In the step (a2), the first-portion memory cells of the selected row are subjected to plural write actions and plural verification actions until all of the first-portion memory cells reach the A-th storage state.

Abstract: Methods and apparatuses for implementing error-correction in communication systems, particularly wireless communication systems. Input bits are encoded according to a chained generator matrix to generate a codeword, and the codeword is transmitted. The chained generator matrix includes a first subset of entries corresponding to a first subset of entries in a base generator matrix for a chained polar code, and a second subset of entries that are different from a second subset of entries in the base generator matrix. A chained generator matrix could be constructed, for example, by applying a chaining matrix to the second subset of entries in the base generator matrix, to produce the second subset of entries in the chained generator matrix.

Abstract: Systems and methods disclosed herein provide an outer code for HARQ applications, which may be an erasure code. In some embodiments, the outer code has a relatively simple decoding algorithm, increased decoding probability with no extra redundancy packets needed and can correct an arbitrary number of code blocks. In some embodiments, the outer code may be implemented as part of the 5G air interface, also known as new radio (NR), and/or in applications such as vehicle-to-everything (V2X) and/or ultra-reliable low latency communication (URLLC). Some embodiments provide a nested HARQ protocol for HARQ transmission with an outer code.

Abstract: A polar coder circuit is described. The polar coder circuit comprises one or more datapaths; and at least one logical three-dimensional, 3D, memory block coupled to the one or more datapaths and comprising a number of one or more random access memories, RAMs, of the logical 3D memory block as a first dimension, wherein the one or more RAMs comprise(s) a width of one or more element(s) as a second dimension and a depth of one or more address(es) as a third dimension and wherein the first dimension or the second dimension has a size 2sd, where sd is a number of stages in a datapath of the one or more datapaths.

Abstract: In one embodiment, a method for managing overprovisioning in a solid state storage drive array comprises receiving usage data from each of a plurality of solid state storage drives, determining a predicted service life value for each of the plurality of solid state storage drives based on at least the usage data, comparing each of the predicted service life values with a predetermined service life value for each respective solid state storage drive, and dynamically adjusting an available logical storage capacity for at least one of the plurality of solid state storage drives based on a result of the step of comparing.

Abstract: The present application concerns an encoding device comprising a FC 11 configured to generate m FC-output-bit-sequences by executing m polar encoding steps upon m FC-input-bit-sequences that comprise frozen and unfrozen bits, wherein m?2. In an i-th polar encoding step of the m polar encoding steps at least one frozen bit is based on at least one unfrozen bit. The present application also concerns a decoding device comprising a processor configured to decode successively a polar-coded-bitstream comprising m-polar decoding steps, wherein m?2. In an i-th polar decoding step of the m polar decoding steps at least one frozen bit is based on at least one unfrozen bit. Further, the present application concerns also correspondingly arranged encoding and decoding methods.

Abstract: Systems and methods of communicating using asymmetric polar codes are provided which overcome the codeword length constraints of systems and methods of communicating that use traditional polar codes. Used herein, asymmetric polar codes refers to a polarizing linear block code of any arbitrary length that is constructed by connecting together constituent polar codes of unequal length. Asymmetric polar codes may be known by other names. In comparison to conventional solutions for variable codeword length, asymmetric polar codes may provide more flexibility, improved performance, and/or reduced complexity of decoding, encoding, or code design. The system and method provide a flexible, universal, and well-defined coding scheme and to provide sound bit-error correction performance and low decoding latency (compared with current length-compatible methods which can be used with current hardware designs).

Abstract: A memory controller is provided to include an error correction encoder and an error correction decoder. The error correction encoder is configured to encode a message at a second code rate and generate a codeword including a message part, a first parity part, and a second parity part. The error correction decoder is in communication with the error correction encoder and configured to perform at least one of i) first error correction decoding operation at a first code rate greater than the second code rate based on a first parity check matrix and first read values or ii) second error correction decoding operation at the second code rate based on a second parity check matrix and second read values. The first read values correspond to a partial codeword including the message part and the first parity part, and the second read values correspond to an entire codeword.

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a host device may access a group of memory cells (e.g., portion of an array configurable to store ECC parity bits) otherwise reserved for ECC functionality of a memory device. The memory device may include a register to indicate whether its ECC functionality is enabled or disabled. When the register indicates the ECC functionality is disabled, the memory device may increase a storage capacity available to the host device by making the group of memory cells available for user-accessible data. Additionally or alternatively, the memory device may store metadata associated with various operational aspects of the memory device in the group of memory cells. Moreover, the memory device may modify a burst length to accommodate additional information to be stored in or read from the group of memory cells.

Abstract: A data processing system and method are provided. A host computing device comprises at least one processor. A network interface device is arranged to couple the host computing device to a network. The network interface device comprises a buffer for receiving data for transmission from the host computing device. The processor is configured to execute instructions to transfer the data for transmission to the buffer. The data processing system further comprises an indicator store configured to store an indication that at least some of the data for transmission has been transferred to the buffer wherein the indication is associated with a descriptor pointing to the buffer.

Abstract: A base matrix is applied to an LDPC coder. The base matrix includes multiple parts, each including multiple of rows and columns, and containing integers, each representative of an identity matrix cyclically shifted in accordance with the integer or representative of an all-zero matrix. At least two of the multiple parts are configured such that their respective column-wise combinations of rows represents a same starting vector, cyclically shifted or interleaved, with zero or more but not all integers not indicative of the all-zero matrix of the same vector substituted by integers indicative of the all-zero matrix. The at least two of the multiple parts are not identical. The applied base matrix is used for one of encoding data using the LDPC coder or decoding data using the LDPC coder.

Abstract: Various examples are directed to systems and methods for reading a memory component. A processing device may receive an indication that a read operation at a physical address of the memory component failed. The processing device may execute a plurality of read retry operations at the physical address. The processing device may access a first syndrome weight describing a first error correction operation performed on a result of a first read retry operation of the plurality of read retry operations and a second syndrome weight describing a second error correction operation performed on a result of a second read retry operation of the plurality of read retry operations. The processing device may select a first threshold voltage associated with the first read retry operation based at least in part on the first syndrome weight and the second syndrome weight.

Abstract: A method and system for real-time monitoring of terminals in a satellite communication system is disclosed. The method includes creating a configuration profile specifying a reporting format for one or more object status, and transmitting the configuration profile to a terminal. The terminal subsequently generates a report containing the requested object status based on the configuration profile. The report is provided to a gateway responsible for managing the terminal using available space within existing traffic. The gateway subsequently forwards report to at least one destination entity.

Abstract: A plurality of error correction circuits corrects errors of the data transmitted through the plurality of transmission lines. A combining portion combines the plurality of transmission lines to the plurality of error correction circuits. The plurality of transmission lines includes a first transmission line, and a second transmission line having a lower transmission characteristic than the first transmission line. The plurality of error correction circuits includes a first and a second error correction circuit having lower error correction capability and power consumption than the first error correction circuit. The combining portion uses a function to combine a plurality of error correction circuits with one transmission path, combines the first transmission line with the second error correction circuit at a higher rate than the first error correction circuit, and combines the second transmission line with the first error correction circuit at a higher rate than the second error correction circuit.

Abstract: There is provided a method of obtaining one or more parity symbols (PS) of an encoding of information symbols (IS) according to a linear cyclic code, the method comprising: upon a permutation of information symbols (IS), generating data indicative of parity coefficients of a row of a generator matrix associated with the linear cyclic code, computing, for each given parity coefficient, a first data in accordance with, at least, the given parity coefficient and the first IS; updating, by the processing circuitry, for each given parity coefficient of the one or more parity coefficients, the first data, in accordance with, at least, the given parity coefficient and the respective IS; and upon meeting a parity completion criterion for a given parity coefficient, deriving a parity symbol from the respective first data, thereby obtaining the one or more parity symbols of the codeword of the linear cyclic code.

Abstract: A wireless device generates a High Efficiency Signal B (HE-SIG-B) field by Block Convolution Code (BCC) encoding and rate-matching a BCC block of the HE-SIG-B field, generates a Physical Layer Protocol Data Unit (PPDU) including the HE-SIG-B field, and transmits the PPDU. A total number N is a total number of bits of the HE-SIG-B field that precede the BCC block, and is greater than 0. The BCC block has a puncturing pattern depending on the total number N. A wireless device receives a PPDU. The PPDU includes an HE-SIG-B field that includes an encoded BCC block. The wireless device de-rate-matches the encoded BCC block having a puncturing pattern depending on a total number N. The total number N is a total number of decoded bits of the HE-SIG-B field that preceded the BCC block, and the total number N is greater than 0.

Abstract: A memory system, which is connectable to a host, includes a non-volatile memory and a controller configured to store data in the non-volatile memory and in a memory region within the host and read the data from the memory region within the host. The controller includes a first encoding/decoding circuit configured to execute encoding/decoding with a first encoding scheme, a second encoding/decoding circuit configured to execute encoding/decoding with a second encoding scheme having a higher error correcting capability than an error correcting capability of the first encoding scheme, an encoding scheme selecting circuit configured to select an encoding/decoding circuit from the first encoding/decoding circuit and the second encoding/decoding circuit to perform encoding of data to be stored in the memory region, based on information about the data read from the memory region.

Abstract: In embodiments, an apparatus may comprise random access memory (RAM); an error detecting and/or correcting code (EDCC) encoder to generate and add an error detecting and/or correcting code to a datum being written into the memory for storage; and an EDCC decoder to use the error detecting and/or correcting code added to the datum to correct one or more bits of error in the datum when the datum with the added error detecting and/or correcting code is read back from the RAM. Further, the apparatus may include an error detection and/or correction checker to inject one or more bits of error into the datum when the datum with the added error and/or correcting code is read back from the RAM, and check whether the EDCC decoder is able to correct the one or more bits of error injected into the datum.

Abstract: The application discloses video data redundancy control methods and apparatuses. Video packet redundancy control information is determined according to packet loss at a reception apparatus. The video packet redundancy control information is received from the reception apparatus. Video data is encoded according to the video packet redundancy control information to obtain encoded video data of a plurality of frames by a transmission apparatus. A frame-level redundancy budget is allocated for one of the plurality of frames according to the video packet redundancy control information. Further, the one of the plurality of frames is packetized according to the frame-level redundancy budget to generate a packetized frame. Redundancy coding is performed on the packetized frame to generate video packets including data packets and redundant packets for transmission to the reception apparatus.

Abstract: Systems and methods for providing forward error correction for a multi-channel audio signal are described. Blocks of an audio stream are buffered into a frame. A transformation can be applied that compacts the energy of each block into a plurality of transformed channels. The energy compaction transform may compact the most energy of a block into the first transformed channel and to compact decreasing amounts of energy into each subsequent transformed channel. The transformed frame may be encoded using any suitable codec and transmitted in a packet over a network. Improved forward error correction may be provided by attaching a low bit rate encoding of the first transformed channel to a subsequent packet. To reconstruct a lost packet, the low bit rate encoding of the first channel for the lost packet may be combined with a packet loss concealment version of the other channels, constructed from a previously-received packet.

Abstract: There is disclosed a method for operating a transmitting node (10, 100) for a wireless communication network, the transmitting node being adapted for transmitting data utilizing error detection coding, wherein the error detection coding has a coding length in bits, the method comprising adapting the coding length based on a retransmission status of the data. There are also disclosed a corresponding method for operating a receiving node and corresponding nodes and program products and storage media.

Abstract: A method and apparatus for code block division are provided. The method may include the following acts. A reference information block length of a code block is determined according to an obtained division related parameter. A maximum information block length is determined according to the reference information block length and a hardware parameter. A Transport Block (TB) having a length greater than the maximum information block length may be divided into two or more code blocks according to the obtained division related parameter, the hardware parameter and the determined maximum information block length. An information length after code block division is less than the determined maximum information block length.

Abstract: There is provided a transmitter including: a transmission unit configured to transmit a parity packet obtained by performing FEC encoding on a plurality of frames in image data for each of the plurality of frames; and a number-of-frames specifying unit configured to specify the number of frames of the plurality of frames to be subjected to the FEC encoding on the basis of a network transmission delay time.

Abstract: One embodiment provides a method comprising arranging a first data chunk into a ring structure, tagging the first data chunk by appending extra data to the first data chunk, and performing erasure coding on the first data chunk utilizing only exclusive or (XOR) operations.

Abstract: Various implementations described herein are directed to a method that identifies a memory instance with multiple tile-cells. The memory instance has memory instance leakage data, and each tile-cell of the multiple tile-cells has tile-cell leakage data. The method subdivides the multiple tile-cells into multiple categories based on a relationship between the memory instance leakage data and the tile-cell leakage data. The method obtains measured leakage data for each tile-cell of the multiple tile-cells by simulating the memory instance based on the memory instance leakage data and the tile-cell leakage data for each category of the multiple categories. The method determines a combined leakage of the memory instance by combining the measured leakage data for each tile-cell of the multiple tile-cells.

Abstract: A system and method that time delays a playback from a first feed at a first time to a second feed at a second time. The method includes recording the first feed that is received at the first time to be used at least partially as a playback of the second feed at the second time. The second time has a predetermined delay relative to the first time. The method includes determining whether the first feed has a discrepancy in the actual playback from a desired playback. The discrepancy is at a known time and lasting a known time amount. The method includes transmitting the playback to the second feed after the predetermined delay. A fix is aired instead of the playback for the known time amount corresponding to the discrepancy.

Abstract: Aspects of the invention include using a cyclic redundancy code (CRC) multiple-input signature register (MISR) for early warning and fail detection. Received bits are monitored at a receiver for transmission errors. The monitoring includes receiving frames of bits that are a subset of frames of bits used by the transmitter to generate a multi-frame CRC. At least one of the received frames of bits includes payload bits and a source single check bit not included in the multi-frame CRC. It is determined whether a transmission error has occurred in the received frames of bits. The determining includes generating a calculated single check bit based at least in part on bits in the received frames of bits, and comparing the received source single check bit to the calculated single check bit. An error indication is transmitted to the transmitter if they don't match.

Abstract: A 5th generation (5G) or pre-5G communication system for supporting a data transmission rate higher than that of a 4th generation (4G) communication system such as long term evolution (LTE) is disclosed. The present disclosure relates to a rate compatible low-density parity-check (RC-LDPC) encoding method and device therefor. The encoding method includes using LDPC in a communication system, including the operations of LDPC encoding information bits by a first encoding rate, and performing a concatenated single parity check (SPC) encoding for the encoded bits by at least one second encoding rate lower than the first encoding rate.

Abstract: A polar code generation method and device are disclosed. The method includes: determining an index set of information bits of a polar code according to a first modulation scheme; and encoding the polar code according to the index set of the information bits of the polar code.

Abstract: Embodiments of the present disclosure provide an FEC coding and decoding method and device, and a system. A transmit end determines a forward error correction FEC coding type according to a length of to-be-coded data in burst data, and performs coding according to the determined FEC coding type. A receive end determines a forward error correction FEC decoding type according to a length of to-be-decoded data in burst data, and performs decoding according to the determined FEC decoding type. The FEC coding and decoding method provided in the embodiments of the present disclosure improves utilization of a communication resource is improved, and saves a communication resource.

Abstract: In various implementations, a method includes determining a sequence of source packets. In some implementations, the sequence of source packets satisfies a windowing condition. In various implementations, the method includes synthesizing a first set of one or more parity packets as a function of a first set of source packets in the sequence. In some implementations, the first set of source packets satisfies a first encoding pattern. In various implementations, the method includes synthesizing a second set of parity packets as a function of a second set of source packets in the sequence. In some implementations, the second set of source packets satisfies a second encoding pattern that is different from the first encoding pattern. In some implementations, the first and second encoding patterns characterize an encoding structure determined as a function of a channel characterization vector.

Abstract: Systems and methods are disclosed herein relating to rate-compatible polar codes and the use thereof in a wireless communications system. In some embodiments, a transmit node operable for use in a wireless communications system comprises a rate-compatible polar encoder operable to encode information bits to provide coded bits utilizing parallel concatenated polar codes. The transmit node further comprises a transmitter operable to transmit the plurality of coded bits. In this manner, the transmit node may, in some embodiments, use polar codes having different coding rates to adapt to time-varying channel conditions.

Abstract: A transmitter, a receiver and a method for communicating data packets. The method comprises receiving a data packet and determining if it is a re- or new transmission; and, when it is a retransmission: combining the received data packet with oldest unsuccessfully decoded data packet stored in a second memory, and decoding the combined data packet; when it is a new transmission: decoding the received data packet; checking if the decoding is successful; deleting the oldest stored data packet in the first memory; storing the decoded data packet in the first memory when the decoding is successful or storing the decoded data packet in the second memory when the decoding is not successful; and transmitting feed-back information to the transmitter.

Abstract: There is provided a method of transporting error correction codes (ECCs) in a transmission stream, the method including encoding a data stream from a data source into data symbols, generating first ECCs from the data symbols, encoding the first ECCs into first error correction code (ECC) symbols, merging the data symbols and the first ECC symbols into the transmission stream, the first ECC symbols being merged before the data symbols into the transmission stream, and transmitting the merged transmission stream to a sink device via a communication link, the first ECC symbols being transmitted before the data symbols.

Abstract: A method for constructing a low-density parity-check (LDPC) code using a structured base parity check matrix with permutation matrix, pseudo-permutation matrix, or zero matrix as constituent sub-matrices; and expanding the structured base parity check matrix into an expanded parity check matrix. A method for constructing a LDPC code using a structured base parity check matrix H=[Hd|Hp], Hd is the data portion, and Hp is the parity portion of the parity check matrix; the parity portion of the structured base parity check matrix is such so that when expanded, an inverse of the parity portion of the expanded parity check matrix is sparse; and expanding the structured base parity check matrix into an expanded parity check matrix. A method for encoding variable sized data by using the expanded LDPC code; and applying shortening, puncturing.

Abstract: A method for constructing a low-density parity-check (LDPC) code using a structured base parity check matrix with permutation matrix, pseudo-permutation matrix, or zero matrix as constituent sub-matrices; and expanding the structured base parity check matrix into an expanded parity check matrix. A method for constructing a LDPC code using a structured base parity check matrix H=[Hd|Hp], Hd is the data portion, and Hp is the parity portion of the parity check matrix; the parity portion of the structured base parity check matrix is such so that when expanded, an inverse of the parity portion of the expanded parity check matrix is sparse; and expanding the structured base parity check matrix into an expanded parity check matrix. A method for encoding variable sized data by using the expanded LDPC code; and applying shortening, puncturing. System and method for operating a wireless device to encode data using low-density parity-check (LDPC) encoding is discussed.