Abstract: A DRAM memory device includes several banks of memory cells each of which are divided into first and second sets of memory cells. The memory cells in the first set can be refreshed at a relatively slow rate to reduce the power consumed by the DRAM device. Error checking and correcting circuitry in the DRAM device corrects any data retention errors in the first set of memory cells caused by the relatively slow refresh rate. The memory cells in the second set are refreshed at a normal rate, which is fast enough that data retention errors do not occur. A mode register in the DRAM device may be programmed to select the size of the second set of memory cells.

Abstract: Aspects of the disclosure can provide a method and an apparatus to decode a data stream based on multiple transmissions with efficient usages of storage and power resources. The method for decoding can include receiving a first plurality of encoded code blocks corresponding to a first transmission of a transport block, decoding the first plurality of encoded code blocks into decoded code blocks, error detecting the decoded code blocks, and storing a decoding history of the decoded code blocks. Further, the method can include receiving a second plurality of encoded code blocks corresponding to a retransmission of the transport block. The second plurality of encoded code blocks can map the first plurality of encoded code blocks, respectively. The method can selectively decode a subset of the second plurality of encoded code blocks based on the decoding history. In addition, the method can include storing soft bits for code blocks that failed decoding.

Abstract: A method and apparatus for turbo coding and decoding is provided herein. During operation, a concatenated transport block (CTB) of length X is received and a forward error correction (FEC) block size KI is determined from a group of available non-contiguous FEC block sizes between Kmin and Kmax, and wherein Kmin?KI<Kmax and wherein KI is additionally based on X. The concatenated transport block of length X is segmented into C segments each of size substantially equal KI. An FEC codeword for each of the C segments is determined using FEC block size KI; and the C FEC codewords are transmitted over the channel.

Abstract: A method and apparatus for transmitting control information in a wireless communication system using a Low Density Parity Check (LDPC) code is provided. The number of LDPC blocks, through which L1 post-signaling information is to be transmitted, is determined according to the total number of bits of the L1 post-signaling information. The number of input information bits of each LDPC block is calculated when the determined number of LDPC blocks is plural. The number of puncturing bits among parity bits of each LDPC block is determined considering a modulation order. A frame including one or multiple LDPC blocks generated through the preceding steps is transmitted.

Abstract: System and methods for storing data encoded with error information in a storage medium are provided. A binary data and an encoded binary error signals are received. The encoded binary error signal includes information that represents occurrence of errors in the binary data signal. The binary data and encoded binary error signals are encoded to generate a binary codeword signal. Bits of the binary codeword signal that represent coding information and the binary data signal are extracted. The extracted bits of the binary codeword signal are stored in a first storage medium. The binary packed data signal is retrieved from the first storage device and decoded to recover the binary data signal and a syndrome. Error information corresponding to the encoded binary error signal may be determined based on the syndrome.

Abstract: In one aspect, a communication system transmitter comprises an adaptive error correction encoder. The adaptive error correction encoder is configured to generate a plurality of error correction frames with each such error correction frame comprising a plurality of data packets and one or more error correction packets. A given one of the error correction packets comprises information relating to the plurality of data packets of its corresponding frame and additional information relating to a different one of the error correction frames. For example, the additional information relating to the different one of the error correction frames may be inserted into a header of the given error correction packet, and may comprise a next frame sequence number indicator and a corresponding next frame mask value for a subsequent one of the error correction frames.

Abstract: Linear Feedback Shift Registers (LFSRs) based 2p state with p>2 or p?2 scramblers, descramblers, sequence generators and sequence detectors in binary implementation are provided. An LFSR may apply devices implementing a binary XOR or EQUIVALENT function, a binary shift register and binary inverters and binary state generator, wherein at least an output of one shift register element in a first LFSR is connected to a device implementing a reversible binary logic function is a second LFSR. They may also apply 2p state inverters using binary combinational logic are applied. Memory based binary 2p state inverters are also applied. Non-LFSR based n-state scramblers and descramblers in binary logic are also provided. A method for simple correlation calculation is provided. Communication systems and data storage systems applying the provided LFSR devices are also disclosed.

Abstract: A method for transmitting data by using hybrid automatic repeat request (HARQ) is provided. A base station allocates a radio resource for a non-acknowledgement (NACK) channel which is used to transmit a NACK signal for multi-user data of a plurality of UEs, transmits the multi-user data, and retransmits the multi-user data when receiving the NACK signal on the NACK channel from at least one UE which receives the multi-user data.

Abstract: A systematic encoder such as a systematic polar encoder for channel encoding to ameliorate the effects of noise in a transmission channel. The codeword carries a data word to be transmitted transparently, and also carries a parity part derived from the data word and a fixed word. Implementations advantageously reduce coding complexity to the order of N log(N), wherein N is the dimension of a matrix of the nth Kronecker power associated with a matrix effectively employed by the encoder.

Abstract: An information communication terminal performs communications with another information communication terminal over a radio communication network system. In the information communication terminal, a receiving unit receives an externally transmitted frame. In a state where error correction is to be performed, a correction processing unit outputs data after performing error correction according to correction information in the frame on data in the frame received by the receiving unit. In a state where the error correction is not to be performed, the correction processing unit outputs the data without performing the error correction on the data in the frame received by the receiving unit. A determining unit determines whether the error correction is to be performed by the correction processing unit or not.

Abstract: Adaptive systems include a memory device including a plurality of memory cells, a data quality monitoring block, and an adaptive data encoding block, the data quality monitoring block and the adaptive data encoding block both being operatively coupled to the memory device. The data quality monitoring block is configured to determine a quality value of a group of one or more memory cells included in the memory device, the determined quality value being indicative of a quality of the group of one or more memory cells. The adaptive data encoding block is configured to select a coding scheme from a plurality of coding schemes to encode data to be written to the group of one or more memory cells in the memory device, the selection of the coding scheme being based at least in part on the determined quality value of the group of one or more memory cells.

Abstract: Adaptive endurance coding including a method for storing data that includes receiving write data and a write address. A compression algorithm is applied to the write data to generate compressed data. An endurance code is applied to the compressed data to generate a codeword. The endurance code is selected and applied in response to the amount of space saved by applying the compression to the write data. The codeword is written to the write address.

Abstract: A system and method for soft decoding data. A plurality of candidate error corrections may be generated to correct one or more data bits having soft bit information. Each candidate error correction may define suggested changes to the data bits and is associated with a soft bit value. The soft bit values associated the plurality of candidate error corrections may be mapped to a uniform scale, for example, a uniform finite or integer grid. The plurality of candidate error corrections may be ordered to have combined associated mapped values in a monotonically non-decreasing order. One or more of the plurality of candidate error corrections may be soft decoded in the order of the associated mapped values by a decoding operation for each candidate error correction therein with the associated non-mapped soft bit values.

Abstract: Methods and systems for storing data in a memory system with different levels of redundancy are disclosed. Methods and systems consistent with the present invention provide allow a redundancy level to be associated with received data, wherein associating the redundancy level of the data includes determining a desired level of protection for that data and determining the redundancy level based on the desired level of protection. A zone within a memory system is located that has a redundancy level that matches the redundancy level of the data, and the data is stored in the located zone with the desired redundancy level.

Abstract: Modem selection of codeword interleaver parameters given standard based, operator based and channel based communication channel performance constraints. A processor implements processes for characterizing the forward error correction codeword and interleaver solution space in terms of expressions from which targeted portions of the solution space may be identified prior to evaluation of the magnitude of the coefficients of the corresponding nodes thereof for compliance with the to communication channel performance constraints.

Abstract: A system and method for achieving higher data rates in physical layer devices. Costs imposed by large data rate increases represented by generational increases in Ethernet standards activities are avoided through physical layer device modifications that enable marginal increases in data bandwidth. Building-block reuse can be promoted through the selective use of clocking rate increase, increase in coding efficiency, and bit reuse.

Abstract: An IP-data transmitting apparatus performs an error correction coding by classifying data into a layer indicative of the priority order of the data based on importance and vulnerability of information included in the data, and combining a plurality of data components into combination patterns. The number of the combination patterns is specified with respect to each layer with predetermined priority order.

Abstract: A selection-signal generating circuit in an LSI being a transmission-side LSI, when a transmission error is detected on an A-side signal line and degeneration control is performed thereon, instructs a selector to select an input from an ECC generator in order to transmit data and ECC data for this data to be transmitted via the B-side signal line, via the A-side signal line. In this manner, the degenerated signal line is used to transmit the ECC data for transmission data to be transmitted via a signal line which is not degenerated.

Abstract: A system and a method of controlling transmitter power in a wireless communication system in which user data is processed as a multirate signal in which the user data signal having a first rate is converted into a transmission data signal having a faster second rate for transmission. The transmission power is adjusted on a relatively slow basis based on quality of data received by a receiver of the transmitted data. The transmitter power is determined as a function of the first and second rates such that a change in the data rate in the multiple channels or the rate of the transmission data signal is compensated in advance of a quality of data based adjustment associated with such data rate change.

Abstract: A wireless device calculates a number of FEC MPDUs based on an indicator value determined by the quality of the communication channel that are combined with data MPDUs in an aggregated data packet. The wireless device uses the indicator value to calculate an expected error transmission rate to dynamically adjust the number of FEC MPDUs in the aggregated data packet to reduce data retransmissions.

Abstract: Different transmissions based on different content blocks which were segmented from the same digital content according to different segmentation schemes, where each of the content blocks has any substring in common with at least one of the other content blocks, are received by a receiving radio communication station, for example a mobile telephone or a mobile network base station. Certain encoded received bits derived from different ones of the transmissions are combined into combined bits. Other encoded received bits derived from one or more of the different transmissions are provided together with the combined bits to a decoder.

Abstract: Systems and methods are provided for selecting precisions during iterative decoding with a low-density parity check (LDPC) decoder in order to maximize LDPC code's performance in the error floor region. The selection of the precision of the messages may be done in such a way as to avoid catastrophic errors and to minimize the number of near-codeword errors during the decoding process. Another system and method to avoid catastrophic errors in the layered (serial) LDPC decoder is provided. Lastly, a system and method that select precisions and provide circuitry that optimizes the exchange of information between a soft-input, soft-output (SISO) channel detector and an error correction code (ECC) decoder for channels with memory is provided.

Abstract: An iterative decoder comprising a transconductance amplifier, a sampler, a Min-Sum decoder, and an early determination module is provided. The transconductance amplifier outputs a current proportional to the voltage of the coded bit stream. The sampler converts the amplified current into a plurality of currents and stores the sampled currents in a plurality of buffers. The Min-Sum decoder receives parallel currents, wherein currents represent the message of each variable node. The Min-Sum decoder exchanges the message of variable nodes and check nodes iteratively and outputs a set of decode codewords according to the possibilities. The early terminating module stops the iterative decoding when the decoded codeword converged.

Abstract: Certain embodiments of the present invention are improved turbo-equalization methods for decoding encoded codewords. In one embodiment, in global decoding iteration i, the magnitude values of all decoder-input LLR values (Lch) are adjusted based on the number b of unsatisfied check nodes in the decoded codeword produced by global iteration i?1. The improved turbo-equalization methods can be used as the sole turbo-equalization method for a given global decoding session, or interleaved with other turbo-equalization methods.

Abstract: A receiver employs iterative decoding of packet data, where the packet data represents a data frame encoded with at least two logical dimensions. A logical dimension refers to a layer, or sub-layer, of a layered network architecture. Consequently, a first logical dimension of encoding might refer to error detection in a packet frame at the data link layer, while a second logical dimension of coding might refer to error detection/correction encoding at a physical layer. For example, a data frame might be divided into several packets, each with a corresponding cyclic redundancy check (CRC) value as coding in the first logical dimension, which are then transmitted with a convolutional code as coding in the second logical dimension. The receiver performs iterative decoding in the first and second logical dimensions until either i) all errors are identified and corrected or ii) another type of stopping condition is met.

Abstract: Example embodiments relate to an apparatus which may determine a length of data to be stored in a memory cell, and may store the data in a memory based on the determined length. A memory data storage apparatus according to example embodiments may, include: a determination unit that may determine a number of bits of data and a number of bits of data detection information to be stored in a memory cell; a data receiving unit that may receive data corresponding to the determined number of bits; an error correction coding unit that may perform an error correction coding with respect to the received data and generate data detection information corresponding to the number of bits of the data detection information; and a data storage unit that may store the received data and generated data detection information in the memory cell.

Abstract: In various embodiments, the reference voltage used for read operations in a non-volatile memory may be adjusted up or down in an attempt to read data from an area that previously produced at least one uncorrectable error. The direction and amount of this adjustment may be based on the number and direction of correctable errors in surrounding data.

Abstract: Continuously interleaved codewords are used in a communication system to provide error correction capability. In general, each codeword shares symbols with both preceding and subsequent codewords, when the codewords are arranged in an order, such that correction of symbols in any one codeword also corrects symbols in another codeword and correction of symbols in any codeword may allow, considering possible corrections of intermediate codewords, for further correction of any codeword in the order of codewords. In one embodiment received information may be arranged in subframes, with each subframe including terminal symbols of a plurality of codewords, each of the plurality of codewords including symbols in multiple subframes.

Abstract: A system allocates shared memory by transmitting/receiving a message specifying a maximum number of bytes of memory that are available to be allocated to an interleaver. The system determines an amount of memory required by the interleaver to interleave a first plurality of RS coded data bytes within a shared memory and allocates a first number of bytes of the shared memory to the interleaver to interleave the first plurality of RS coded data bytes for transmission at a first data rate. The system also allocates a second number of bytes of the shared memory to a deinterleaver to deinterleave a second plurality of RS coded data bytes received at a second data rate and interleaves the first plurality of RS coded data bytes within the shared memory allocated to the interleaver and deinterleaves the second plurality of RS coded data bytes within the shared memory allocated to the deinterleaver.

Abstract: An integrated circuit includes a signal source and a signal destination linked by a signal path. Error correction codes (e.g. Hamming codes) are applied to the signals to be transmitted. Errors detected in the signal transmission are used to control an operating parameter of the signal path, such as signal voltage level, body bias voltage, clock frequency and/or temperature. The control applied is closed-loop feedback control seeking to maintain a finite non-zero predetermined error rate. The technique can also be used between a memory accessing integrated circuit and a separate memory integrated circuit. Furthermore, the technique can be used to provide fixed, but differing operating parameters for signal lines within a signal path.

Abstract: Mechanisms are provided for processing streaming data at high sustained data rates. These mechanisms receive a plurality of data elements over a plurality of non-sequential communication channels and write the plurality of data elements directly to the file system of the data processing system in an unassembled manner. The mechanisms determining whether to perform a data scrubbing operation or not based on history information indicative of whether data elements in the plurality of data elements are being received in a substantially sequential manner. The mechanisms perform a data scrubbing operation, in response to a determination to perform data scrubbing, to identify any missing data elements in the plurality of data elements written to the file system and assemble the plurality of data elements into a plurality of data streams in response to results of the data scrubbing indicating that there are no missing data elements.

Abstract: A recording/reproducing apparatus includes an encoding section, a decoding section, and a first judging section. The encoding section is configured to encode data that is to be recorded onto a recording medium into an LDPC (Low Density Parity Check) code. The decoding section is configured to decode the LDPC code read out from the recording medium. The judging section is configured to judge a block with a recording error based on one of a block error flag and an iterative decoding count output from the decoding section.

Abstract: A continuous redundancy check method and apparatus receives (110) at least one data bit of a block's payload, calculates (120) a partial redundancy check value using the at least one data bit, compares (130) the partial redundancy check value with a reference value, and stores (134, 138) in an index an indication of whether the calculated redundancy check value matched the reference value. Meanwhile, the at least one data bit is also stored (140) in a data memory. As additional data bits of the payload are received, cumulative partial redundancy check values are calculated and compared to the reference value. When the complete payload has been stored (140), the index is analyzed (160, 165) to determine if a block error has been detected by the redundancy check functions. This continuous redundancy check method and apparatus allows a receiver to quickly determine whether a block error has occurred, especially when there may be padding (or dummy) bits in the block's payload.

Abstract: An IC card is provided that is capable of identifying a communication type of incoming data received by non-contact communication. The IC card includes: an error detection portion that, for each of a plurality of communication types, performs error detection of incoming data based on an encoding format defined by each of the communication types; and a type identification portion that identifies, among the plurality of communication types, a communication type in which error information is not detected by the error detection portion as a communication type of the incoming data.

Abstract: Variable modulation within combined LDPC (Low Density Parity Check) coding and modulation coding systems. Variable modulation encoding of LDPC coded symbols is presented. In addition, LDPC encoding, that generates an LDPC variable code rate signal, may also be performed as well. The encoding can generate an LDPC variable code rate and/or modulation signal whose code rate and/or modulation may vary as frequently as on a symbol by symbol basis. Some embodiments employ a common constellation shape for all of the symbols of the signal sequence, yet individual symbols may be mapped according different mappings of the commonly shaped constellation; such an embodiment may be viewed as generating a LDPC variable mapped signal. In general, any one or more of the code rate, constellation shape, or mapping of the individual symbols of a signal sequence may vary as frequently as on a symbol by symbol basis.

Abstract: Apparatus and methods store error recovery data in different dimensions of a memory array. For example, in one dimension, block error correction codes (ECC) are used, and in another dimension, supplemental error correction codes, such as convolutional codes, are used. By using separate dimensions, the likelihood that a defect affects both error recovery techniques is lessened, thereby increasing the probability that error recovery can be performed successfully. In one example, block error correction codes are used for data stored along rows, and this data is stored in one level of multiple-level cells of the array. Supplemental error correction codes are used for data stored along columns, such as along the cells of a string, and the supplemental error correction codes are stored in a different level than the error correction codes.

Abstract: A system and method for detection of rate determination algorithm errors in variable rate communications system receivers. The disclosed embodiments prevent rate determination algorithm errors from causing audible artifacts such as screeches or beeps. The disclosed system and method detects frames with incorrectly determined data rates and performs frame erasure processing and/or memory state clean up to prevent propagation of distortion across multiple frames. Frames with incorrectly determined data rates are detected by checking illegal rate transitions, reserved bits, validating unused filter type bit combinations and analyzing relationships between fixed code-book gains and linear prediction coefficient gains.

Abstract: The present invention provides a method for enhancing reliability of information transmission by (a) establishing a matrix based on the length of bits of valid information in frame time slots; and creating a new matrix by presetting Error Correction Coding (ECC) for rows and columns of said matrix; (b) adopting the 1st Interleaving method to re-allocate bits which have been processed twice by using said ECC in said new matrix, to both ends of said frame time slots; and (c) adopting the 2nd Interleaving method to re-allocate the remaining bits in said new matrix to the middle of said frame time slots. After processed like this, the anti-interfering ability of the bits at both ends of TDMA frame time slot can be significantly enhanced, and the bit-error rate is decreased most, and all redundancy bits of Hamming codes can be arrayed at both ends of TDMA frame time slot.

Abstract: A method for data storage in a memory (28) that includes a plurality of analog memory cells (32) includes estimating respective achievable storage capacities of the analog memory cells. The memory cells are assigned respective storage configurations defining quantities of data to be stored in the memory cells based on the estimated achievable capacities. The data is stored in the memory cells in accordance with the respective assigned storage configurations. The achievable storage capacities of the analog memory cells are re-estimated after the memory has been installed in a host system and used for storing the data in the host system. The storage configurations are modified responsively to the re-estimated achievable capacities.

Abstract: A method and apparatus are described for recovering from loss of an original data packet, including detecting data packet loss, joining a delayed multicast group, receiving a delayed data packet and using the delayed data packet to recover the original data packet that was lost. The delayed data packet is one of a copy of the original data packet, a copy of the original data packet encoded at a lower bit rate or a parity packet. Also described are a method and apparatus for staggercasting including encoding and compressing a first data sequence, packetizing the compressed encoded data sequence to form a data packet, multicasting the data packet to a first multicast group, encoding and compressing a second data sequence, packetizing the compressed encoded second data sequence to form a packet and multicasting the packet delayed by an offset time to a second multicast group.

Abstract: A scalable information signal is protected in a more efficient and/or safe way by adopting the inter-relationship among the plurality of portions of different levels within the information signal in FEC protecting the information signal. In particular, portions of the information signal representing the information content at a higher level should have associated therewith redundancy information which is dependent not only on that part of this portion being disjoint to a respective overlapping lower level portion. Rather, redundancy information should also be dependent on the latter part so as to increase the chances of success of forward error correcting an error within the lower level portion at the reception side.

Abstract: Methods are disclosed for improving communications on feedback transmission channels, in which there is a possibility of bit errors. The basic solutions to counter those errors are: proper design of the CSI vector quantizer indexing (i.e., the bit representation of centroid indices) in order to minimize impact of index errors, use of error detection techniques to expurgate the erroneous indices and use of other methods to recover correct indices.

Abstract: Embodiments of a broadcast receiver and method for optimizing a scale factor in a log-likelihood ratio (LLR) mapper are generally described herein. In some embodiments, the broadcast receiver includes an LLR mapper to generate LLRs from demodulated data samples, a low-density parity-check (LDPC) decoder to generate decoded data from the LLRs, and an LLR optimizer to dynamically select a scale factor for the LLR mapper based on a number of iterations for convergence of the LDPC decoder. In some embodiments, the LLR optimizer iteratively revises the scale factor during receipt of broadcast signals until the number of iterations of the iterative decoder is either minimized for convergence or minimized for convergence failures.

Abstract: An iterative turbo decoder for a wireless transmit receive unit (WTRU) of a wireless communication system and method for error correcting received communication signal data are provided. The decoder implements a stopping rule through use of signature codes to determine whether successive iterations of decoder data are the same.

Abstract: A network communication device includes a host interface, which is coupled to communicate with a host processor, having a host memory, so as to receive a work request to execute a transaction in which a plurality of data blocks are to be transferred over a packet network. Processing circuitry is configured to process multiple data packets so as to execute the transaction, each data packet in the transaction containing a portion of the data blocks, and the multiple data packets including at least first and last packets, which respectively contain the first and last data blocks of the transaction. The processing circuitry is configured to compute a transaction signature over the data blocks while processing the data packets so that at least the first data block passes out of the network communication device through one of the interfaces before computation of the transaction signature is completed.

Abstract: Techniques for transmitting and receiving multiple channels with block coding in a communication system are disclosed. In one aspect, a secondary broadcast channel is transmitted concurrently with parity information, encoded from a primary broadcast channel. In another aspect, a mobile station repurposes its receiving circuitry to receive one or more portions of the secondary broadcast channel after a sufficient portion of the primary broadcast channel is received without identified error. In another aspect, secondary broadcast channels associated with a plurality of primary broadcast channels are multiplexed onto a single secondary channel. Various other aspects are also presented. These aspects have the benefit of minimizing mobile station resources required to receive multiple broadcast channels, as well as reducing the complexity and channel resources required to transmit multiple broadcast channels.

Abstract: A system and method for achieving higher data rates in physical layer devices. Costs imposed by large data rate increases represented by generational increases in Ethernet standards activities are avoided through physical layer device modifications that enable marginal increases in data bandwidth. Building-block reuse can be promoted through the selective use of clocking rate increase, increase in coding efficiency, and bit reuse.

Abstract: When a determination section of a reception apparatus determines that a control channel is intended for the reception apparatus, a comparing section of the reception apparatus compares control information transmitted on the control channel with a reception capability of the reception apparatus. A data channel reception section of the reception apparatus receives a data channel when the control information is within the reception capability of the reception apparatus, but does not receive the data channel when the control information exceeds the reception capability of the reception apparatus. When the control information exceeds the reception capability of the reception apparatus, the transmission section does not transmit an ACK signal and a NACK signal with respect to the data channel.

Abstract: An encoding of K blocks of information for transmission on N subchannels, responsive to a number of redundant blocks M, employs one of multiple check codes depending on the number of redundant blocks M and employs multiple processes for determining a code for the K blocks of information depending on the number of redundant blocks M and K blocks of information together.

Abstract: A forward error correction (FEC) method is provided including an FEC dynamic central station and a plurality of FEC dynamic remote stations that transmit bearer data and corresponding error correction data therebetween during a plurality of time frames. The error rate of the communication channel is measured and the amount of error correction data transmitted is accordingly and dynamically adjusted, so that the minimum amount of overhead required to effectively transmit the error correction data is used.