For Packet Or Frame Multiplexed Data Patents (Class 714/776)
  • Patent number: 12010033
    Abstract: There is disclosed a router for routing data on a computing chip comprising a plurality of processing elements, the router comprising: a packet processing pipeline; a dropped packet buffer; and one or more circuits configured to: determine that a data packet in the packet processing pipeline is to be dropped; move the data packet that is to be dropped from the packet processing pipeline to the dropped packet buffer; and re-insert the dropped data packet from the dropped packet buffer into the packet processing pipeline for re-processing.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: June 11, 2024
    Assignee: COGNISCIENCE LIMITED
    Inventors: Steve Furber, Gengting Liu
  • Patent number: 12002540
    Abstract: A memory device includes a set of inputs, and a first register that includes a first register field to store a value for enabling application of one of a plurality of command/address (CA) on-die termination (ODT) impedance values to first inputs that receive the CA signals; and a second register field to store a value for enabling application of one of a plurality of chip select (CS) ODT impedance values to a second input that receives the CS signal. A third register field may store a value for enabling application of a clock (CK) ODT impedance value to third inputs that receive the CK signal.
    Type: Grant
    Filed: June 26, 2023
    Date of Patent: June 4, 2024
    Assignee: RAMBUS INC.
    Inventors: Ian Shaeffer, Kyung Suk Oh
  • Patent number: 12003253
    Abstract: Apparatuses, systems, and techniques to compute cyclic redundancy checks use a graphics processing unit (GPU) to compute cyclic redundancy checks. For example, in at least one embodiment, an input data sequence is distributed among GPU threads for parallel calculation of an overall CRC value for the input data sequence according to various novel techniques described herein.
    Type: Grant
    Filed: August 13, 2021
    Date of Patent: June 4, 2024
    Assignee: NVIDIA Corporation
    Inventor: Andrea Miele
  • Patent number: 11979232
    Abstract: A system performs verification of Ethernet hardware. A data frame including a first portion for storing a checksum value and a second portion for storing a timestamp value is received. The second portion of data frame is set to zero. A timestamp value for including in second portion of the data frame is received. A modified checksum value is determined based on the checksum value included in the first portion of the data frame and the timestamp value. A cyclic redundancy check (CRC) value is determined for the data frame by nullifying the checksum value in the data frame and considering the timestamp value. A final CRC value is determined by combining the CRC value for the data frame and a CRC correction value based on the checksum. The modified data frame is sent for processing using an emulator.
    Type: Grant
    Filed: September 13, 2022
    Date of Patent: May 7, 2024
    Assignee: Synopsys, Inc.
    Inventors: Jishnu De, Jaspreet Singh Gambhir
  • Patent number: 11977771
    Abstract: A memory device includes: a plurality of memory cells; soft read logic configured to generate soft data by reading data from the plurality of memory cells in response to a soft read command from a controller, the soft data including at least a major symbol and at least a minor symbol; a compressor configured to generate compressed data by: encoding, into a code alphabet having a second length, a major source alphabet including repetitions of the major symbol by a first length among a plurality of source alphabets included in the soft data, and encoding, into a code alphabet having a longer length than the second length, a minor source alphabet including repetitions of the major symbol by a shorter length than the first length and ending with one minor symbol; and an interface configured to provide the compressed data to the controller.
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: May 7, 2024
    Assignee: SK hynix Inc.
    Inventors: Dae Sung Kim, Sung Ho Ahn, Sin Ho Yang, Jae Hyeong Jeong
  • Patent number: 11956173
    Abstract: The present invention relates to a wireless communication system, and more particularly, to a method and apparatus for receiving information on a number N of a code block group defined for one transport block from a base station through an upper layer signal, receiving a first transport block including a plurality of code blocks from the base station through a physical layer channel, and transmitting HARQ-ACK payload including HARQ-ACK information on the first transport block to the base station. Preferably, a code block-based CRC is attached to each of the code blocks, a transport block-based CRC is attached to the first transport block, and the HARQ-ACK payload includes a plurality of HARQ-ACK bits corresponding to M code block groups for the first transport block.
    Type: Grant
    Filed: October 17, 2022
    Date of Patent: April 9, 2024
    Assignee: LG Electronics Inc.
    Inventors: Suckchel Yang, Kijun Kim, Seonwook Kim, Changhwan Park, Joonkui Ahn, Hanjun Park, Seunggye Hwang
  • Patent number: 11956174
    Abstract: The present invention relates to a wireless communication system, and more particularly, to a method and apparatus for receiving information on a number N of a code block group defined for one transport block from a base station through an upper layer signal, receiving a first transport block including a plurality of code blocks from the base station through a physical layer channel, and transmitting HARQ-ACK payload including HARQ-ACK information on the first transport block to the base station. Preferably, a code block-based CRC is attached to each of the code blocks, a transport block-based CRC is attached to the first transport block, and the HARQ-ACK payload includes a plurality of HARQ-ACK bits corresponding to M code block groups for the first transport block.
    Type: Grant
    Filed: October 17, 2022
    Date of Patent: April 9, 2024
    Assignee: LG Electronics Inc.
    Inventors: Suckchel Yang, Kijun Kim, Seonwook Kim, Changhwan Park, Joonkui Ahn, Hanjun Park, Seunggye Hwang
  • Patent number: 11949626
    Abstract: The present disclosure provides a terminal device that allows constraints on user allocation to be prevented and spread codes to be allocated in a scheduler when non-adaptive HARQ is employed using a PHICH. A codeword generator generates code words by encoding data, a layer mapping unit places each CW in one or a plurality of layers, a DMRS generator generates a reference signal for each layer in which a CW is placed by using any resource among a plurality of resources defined by a mutually orthogonal plurality of OCCs, and an ACK/NACK demodulator receives a response signal indicating a retransmission request. When a response signal requesting retransmission of only a CW placed in a plurality of layers is received, the DMRS generator uses each resource having the same OCC among the plurality of resources for the reference signals generated in the corresponding layers.
    Type: Grant
    Filed: January 3, 2023
    Date of Patent: April 2, 2024
    Assignee: Sun Patent Trust
    Inventors: Masayuki Hoshino, Akihiko Nishio, Daichi Imamura
  • Patent number: 11937244
    Abstract: A method performed by a wireless device (410) includes transmitting an uplink, UL, burst to a network node (460). The UL burst includes UL control information, UCI, multiplexed in a Physical Uplink Shared Channel, PUSCH. The UCI carries one or more parameters for unlicensed operation, and the UL burst has an associated UL burst structure. The UL burst structure includes a first slot, a full slot, and a last slot.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: March 19, 2024
    Assignee: Telefonaktiebolagget LM Ericsson (Publ)
    Inventors: Reem Karaki, Jung-Fu Cheng
  • Patent number: 11929834
    Abstract: A redundant communication apparatus includes a determining unit and a transmitting unit. The determining unit determines an upper limit of a redundancy level when transmission waiting data in a transmission apparatus is made redundant and transmitted, based on a data quantity of the transmission waiting data and a communication speed of a communication line between a reception apparatus that is a transmission destination of the transmission waiting data and the transmission apparatus. The transmitting unit causes the transmission waiting data to be made redundant at a redundancy level that is equal to or less than the upper limit determined by the determining unit and transmits the data to the reception apparatus via the communication line.
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: March 12, 2024
    Assignee: DENSO CORPORATION
    Inventor: Tsuneo Nakata
  • Patent number: 11914475
    Abstract: A method for coding (k, r) data and a method for reconstructing data are provided. The coding method includes steps consisting in: dividing an initial datum a into k data blocks ai; grouping the k data blocks into r?1 subsets Sj of data blocks; generating, for each subset Sj, a linear function gj(a) defined as a linear combination of the data blocks assigned to said subset Sj; and generating r parity functions comprising a primary parity function f0(a) as a linear combination of the k data blocks ai, and r?1 secondary parity functions, each secondary parity function fj(a) being defined as the sum of the primary parity function f0(a) and of a linear function gj(a).
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: February 27, 2024
    Assignee: INSTITUT MINES TELECOM
    Inventors: Hana Baccouch, Nadia Boukhatem
  • Patent number: 11888777
    Abstract: Certain aspects of the present disclosure provide techniques for autonomous reference signal transmission configuration. Certain aspects provide a method of receiving a configuration message from the base station, wherein the configuration message comprises an indication of a set of candidate resources for transmitting the reference signal. Certain aspects provide a method of detecting a future downlink transmission from the base station, and other aspects provide a method of transmitting, in response to detecting the future downlink transmission, the reference signal utilizing a first resource of the set of candidate resources prior to receiving the future downlink transmission via a second resource in the set of candidate resources.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: January 30, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Vinay Joseph, Rajat Prakash, Peerapol Tinnakornsrisuphap, Mostafa Khoshnevisan, Piyush Gupta, Junyi Li, Farhad Meshkati
  • Patent number: 11870458
    Abstract: Embodiments herein relate to a method performed by a network node for handling a received signal in a communication network. The network node distributes a first number of inputs of a demodulated signal to a first processing core of at least two processing cores and a second number of inputs of the demodulated signal to a second processing core of the at least two processing cores. The network node further decodes the first number of inputs of the demodulated signal by a first message passing within the first processing core, and decodes the second number of inputs of the demodulated signal by a second message passing within the second processing core. The network node further decodes the demodulated signal by performing a third message passing between the different processing cores over a bus that is performed according to a set schedule.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: January 9, 2024
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Hugo Tullberg, Guido Carlo Ferrante
  • Patent number: 11863713
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for image frame freeze detection. An example hardware accelerator includes a core logic circuit to generate second image data based on first image data associated with a first image frame, the second image data corresponding to at least one of processed image data, transformed image data, or one or more image data statistics, a load/store engine (LSE) coupled to the core logic circuit, the LSE to determine a first CRC value based on the second image data obtained from the core logic circuit, and a first interface coupled to a second interface, the second interface coupled to memory, the first interface to transmit the first CRC value obtained from the memory to a host device.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: January 2, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Niraj Nandan, Brian Chae, Mihir Mody, Rajasekhar Reddy Allu
  • Patent number: 11855775
    Abstract: Embodiments of this application disclose a signal transcoding method performed by an electronic device. The method includes: acquiring an encoding result of an ith signal frame and encoding results respectively corresponding to first n signal frames of the ith signal frame; generating forward error correction (FEC) encoding results respectively corresponding to the first n signal frames according to the encoding results respectively corresponding to the first n signal frames; and synthesizing the encoding result corresponding to the ith signal frame and the FEC encoding results respectively corresponding to the first n signal frames to generate an encoded frame corresponding to the ith signal frame, the encoded frame comprising a flag bit for indicating a value of n. According to this application, a quantity of FEC encoded frames included in an encoded frame can be flexibly adjusted to improve the reliability of data transmission in a poor network state.
    Type: Grant
    Filed: August 30, 2022
    Date of Patent: December 26, 2023
    Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Qingbo Huang, Wei Xiao
  • Patent number: 11843458
    Abstract: A control device for use in a broadcast system includes a broadcast controller that controls a broadcast transmitter of the broadcast system that broadcasts broadcast signals in a coverage area for reception by terminals including a broadcast receiver and a broadband receiver, and a broadband controller that controls a broadband server of a broadband system that provides redundancy data to terminals within the coverage area. The broadband controller is configured to control the provision of redundancy data by the broadband server for use by one or more terminals which use the redundancy data together with broadcast signals received via said broadcast system for recovering content received within the broadcast signals and/or provided via the broadband system.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: December 12, 2023
    Assignee: SATURN LICENSING LLC
    Inventors: Junge Qi, Joerg Robert, Jan Zoellner, Lothar Stadelmeier, Nabil Loghin
  • Patent number: 11843459
    Abstract: The present disclosure provides an encoding and decoding device implementing an improved forward error correction (FEC) coding/decoding method. In particular, the encoding device is configured to encode a stream of data symbols using a spatially coupled code (e.g. staircase codes, braided block codes or continuously interleaved block codes), wherein at least one generalized error location (GEL) code is used as a component code of the spatially coupled code. Accordingly, the decoding device is configured to decode a sequence of encoded symbol blocks using a spatially coupled code, wherein at least one GEL code is used as a component code of the spatially coupled code. Thereby, a suitable spatially coupled FEC code that allows for very low-latency, high-throughput, high-rate applications with a low-complexity decoding procedure, and allows for mitigation of the error-floor, is designed.
    Type: Grant
    Filed: June 10, 2022
    Date of Patent: December 12, 2023
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Vladimir Vitalievich Gritsenko, Vladislav Nikolaevich Obolentsev, Dmitrii Yurievich Bukhan, Aleksei Eduardovich Maevskii, Hongchen Yu, Kun Gu, Jie Chen, Shiyao Xiao, Man Zhao, Jun Chen, Yunlong Li
  • Patent number: 11831430
    Abstract: This disclosure relates to encoding and decoding methods and apparatuses. The method may include encoding an ith signal frame, to obtain an encoded result of the ith signal frame. The method may further include performing forward error correction encoding on first n signal frames, to obtain forward error correction encoded results corresponding to the first n signal frames. The first n signal frames may be signal frames located before the ith signal frame. The method may further include synthesizing the encoded result of the ith signal frame and the forward error correction encoded results corresponding to the first n signal frames, to obtain an ith encoded frame corresponding to the ith signal frame. The ith encoded frame may comprise a flag bit, the flag bit may be for indicating a number n, and n may be a positive integer greater than or equal to 2.
    Type: Grant
    Filed: August 31, 2022
    Date of Patent: November 28, 2023
    Assignee: Tencent Technology (Shenzhen) Company Limited
    Inventors: Qingbo Huang, Wei Xiao, Meng Wang, Ling Zhu
  • Patent number: 11822515
    Abstract: Drivers in different functional paths can use different types of identifiers for the same hardware device, such that the drivers may not be able to natively coordinate their actions related to the hardware device due to incompatible identifier types. However, a driver at a file system layer of one functional path can obtain a volume Physical Device Object (PDO) identifier at a volume layer and find a disk PDO identifier at a disk layer that is associated with the same device number. The driver can also find a parent device instance identifier from the disk PDO identifier, and use the parent device instance identifier as a plug-and-play (PnP) identifier for the hardware device during communications with a second driver in a PnP functional path.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: November 21, 2023
    Assignee: CrowdStrike, Inc.
    Inventors: Cameron Gutman, Aaron LeMasters
  • Patent number: 11817881
    Abstract: A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.
    Type: Grant
    Filed: January 6, 2023
    Date of Patent: November 14, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Se-ho Myung, Hong-sil Jeong, Kyung-joong Kim
  • Patent number: 11804925
    Abstract: A method for data transmission includes receiving a data stream from a host device, the data stream as received from the host device including encoded data, separating the encoded data in the data stream into first data blocks and second data blocks, and generating a first forward error correction (FEC) block. The first FEC block includes a first parity section and a first data section, the first parity section includes a first parity bit corresponding to the first data blocks and a second parity bit corresponding to the second data blocks, and the first data section includes the first data blocks and the second data blocks. The method further includes transmitting the first FEC block.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: October 31, 2023
    Assignee: Marvell Asia Pte Ltd.
    Inventors: Jamal Riani, Benjamin Smith, Volodymyr Shvydun, Sudeep Bhoja, Arash Farhoodfar
  • Patent number: 11791845
    Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). A channel encoding method in a communication or broadcasting system includes identifying an input bit size, determining a block size (Z), determining an LDPC sequence for LDPC encoding, and performing the LDPC encoding based on the LDPC sequence and the block size.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: October 17, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seokki Ahn, Kyungjoong Kim, Seho Myung, Hongsil Jeong, Min Jang
  • Patent number: 11784867
    Abstract: A communication device includes an acquisition unit that acquires a bit sequence, and a conversion unit that converts the bit sequence to a predetermined complex constellation point sequence including a plurality of complex constellation points including a non-zero complex constellation point and a zero complex constellation point. At least one of the predetermined complex constellation point sequences is a first complex constellation point sequence in which each of a plurality of complex constellation points constituting the complex constellation point sequence is converted to any complex constellation point or zero complex constellation point of a first signal constellation including non-power of two number of complex constellation points. The conversion unit converts one of the bit sequences to at least the first complex constellation point sequence.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: October 10, 2023
    Assignee: SONY GROUP CORPORATION
    Inventors: Ryota Kimura, Hiroki Matsuda, Yukitoshi Sanada
  • Patent number: 11777525
    Abstract: A method for encoding a quasi-cyclic low-density parity-check (LDPC) code according to an embodiment of the present invention may comprise the steps of: generating a multi-edge LDPC code matrix including a high rate code matrix and a single parity check code matrix; and encoding a signal by using the multi-edge LDPC code matrix, wherein the single parity check code matrix includes a first matrix having a non-row-orthogonal structure matrix and a second matrix having a pure row-orthogonal structure, which are concatenated.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: October 3, 2023
    Assignee: LG Electronics Inc.
    Inventors: Jongwoong Shin, Bonghoe Kim, Jinwoo Kim, Ilmu Byun
  • Patent number: 11750322
    Abstract: A method for channel encoding in a communication or broadcasting system is provided. The method includes determining a block size Z, and performing encoding based on the block size and a first matrix corresponding to the block size, wherein the first matrix is determined based on information and a plurality of second matrices, and wherein a part of a column index indicating a position of a non-zero element in each row of the information includes an index according to mathematical expression 22 above.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: September 5, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyungjoong Kim, Seho Myung, Seokki Ahn, Hongsil Jeong, Min Jang
  • Patent number: 11742876
    Abstract: According to one embodiment, an interleaving unit divides a symbol string into first and second symbols. A first coding unit converts the first symbols to first codewords. A first packet generating unit generates first packets including the first codewords. A first request generating unit generates first packet requests including sizes of variable length packets. A second coding unit converts the second symbols to second codewords. A second packet generating unit generates second packets including the second codewords. A second request generating unit generates second packet requests including sizes of variable length packets. A multiplexer outputs a compressed stream including the first and second variable length packets cut out from the first and second packets.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: August 29, 2023
    Assignee: Kioxia Corporation
    Inventors: Masato Sumiyoshi, Keiri Nakanishi, Kohei Oikawa, Sho Kodama
  • Patent number: 11736123
    Abstract: A zero padding apparatus and method for fixed length signaling information are disclosed. A zero padding apparatus according to an embodiment of the present invention includes a processor configured to generate a LDPC information bit string by deciding a number of groups whose all bits are to be filled with 0 using a difference between a length of the LDPC information bit string and a length of a BCH-encoded bit string, selecting the groups using a shortening pattern order to fill all the bits of the groups with 0, and filling at least a part of remaining groups, which are not filled with 0, with the BCH-encoded bit string; and memory configured to provide the LDPC information bit string to an LDPC encoder.
    Type: Grant
    Filed: August 19, 2022
    Date of Patent: August 22, 2023
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Jae-Young Lee, Heung-Mook Kim
  • Patent number: 11714715
    Abstract: A plurality of storage nodes in a single chassis is provided. The plurality of storage nodes in the single chassis is configured to communicate together as a storage cluster. Each of the plurality of storage nodes includes nonvolatile solid-state memory for user data storage. The plurality of storage nodes is configured to distribute the user data and metadata associated with the user data throughout the plurality of storage nodes such that the plurality of storage nodes maintain the ability to read the user data, using erasure coding, despite a loss of two of the plurality of storage nodes. A plurality of compute nodes is included in the single chassis, each of the plurality of compute nodes is configured to communicate with the plurality of storage nodes. A method for accessing user data in a plurality of storage nodes having nonvolatile solid-state memory is also provided.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: August 1, 2023
    Assignee: PURE STORAGE, INC.
    Inventors: John Hayes, John Colgrove, John D. Davis
  • Patent number: 11716170
    Abstract: A protocol layer on top of the Bluetooth low energy (BLE) system of paired devices to provide transmission that allows arbitrary sizes of data to be sent. To guarantee transmissions, the transmissions may be validated and, if required, resent to replace data that was lost or corrupted. The protocol layer also supports Remote Procedure Calls to allow functions on either of two connected devices to be executed on one device on behalf of the other. A further protocol layer also allows high priority, short messages to temporarily interrupt the transmission of low priority, long messages.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: August 1, 2023
    Assignee: RLT IP LTD.
    Inventors: Paula A. Maddox, Richard E. Collins, Ferenc Visztra, Peter Robins
  • Patent number: 11711098
    Abstract: A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate parity bits; a parity permutator configured to group-wise interleave a plurality of bit groups including the parity bits; and a puncturer configured to select some of the parity bits in the group-wise interleaved bit groups and puncture the selected parity bits, wherein the parity permutator group-wise interleaves the bit groups such that some of the bit groups at predetermined positions in the bit groups before the group-wise interleaving are positioned serially after the group-wise interleaving and a remainder of the bit groups before the group-wise interleaving are positioned without an order after the group-wise interleaving so that the puncturer selects parity bits included in the some of the bit groups sequentially and selects parity bits included in the remainder of the bit groups without an order.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: July 25, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Se-ho Myung, Kyung-joong Kim, Hong-sil Jeong
  • Patent number: 11711244
    Abstract: Disclosed are a method for transmitting a sounding reference signal, a terminal device and a network device. The method comprises: a terminal device determining, in a first time-domain resource unit, a plurality of second time-domain resource units for sending a sounding reference signal (SRS) of the terminal device; the terminal device determining, according to a frequency hopping pattern of the terminal device, a target resource for sending the SRS on the plurality of second time-domain resource units; and the terminal device sending, according to the target resource, the SRS to a network device. The present invention reduces the interference of SRS signals between different terminal devices, and also avoids the occurrence of a continuous strong interference situation between terminal devices.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: July 25, 2023
    Assignee: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.
    Inventor: Hai Tang
  • Patent number: 11700016
    Abstract: A zero padding apparatus and method for variable length signaling information are disclosed. A zero padding apparatus according to an embodiment of the present invention includes a processor configured to generate a LDPC information bit string by deciding a number of groups whose all bits are to be filled with 0 using a difference between a length of the LDPC information bit string and a length of a BCH-encoded bit string, selecting the groups using a shortening pattern order to fill all the bits of the groups with 0, and filling at least a part of remaining groups, which are not filled with 0, with the BCH-encoded bit string; and memory configured to provide the LDPC information bit string to an LDPC encoder.
    Type: Grant
    Filed: March 15, 2022
    Date of Patent: July 11, 2023
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Jae-Young Lee, Heung-Mook Kim
  • Patent number: 11689222
    Abstract: A parity interleaving apparatus and method for variable length signaling information are disclosed. A parity interleaving apparatus according to an embodiment of the present invention includes a processor configured to generate a parity bit string for parity puncturing by segmenting parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, into a plurality of groups, and group-wise interleaving the groups using an order of group-wise interleaving; and memory configured to provide the parity bit string for parity puncturing to a parity puncturing unit.
    Type: Grant
    Filed: June 2, 2022
    Date of Patent: June 27, 2023
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Jae-Young Lee, Heung-Mook Kim
  • Patent number: 11688441
    Abstract: A memory device includes a set of inputs, and a first register that includes a first register field to store a value for enabling application of one of a plurality of command/address (CA) on-die termination (ODT) impedance values to first inputs that receive the CA signals; a second register field to store a value for enabling application of one of a plurality of chip select (CS) ODT impedance values to a second input that receives the CS signal; and a third register field to store a value for enabling application of a clock (CK) ODT impedance value to third inputs that receive the CK signal. The memory device also includes second and third registers to store values for selecting one of the plurality of CA ODT impedance values and one of the plurality of CS ODT impedance values for application to the first inputs and second input, respectively.
    Type: Grant
    Filed: September 27, 2022
    Date of Patent: June 27, 2023
    Assignee: RAMBUS INC.
    Inventors: Ian Shaeffer, Kyung Suk Oh
  • Patent number: 11683125
    Abstract: Systems, methods, and instrumentalities are disclosed for interleaving coded bits. A wireless transmit/receive unit (WTRU) may generate a plurality of polar encoded bits using polar encoding. The WTRU may divide the plurality of polar encoded bits into sub-blocks of equal size in a sequential manner. The WTRU may apply sub-block wise interleaving to the sub-blocks using an interleaver pattern. The sub-blocks associated with a subset of the sub-blocks may be interleaved, and sub-blocks associated with another subset of the sub-blocks may not be interleaved. The sub-block wise interleaving may include applying interleaving across the sub-blocks without interleaving bits associated with each of the sub-blocks. The WTRU may concatenate bits from each of the interleaved sub-blocks to generate interleaved bits, and store the interleaved bits associated with the interleaved sub-blocks in a circular buffer. The WTRU may select a plurality of bits for transmission from the interleaved bits.
    Type: Grant
    Filed: May 17, 2022
    Date of Patent: June 20, 2023
    Assignee: InterDigital Patent Holdings, Inc.
    Inventors: Chunxuan Ye, Fengjun Xi, Sungkwon Hong, Kyle Jung-Lin Pan, Robert L. Olesen
  • Patent number: 11683126
    Abstract: Embodiments herein disclose conditioning traffic through multiple data paths of a Software-Defined Wide Area Network (SD-WAN). Some embodiments include monitoring available paths through an SD-WAN to reach a destination node, determining a quality score for packets to the destination node on a first path of the available paths, sending a data packet sequence to the destination node on the first path, generating a forward error correction (FEC) packet for the packet sequence, and sending the FEC packet to the destination node on a second path of the available paths in response to the quality score being less than a quality threshold.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: June 20, 2023
    Assignee: VERSA NETWORKS, INC.
    Inventors: Kapil Bajaj, Apurva Mehta
  • Patent number: 11677494
    Abstract: A method for enhanced error protection using double-cyclic redundancy check (CRC) includes receiving a first packet, by a first physical layer (PHY). The first packet includes a source packet and a first CRC. The method also includes encrypting the first packet having the first CRC to generate an encrypted first packet. The method further includes appending a second CRC to the encrypted first packet to produce a second packet, and transmitting the second packet to a second PHY via a transmission line.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: June 13, 2023
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Sundararajan Chidambara, Sameer Kanhaiyalal Shah, Nishant Chadha
  • Patent number: 11641214
    Abstract: A transmitting apparatus is disclosed. The transmitting apparatus includes an encoder to perform channel encoding with respect to bits and generate a codeword, an interleaver to interleave the codeword, and a modulator to map the interleaved codeword onto a non-uniform constellation according to a modulation scheme, and the constellation may include constellation points defined based on various tables according to the modulation scheme.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: May 2, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Se-ho Myung, Belkacem Mouhouche, Daniel Ansorregui Lobete, Kyung-joong Kim, Hong-sil Jeong
  • Patent number: 11636061
    Abstract: Embodiments herein describe on-demand packetization where data that is too large to be converted directly into data words (DWs) for a chip-to-chip (C2C) interface are packetized instead. When identifying a protocol word that is larger than the DW of the C2C interface, a protocol layer can perform packetization where a plurality of protocol words are packetized and sent as a transfer. In one embodiment, the protocol layer removes some or all of the control data or signals in the protocol words so that the protocol words no longer exceed the size of the DW. These shortened protocol words can then be mapped to DWs and transmitted as separate packets on the C2C. The protocol layer can then collect the portion of the control data that was removed from the protocol words and transmit this data as a separate packet on the C2C interface.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: April 25, 2023
    Assignee: XILINX, INC.
    Inventors: Krishnan Srinivasan, Sagheer Ahmad, Ygal Arbel
  • Patent number: 11637570
    Abstract: One example method includes obtaining L1 first decoding paths of an (i?1)th group of to-be-decoded bits, where i is an integer, received data corresponds to P groups of to-be-decoded bits, and 1<i?P, determining at least one second decoding path corresponding to each first decoding path, where a quantity of second decoding paths corresponding to each first decoding path is less than 2n, and where n is a quantity of information bits included in an ith group of to-be-decoded bits, and determining at least one reserved decoding path of the ith group of to-be-decoded bits in second decoding paths corresponding to the L1 first decoding paths. The at least one reserved decoding path includes a decoding result of the ith group of to-be-decoded bits.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: April 25, 2023
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Liang Ma, Hang Li, Yuejun Wei
  • Patent number: 11637735
    Abstract: A transmitting apparatus is disclosed. The transmitting apparatus includes an encoder to perform channel encoding with respect to bits and generate a codeword, an interleaver to interleave the codeword, and a modulator to map the interleaved codeword onto a non-uniform constellation according to a modulation scheme, and the constellation may include constellation points defined based on various tables according to the modulation scheme.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: April 25, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Se-ho Myung, Belkacem Mouhouche, Daniel Ansorregui Lobete, Kyung-joong Kim, Hong-sil Jeong
  • Patent number: 11625296
    Abstract: A method of correcting a memory error of a dynamic random-access memory module (DRAM) using a double data rate (DDR) interface, the method includes conducting a memory transaction including multiple bursts with a memory controller to send data from data chips of the DRAM to the memory controller, detecting one or more errors using an ECC chip of the DRAM, determining a number of the bursts having the errors using the ECC chip of the DRAM, determining whether the number of the bursts having the errors is greater than a threshold number, determining a type of the errors, and directing the memory controller based on the determined type of the errors, wherein the DRAM includes a single ECC chip per memory channel.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: April 11, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dimin Niu, Mu-Tien Chang, Hongzhong Zheng, Hyun-Joong Kim, Won-hyung Song, Jangseok Choi
  • Patent number: 11611351
    Abstract: In described examples, a sample and hold circuit is configured to periodically connect one input of an op-amp to a reference voltage through a switch while a second input of the op-amp is connected to an output of the op-amp. Offset cancellation is performed by storing a sampled offset on a sampling capacitor coupled to the second input of the op-amp.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: March 21, 2023
    Assignee: Texas Instruments Incorporated
    Inventor: Maher Mahmoud Sarraj
  • Patent number: 11606693
    Abstract: A method in a first node of a wireless communications network comprises: inspecting a data packet or message to determine a characteristic of the data packet or message; and selectively activating integrity protection for onward transmission of the data packet or message to a second node of the wireless communications network based on the determined characteristic.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: March 14, 2023
    Assignee: Telefonaktiebolaget LM Ericsson (Publ)
    Inventors: Gunnar Bergquist, Prajwol Kumar Nakarmi, Fredrik Sonnevi
  • Patent number: 11595228
    Abstract: A data system of a towing vehicle and/or trailer vehicle includes a control device, a sensor system configured to record and process sensor data, and a BUS system configured to transfer the sensor data between the control device and the sensor system. The BUS system has a first BUS device in the form of a CAN BUS and a second BUS device in the form of an ETHERNET BUS, and the BUS system further has a first interface configured to transfer the sensor data to a second interface of a second BUS system of a second data system of a second towing vehicle and/or trailer vehicle. The data system additionally includes an intelligent switch, coupled to the control device and/or to the first interface, the intelligent switch being configured to couple the first towing vehicle and/or trailer vehicle to the second towing vehicle and/or trailer vehicle in a coordinated manner.
    Type: Grant
    Filed: August 15, 2018
    Date of Patent: February 28, 2023
    Assignee: ZF CV SYSTEMS EUROPE BV
    Inventors: Thomas Dieckmann, Andreas Goers, Sebastian Kuehne, Ralph-Carsten Luelfing, Marco Michel, Thomas Wolf, Oliver Wulf
  • Patent number: 11595152
    Abstract: Embodiments of the present disclosure relate to a binary clustered forward error correction encoding scheme. Systems and methods are disclosed that define binary clustered encodings of the media packets from which forward error correction (FEC) packets are computed. The different encodings specify which media packets in a frame are used to compute each FEC packet (a frame includes M media packets). The different encodings may be defined based on the quantity of media packets in a frame, M?floor(2N), where each bit of the binary representation of N is associated with a different cluster pair encoding of the media packets. Each cluster pair includes a cluster for which the bit=0 and a cluster for which the bit=1. Computing FEC packets using at least two cluster pair encodings provides redundancy for each media packet, thereby improving media packet recovery rates.
    Type: Grant
    Filed: November 4, 2021
    Date of Patent: February 28, 2023
    Assignee: NVIDIA Corporation
    Inventors: Shridhar Majali, Harsh Chandresh Maniar, Reza Marandian Hagh
  • Patent number: 11575467
    Abstract: Systems, procedures, and instrumentalities are disclosed for transmissions with polar codes. A transmitting entity may determine a mother code length. The mother code length may be based on value(s), e.g., a maximum number of transmissions. The transmitting entity may determine a number of information bits to be polar encoded. The number of information bits may be larger than a number of payload bits. The transmitting entity may map the number of information bits to a number of bit channels of a polar code. The transmitting entity may polar encode the information bits in the bit channels using the determined mother code length. The transmitting entity may partition the polar encoded bits into a number of parts. The number of parts may be based on one or more values, e.g., the maximum number of transmissions. The transmitting entity may transmit bits that have been interleaved to a circular buffer.
    Type: Grant
    Filed: November 12, 2018
    Date of Patent: February 7, 2023
    Assignee: InterDigital Patent Holdings, Inc.
    Inventors: Chunxuan Ye, Fengjun Xi, Kyle Jung-Lin Pan
  • Patent number: 11575394
    Abstract: A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: February 7, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Se-ho Myung, Hong-sil Jeong, Kyung-joong Kim
  • Patent number: 11569924
    Abstract: A first network element includes trail trace identifier information in an optical network frame. The first network element obtains data to transmit over an optical network link to a second network element. The first network element generates an optical network frame with alignment marker bytes, which are followed by padding bytes. The optical network frame also includes overhead bytes following the padding bytes. The overhead bytes include a Multi-Frame Alignment Signal (MFAS) byte, a link status byte, and reserved bytes. The optical network frame also includes a payload bytes following the overhead bytes. The payload bytes encode at least a portion of the data to transmit to the second network element. The first network element inserts trail trace identifier information into the reserved bytes in the overhead bytes. The trail trace identifier information identifies the first network element as a source of the optical network frame.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: January 31, 2023
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Gilberto Loprieno, Stefano Binetti, Paolo Sironi
  • Patent number: RE49925
    Abstract: The present technology relates to a data processing device and a data processing method, which are capable of securing excellent communication quality in data transmission using an LDPC code. In group-wise interleave, an LDPC code in which a code length N is 16200 bits and an encoding rate r is 6/15, 8/15, or 10/15 is interleaved in units of bit groups of 360 bits. In group-wise deinterleave, a sequence of the LDPC code that has undergone the group-wise interleave is restored to an original sequence. For example, the present technology can be applied to a technique of performing data transmission using an LDPC code.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: April 16, 2024
    Assignee: Saturn Licensing LLC
    Inventors: Ryoji Ikegaya, Makiko Yamamoto, Yuji Shinohara