Abstract: A method and a system for decoding information signals encoded in accordance with a multi-state encoding scheme and transmitted over a multi-dimensional transmission channel by computing a distance of a received word from a codeword. One-dimensional (1D) input signals are processed in a pair of symbol decoders, implemented as look-up tables, to produce a pair of 1D errors, with each representing a distance metric between the input signal and a symbol in one of two disjoint symbol-subsets. The 1D errors are combined based on the multi-state encoding scheme in order to produce a set of multi-dimensional error terms. Each of the multi-dimensional error terms corresponds to a distance between a received word and a nearest codeword.

Abstract: A prediction device and method for use in a Viterbi decoder is provided. The prediction device is applicable to a communication system with low bit error rate for reducing the count of accessing path memories, thereby lowering the power consumption of the system. The prediction device needs not activate the traceback modules when making a successful prediction. In other words, no access to the path memories is required. The predicted bits decoded and outputted by the decoded bit registers are the decoded bits from the Viterbi decoder. Therefore, the prediction device saves much traceback and power consumption for decoding.

Abstract: A method (700) and apparatus (600) are described for performing 2M?1 parallel ACS operations to generate 2M path metric outputs and buffering the 2M path metric outputs in connection with a track buffer (112) in an Ultrawide Bandwidth (UWB) receiver for decoding a message sequence encoded according to a convolutional code. Contents of the track buffer are updated in accordance with Register Exchange and outputs from the track buffer can further be input to a voting unit (114) where a voting scheme can be applied and a decision rendered as to the originally transmitted message sequence.

Abstract: In one embodiment, interleaved signals in a receiver are accessed by memory pointers and delivered to data stream locations without the need to transfer data to an intermediate physical buffer.

Abstract: Joint decoding of ISI (Inter-Symbol Interference) channel and modulation codes. A means is presented by which a single, combined ISI and modulation decoding module is operable to process a signal received from an ISI communication channel and directly to generate a soft estimate of information encoded therein. A single module, that employs a decoding transfer function that is substantially matched to the communication channel that introduces the ISI and the modulation encoding performed on the information before being launched into the ISI communication channel. This means is adaptable to a variety of modulation coding systems that are tailored to deal with communication systems that introduce ISI. Moreover, this means is extendable to communication systems employing an error correction code (ECC) such as Reed-Solomon (RS) coding as well as ECCs of an iterative nature such as LDPC (Low Density Parity Check) coding, turbo coding, and/or turbo trellis code modulation (TTCM) coding.

Abstract: A data recording and reproducing system adds a first error correcting code to input data to generate a first code block, encodes the first code block with a second error correcting code to generate a second code block, interleaves the second code block to generate a recording block, and records and reproduces the recording block via a partial response channel including a recording medium. An output signal from the partial response channel, and thus the second code block, is decoded; the decoded data and the reliability of the decoded data is determined, based on likelihood information obtained during iterative decoding; and the first error correcting code is decoded. The decoded data and the reliability information are supplied to the first error correcting code decoder.

Abstract: A path-select-signal memory section in the Viterbi detector outputs each decoded data B?Sik corresponding to a branch that occurred a prescribed time ago in a surviving path to each state at a present time, in response to path select signals SEL0, SEL1. A shift register stores the path select signals SEL0, SEL1 in order of time. A binary output unit outputs a decoded bit corresponding to a branch that occurred a prescribed time ago in a surviving path. Output signal lines of the binary output unit and a selector train are connected according to a trellis diagram that corresponds to encoding operation.

Abstract: A configurable Viterbi decoder to decode a coded signal for inclusion in a radio receiver for implementing the physical layer receiving function (PHY) of a wireless data network. The decoder includes a branch metric generator with an input to the coded signal, an ACS subsystem coupled to the branch metric generator, and a survivor memory unit coupled to the ACS subsystem. The decoder includes a plurality of outputs each providing a decoded version of the input signal decoded to a distinct decision depth such that the Viterbi decoder is programmable to decode the signal to one of a plurality of decision depths.

Abstract: Turbo encoded data is received in a wireless communication system. A signal is received including the turbo encoded data. An initial data estimation is performed on the received signal. At least one iteration of turbo decoding is performed on the estimated data. A subsequent data estimation is performed using the received signal and the result of the turbo decoding. At least one iteration of turbo decoding is performed on a result of the subsequent data estimation.

Abstract: Decoder design adaptable to decode coded signals using min* or max* processing. A very efficient means of min* processing or max* processing may be performed within a communication device to assist in the very complex and cumbersome calculations that are employed when decoding coded signals. The types of coded signals that may be decoded using min* processing or max* processing are varied, and they include LDPC (Low Density Parity Check) coded signals, turbo coded signals, and TTCM (Turbo Trellis Coded Modulation) coded signals, among other coded signal types. Many of the calculations and/or determinations performed within min* processing or max* processing are performed simultaneously and in parallel of one another thereby ensuring very fast operation. In a finite precision digital implementation, when certain calculated bits of min* or max* processing are available, they govern selection of resultants from among multiple calculations and determinations made simultaneously and in parallel.

Abstract: The present invention relates to an addressing architecture for parallel processing of recursive data. A basic idea of the present invention is to store a calculated new path metric at the memory location used by the old path metric, which old metric was employed to calculate the new metric. If m metric values are read and m metric values are simultaneously calculated in parallel, it is possible to store the new, calculated metrics in the memory position where the old metrics were held. The present invention is advantageous, since the size of the storage area for the path metrics is reduced to half compared to the storage area employed in prior art Viterbi decoders for the same performance with regard to path metric computations.

Abstract: A system and method for Reverse Error Correction Coding. The system includes a Constraint encoder, an Error Correction Code encoder, and a uniform interleaver. The Constraint encoder receives a source data stream and generates a first intermediate encoded data stream satisfying a first predetermined timing data constraint. The Error Correction Code encoder receives the first intermediate encoded data stream and generates a second intermediate encoded data stream having one or more Error Correction Code based elements. The uniform interleaver receives the second intermediate encoded data stream and generates a channel data stream having the one or more Error Correction Code based elements and satisfying a second predetermined timing data constraint.

Abstract: Various systems and methods for generating and/or ordering error indications are disclosed herein. In some cases, the error indication is used as an erasure pointer in a memory access system. As one particular example, a system for ordering erasure pointers is disclosed that includes a group of N sort cells, where N is a whole number. Each of the sort cells is operable to maintain a respective error indication that includes an error value and an associated error pointer. Further, the group of N sort cells is operable to receive an incoming error indication including error value and associated error pointer, and to update the error indication of one or more of the group of N sort cells based in part on the incoming error value. The system also includes a selector circuit that is operable to allow selectable access to each of the respective error pointers maintained in the group of N sort cells.

Abstract: An iterative method and a device for decoding received signals transmitted in data frames via various channels. In order to be able to utilize the computing capacity of digital signal processors (DSPs) as efficiently as possible, it is proposed that, starting at a first channel, the quality of the decoded signal transmitted via the first channel is checked following every iteration and switchover takes place to at least one further channel if a specifiable switchover condition exists. The switchover condition may, for example, be a specifiable quality of the decoded signal transmitted via the channel under consideration. To determine the quality of the decoded signal a cyclic redundancy check (CRC), in particular, is proposed following every iteration.

Abstract: A high-speed radix-4 butterfly module and the method of performing Viterbi decoding using the same. The high-speed radix-4 butterfly module includes first to fourth add-compare-select (ACS) circuits. The first and the second ACS circuits receive first to fourth branch metric values and first to fourth previous-stage path metric values, and accordingly produces a first and a second path metric values. The third and the fourth ACS circuits receive fifth to eighth branch metric values and the first to the fourth previous-stage path metric values, and accordingly produces a third and a fourth path metric values. The radix-4 butterfly unit of the invention uses the symmetric relation to reduce an amount of branch computation required for each radix-4 butterfly unit to a half. Thus, the circuit complexity of the typical radix-4 butterfly module and the hardware cost of the Viterbi decoder are reduced.

Abstract: The present invention provides systems and methods for adaptively decoding transmitted frames efficiently in non-Gaussian, non-stationary environments. One such system comprises a decoder adapted to decode a received transmission frame using a decoding scheme, a channel assessment unit for sensing channel characteristics, and a tuning unit for adjusting the decoding scheme based, at least in part, on channel characteristics sensed by the channel assessment unit.

Abstract: The need for separate CRC bits is eliminated by taking advantage of what has been determined to be an embedded error detection capability of the tail bits generated by the constituent encoders of a turbo coder to perform error detection following turbo decoding. Specifically, it has been recognized that the tail bits are similar to CRC bits that would be generated by a CRC encoder that uses as its generating polynomial the feedback polynomial used by the turbo encoder. At the turbo decoder, after a final turbo decoding iteration cycle, a check is performed on the decoded systematic information bits by calculating the tail bits from the decoded information bits using that generating polynomial and bit-by-bit comparing the calculated tail bits with the systematic tail bits decoded by the turbo decoder. If a mismatch occurs at one or more bit positions, an error is indicated.

Abstract: An apparatus for reproducing data includes a branch metric computation unit and a plurality of parallel computation units. Each parallel computation unit includes path metric computation units that compute path metric values based on branch metric values. Path metric memories store the path metric values to be used in a next following path metric computation, and reliability computation units compute path reliability. Modified-path generating units generate an inverted path that is inverse to a path indicated by an output of the reliability computation units as having low reliability. If any one of the modified-path generating units generates the inverted path, a corresponding one of the path metric computation units stores a path metric value corresponding to the inverted path in a corresponding one of the path metric memories as a path metric value to be used in a next following path metric computation.

Abstract: At the receiver in a wireless communications system, the likelihood of a false CRC pass that can occur when a weak received signal produces an all ZERO output from a convolutional or a turbo decoder is minimized. To prevent an all ZERO output, a convolutional decoder selects from among those determined equally most likely transmitted sequences of bits in a data block one that has a weight greater than the one having the minimum weight. A turbo decoder selects a ONE rather than a ZERO as the value of a transmitted bit in a data block when for that bit a bit value of a ZERO and a ONE are determined to be equally likely.

Abstract: The present invention provides systems and methods for correcting errors in a received frame. The present invention introduces diversity into an error detection and correction system at the receiver side by decoding a received frame using a plurality of decoding schemes. Each of these schemes are optimized for a different set of underlying assumptions. The schemes may be optimized to account for various types of noise including, not limited to, Gaussian noise and impulsive noise. The plurality of decoded frames are then validated using an outer decoder to choose a valid frame from candidate decoded frames. By including a plurality of decoders using a plurality of decoding schemes, the error detection and correction system may accurately detect and correct errors in a constantly changing environment having constantly changing noise patterns.

Abstract: A Viterbi decoder is configured for subtracting each survivor metric for each corresponding encoder state by a prescribed subtraction operator based on a prescribed event. The subtraction of each survivor metric by a prescribed subtraction operator based on a prescribed event minimizes memory requirements in the accumulated metric table by limiting the survivor metric values to a identifiable range. Hence, the Viterbi decoder can be implemented in an economical manner with reduced memory requirements.

Abstract: A Viterbi decoder that identifies errors in an early decision output comprises an early decision generator that generates the early decision output. An error detector detects errors in the early decision output and generates a signal when the early decision output errors are detected.

Abstract: A Viterbi decoder that identifies errors in a full decision output comprises a full decision generator that generates the full decision output. An error detector detects errors in the full decision output and generates a signal when the full decision output errors are detected.

Abstract: A method and apparatus are disclosed for improving the maximum data rate of reduced-state Viterbi detectors with local feedback. The maximum data rate that may be achieved by the disclosed reduced-state Viterbi detectors is improved by precomputing a number of candidate branch metrics and performing pipelined selection of an appropriate branch metric. A reduced-state Viterbi detector is thus disclosed that precomputes branch metrics for speculative sequences of one or more channel symbols; selects one of said precomputed branch metrics based on at least one decision from at least one corresponding state using at least two pipeline registers; and selects a path having a best path metric for a given state.

Abstract: A method and an apparatus for scaling demodulated data symbols contained in a packet to generate scaled log-likelihood ratios for Turbo decoding are disclosed. A packet consists of one or more subpackets depending on the type of packet. Each subpacket is identified by a subpacket identification number. The payload size of the packet and the subpacket identification number may be determined by decoding a reverse rate indicator (RRI) channel. A scale factor which is associated with a specific subpacket identification number and a specific payload size results in a performance measure that is closest to an expected performance measure. The scale factor is used for scaling the demodulated data symbols to generate scaled log-likelihood ratios for Turbo decoding.

Abstract: A method for reducing fading channel signal data loss for serial data rates up to approximately 10 gigabits per second includes sequentially distributing serial data to multiple encoders. Individual data bytes are sent from the encoders to a convolutional interleaver. Each byte is distributed to an individual memory element of the interleaver in a received byte sequence. An address generator generates write and read addresses assignable to each memory element. Multiple shift registers have variably graduated lengths. The serial data is distributed between channels each having a different delay element created by shift register length differences. The delay elements are adjustable to correct data dropout due to daily atmospheric/channel changes. Fade detection signals are inserted before transmission and measured at a receiver. The fade signals help create erasure bits to improve decoding accuracy and adjust interleaver delay parameters.

Abstract: In an error correction method, a codeword is transmitted through a noisy communication channel and detected by a receiving device. An error detection code is then applied to the detected codeword to generate a syndrome. Where the syndrome is not all zero, the codeword is determined to contain some error. Accordingly, the method computes a set of potential error start positions for a plurality of error events based on a syndrome value corresponding to the syndrome. Next, a confidence value is computed for each of the plurality of error events at each of the potential error start positions in the refined set, and finally, a most likely error event in the detected codeword is corrected based on an error event and corresponding potential error start position having the highest confidence value.

Abstract: A decision-driven control loop wherein a first reconstructed signal is compared to an unreconstructed data symbol signal to initially drive the control loop. A second reconstructed signal that is based on a longer memory path than the first reconstructed signal is evaluated against the first reconstructed signal. The decision-driven control loop is ultimately controlled based on the results of the evaluation between the first and second reconstructed signals. The inventive decision-driven control loop, which may be implemented in software, may form part of a read channel in a storage device.

Abstract: A digital signal decoding device according to an aspect of the present invention is a digital signal decoding device for generating a binary code sequence by maximum likelihood estimation from a convolutionally encoded input signal sequence, includes an add-compare-select unit configured to compare only two metric values one unit time before the calculation time of a predetermined branch metric value calculated from the input signal sequence at two successive times at each time, to add the predetermined branch metric value to the two metric values independently of the compare process, to select one of the two sums in accordance with the comparison result of the two metric values, and to output the selected value as a metric value to be used at the next time.

Abstract: A method and apparatus for the implementation of reduced state sequence estimation is disclosed with an increased throughput using precomputation (look-ahead), with only a linear increase in hardware complexity with respect to the look-ahead depth. The present invention limits the increase in hardware complexity by taking advantage of past decisions (or survivor symbols). The critical path of a conventional RSSE implementation is broken up into at least two smaller critical paths using pipeline registers. Various reduced state sequence estimation implementations are disclosed that employ one-step or multiple-step look-ahead techniques to process a signal received from a dispersive channel having a channel memory.

Abstract: A trellis traceback apparatus and method are disclosed. In one aspect, the apparatus may include a branch indication memory, memory address logic, a selector, and a shift register. The memory may store branch indication information for a state at a section, the information indicating a branch that leads to the state. The memory address logic may indicate the section. The selector may receive the branch indication information for the state at the indicated section. The selector may select the branch indication information based on received selection information. The shift register may provide information stored in a plurality of register segments to the selector as the selection information, and the shift register may receive and store the selected branch indication information.

Abstract: A second stage SOVA detector comprises a dynamic state reordering block with inputs that receive absolute state domain data from a first stage SOVA detector. The second stage SOVA detector provides relative state domain data outputs and selection bit outputs. The second stage SOVA detector comprises pipeline registers. The pipeline registers receive the relative state domain data outputs and the selection bit outputs and provide pipelined outputs. The second stage SOVA detector comprises a reliability update-register exchange unit receiving the pipelined outputs and providing detected data bits and reliabilities.

Abstract: A method and apparatus detecting binary data, the apparatus includes an analog-to-digital (AD) converter converting the input analog signal into a digital signal; at least one binarization unit converting the digital signal into binary data; a viterbi decoder performing viterbi decoding to detect binary data from the digital signal; and a level detector receiving the digital signal, receiving at least two binary data from one of the viterbi decoder and the at least one binarization unit, and detecting and outputting a level value for the viterbi decoding from the digital signal when a number of the at least two binary data, which correspond to each other on a time axis and have the same values, is equal to or greater than a predetermined number. Accordingly, it is possible to more precisely detect binary data from an analog signal.

Abstract: Method for computing distances to received data points. A preferred embodiment comprises determining a first point on a grid nearest to the received point, computing a second point closest to the received point inside a specified area, wherein the second point is a point in a first coset, computing a third, fourth, and fifth point, wherein each point is a member of a different coset and each point is the closest point in its coset to the received point, and computing a distance from the received point to each of the second, third, fourth, and fifth points.

Abstract: The invention provides a data decoding apparatus and method by which the data rate can be discriminated at a high speed using a Viterbi decoding process. Receive data are successively Viterbi decoded beginning with the top thereof. At a point of time when receive data which may possibly be end bit position data required for data rate discrimination are Viterbi decoded, data necessary for the data rate discrimination are successively extracted, and the data rate is discriminated based on the extracted necessary data.

Abstract: An apparatus and method of reducing power dissipation in a register exchange implementation of a Viterbi decoder used in a digital receiver or mass-storage system without degrading the bit error rate of the decoder, by selectively inhibiting data samples in the Viterbi decoder's register memory from being shifted if the data samples have converged to a single value. FIFO memories keep track of what data samples have converged, the order of the samples, and the converged data value, thereby keeping the decoded data in the FIFO synchronized with data continuing to be shifted through the register memory.

Abstract: An E2PR4 Viterbi detector receives a signal that represents a sequence of values, the sequence having a potential state. The detector includes a recovery circuit that recovers the sequence from the signal by identifying the surviving path to the potential state and simultaneously adding a modified branch metric to the path metric of the surviving path. By simultaneously identifying the surviving path and adding a modified branch metric to its path metric, such an E2PR4 Viterbi detector can operate faster than a conventional add-compare-select E2PR4 Viterbi detector.

Abstract: A pragmatic trellis code modulation decoder including a demodulator for receiving a modulated signal and computing coordination values of symbols of the modulated signal on an I-axis and Q-axis in a constellation; a coset mapper for generating 3-bit soft decision data based on the computed coordinate values; a viterbi decoder for receiving 3-bit soft decision data and generating 1-bit data as a coded data by decoding the 3-bit soft decision data; a re-encoder for receiving the 1-bit data from the viterbi decoder and obtaining un-coded information in order to compute an un-coded data; a sector phase quantizer for obtaining I channel and Q channel information based on the coordination values from the demodulator in order to obtain un-coded data; a time delayer for delaying output of the sector phase quantizer until the re-encoder outputs the un-coded information; and a non-coded code decoder for computing the un-coded data.

Abstract: A decoding apparatus includes simultaneous decoding means for sequentially Viterbi-decoding a plurality of data sequences over respective data lengths from the start at the same time, and stop means for sequentially comparing likelihoods of respective data sequences which are simultaneously Viterbi-decoded by the simultaneous decoding means and stopping the simultaneous decoding means from decoding a certain data sequence if it is determined based upon the compared result that a likelihood of the certain data sequence is lower than a threshold value.

Abstract: When a convolution code is decoded, electric power consumption is certainly suppressed keeping error correction capability. In a Viterbi decoder 100 which decodes received signal, a convolution code, having plural series with a soft decision Viterbi decoding method, an estimation control unit 30 estimates quality of the received signal and outputs control signal M according to the quality to a branch metric calculation data obtaining unit 20. The branch metric calculation data obtaining unit 20 performs logical combination operation between digital multi-value data S1 expressing amplitude of the received signal and the control signal M, and thereby, outputs the digital multi-value data S1 directly to a decoding execution unit 90 if the quality of the received signal is lower than a prescribed level, and outputs the digital multi-value data S1 reduced by series each as branch metric calculation data S2 to the decoding execution unit 90 if the quality of the received signal is no less than the prescribed level.

Abstract: Viterbi decoder for decoding a received sequence of data symbols which are coded using a predetermined coding instruction is provided. The Viterbi decoder includes a branch metric calculation circuit for calculation of branch metrics for the received sequence of coded data symbols. The Viterbi decoder includes a path metric calculation circuit for calculation of path metrics as a function of the branch metrics and the coding instruction, with the calculated path metrics in each case being compared with an adjustable decision threshold value in order to produce an associated logic validity value. The Viterbi decoder also includes a selection circuit which temporarily stores those path metrics whose validity value is logic high in a memory, and selects from the temporarily stored path metrics that path with the optimum path metric.

Abstract: In a method for equalization of a data signal based on the Viterbi algorithm, trellis contributions are first of all calculated for reconstructed signal values from transition metrics, and are stored in a first table memory. If a reduced trellis diagram is intended to be used as the basis for calculation of the transition metrics, decision feedback contributions are also calculated, and are stored in a further table memory. In the case of ACS operations, the first and, if appropriate, the further table memories are accessed in order to determine the reconstructed signal values.

Abstract: In accordance with an embodiment of the present invention, a Viterbi decoder is described that operates on convolutional error correcting codes. The decoder allows for a pipelined architecture and a unique partitioning of survivor memory to maintain data integrity. Throughput rate is improved and stalling minimized by accessing memory words using a look-ahead function to fill the pipeline.

Abstract: To obtain best performance from a turbo decoder using a SOVA algorithm a normalization unit is used. By using normalization, the complexity of the decoder is increased. To decrease the complexity it is proposed not to normalize all of the decoding units output. In this way, computational complexity is reduced with only a small degradation in performance.

Abstract: A digital signal processor includes a functional unit configured to execute instructions. The functional unit determines a first minimum data of a first data and a second data, in parallel with a determination of a second minimum data of a third data and a fourth data. The functional unit outputs processed data including the first minimum data and the second minimum data. Each bit length of the first minimum data and the second minimum data is equal to n bits in length. A bit length of the processed data is equal to 2 n bits in length.

Abstract: A method of reducing complexity in a Viterbi decoding algorithm used in intersymbol interference channels is provided. The method includes the steps of identifying a survivor path for an input symbol, making a hard decision about a polarity of the input symbol based on the identified survivor path, identifying a plurality of dominant error events for which the opposite polarity would be determined for the input symbol, measuring a penalty metric value based on the identified survivor path for each of the plurality of dominant error events, choosing a dominant error event having a least penalty metric value from the identified plurality of dominant error events, and calculating an approximation to a logarithmic likelihood ratio for the input symbol based on the survivor path and the chosen dominant error event.

Abstract: The present invention is a multi-carrier communication system for transmitting/receiving signals via at least four sub-channels, comprising: a transmitter for transmitting data independently via the four sub-channels; a receiver comprising a receive unit disposed for each sub-channel for receiving data from a corresponding sub-channel and performing soft decision of the receive data; and means for inputting soft decision target values in receive units corresponding to three sub-channels other than a target sub-channel to a receive unit of the target sub-channel, wherein the receive unit of the target sub-channel adjusts its own soft decision target value using the soft decision target values that are input from the receive units of the other sub-channels, and decides the receive data based on this adjusted soft decision target value.

Abstract: A receiver system that receives signals and has a demapper device that is responsive to an equalizer output and generates a demapper output including one or more bit metrics. The receiver system also generates equalizer output, and the demapper uses distance measure to calculate bit metrics. The receiver system uses demapper output to generate a processed output. The receiver system further includes a convolutional decoder which is responsive to the processed output, and subsequently generates a decoded bit sequence, as well as uses the processed output to generate one or more path metrics. The convolutional decoder uses bit metrics and path metrics to the decode processed output, to generate a decoded bit sequence. The receiver system uses the distance measure to reduce the size of the bit metrics and the size of the path metrics to improve the performance of said convolutional decoder.

Abstract: Two correlation signals which are obtained by computing correlations between two reference signals and a reception signal are inputted to a level-0 cell, the reference signals being generated on the basis of combinations of crosstalk coefficients. A level-1 soft judgment target signal is produced by using soft judgment target signals that are outputted by two sets of level-0 cells respectively and, similarly, a level (N+1) cell is formed by using two sets of level-N cells, whereby a soft judgment target signal creation portion with a hierarchical structure is constituted. A judgment unit outputs a soft judgment value of the target subchannel on the basis of the soft judgment target signal that is outputted by the level (N+1) cell, and judges a reception signal.

Abstract: Digital circuits and methods for designing digital circuits are presented. More particularly, the present invention relates to error correction circuits and methods in communications and other systems. In the present invention, a novel K-nested layered look-ahead method and its corresponding architecture, which combine K-trellis steps into one trellis step (where K is the encoder constraint length), are proposed for implementing low-latency high-throughput rate Viterbi decoder circuits. The main idea of the present invention involves combining K-trellis steps as a pipeline structure and then combining the resulting look-ahead branch metrics as a tree structure in a layered manner to decrease the ACS precomputation latency of look-ahead Viterbi decoder circuits. The proposed method guarantees parallel paths between any two trellis states in the look-ahead trellises and distributes the add-compare-select (ACS) computations to all trellis layers.