Abstract: Encoded symbols of a concatenated convolutional-encoded and block encoded signal are presented to a conventional first stage of a concatenated decoder, comprising in sequence a soft metric generator, a Viterbi decoder, a first de-interleaver and a first block decoder such as a Reed-Solomon decoder. The encoded symbols are also presented to a delay chain to produce progressively delayed encoded symbols. Where an output block of the conventional decoder is indicated as being a valid codeword by the first block decoder, the bytes in this block are marked as being correct. These bytes that are known to be correct are then used after interleaving and serialization as known bits input to a second stage of the decoder process operating on the delayed encoded symbols and incorporating a modified soft metric generator constrained by the known bits. This process can be extended to further iterations as required.

Abstract: An application specific processor to implement a Viterbi decode algorithm for channel decoding functions of received symbols. The Viterbi decode algorithm is at least one of a Bit Serial decode algorithm, and block based decode algorithm. The application specific processor includes a Load-Store, Logical and De-puncturing (LLD) slot that performs a Load-Store function, a Logical function, a De-puncturing function, and a Trace-back Address generation function, a Branch Metric Compute (BMU) slot that performs a Radix-2 branch metric computations, a Radix-4 branch metric computations, and Squared Euclidean Branch Metric computations, and an Add-Compare-Select (ACS) slot that performs a Radix-2 Path metric computations, a Radix-4 Path metric computations, a best state computations, and a decision bit generation. The LLD slot, the BMU slot and the ACS slot perform in a software pipelined manner to enable high speed Viterbi decoding functions.

Abstract: A data detection and decoding system includes a SOVA channel detector that uses single parity (SOVASP) to improve the accuracy with which the detector estimates bits. Each column or row read back from the read channel constitutes a code word and each code word is encoded to satisfy single parity. Because the SOVASP channel detector detects whether each code word satisfies single parity, it is unnecessary to use both a column decoder and a row decoder in the channel decoder. Either the row decoder or the column decoder can be eliminated depending on whether bits are read back on a column-by-column basis or on a row-by-row basis. This reduction in components reduces hardware complexity and improves system performance. The output of the row or column decoder is received by a second detector that processes the output received from the decoder to recover the original information bits.

Abstract: Pairs of parallel Viterbi decoders use windowed block data for decoding data at rates above 320 Mbps. Memory banks of the deinterleavers feeding the decoders operate such that some are receiving data while others are sending data to the decoders. Parallel input streams to every pair of decoders overlap for several traceback lengths of the decoder causing data input to a first decoder at the end of an input stream to be the same as the data input to a second decoder of the same pair at the beginning of an input stream. Then, the first decoder is able to post-synchronize its path metric with the second decoder and the second decoder is able to pre-synchronize its path metric with the first. Either, the deinterleaver data length is an integer multiple of the traceback length or the data input to only the first block of the first interleaver is padded.

Abstract: In a digital system using a turbo code, a method for performing iterative decoding in accordance with a Log-MAP Algorithm comprises the steps of:—generating a look-up table comprising a plurality of values representative of a correcting factor;—performing a first calculation to obtain a forward metric;—performing a second calculation to obtain a backward metric;—performing a third calculation to obtain a log-likelihood ratio for every information bit to be decoded. In accordance with the method, at least one and no more than two of such calculations are performed by the use of said look-up table for implementing the Log-MAP decoding algorithm and the remaining calculations are performed implementing a Max-Log-MAP decoding algorithm.

Abstract: Serial concatenated trellis coded modulation (SCTCM) includes an outer coder, an interleaver, a recursive inner coder and a mapping element. The outer coder receives data to be coded and produces outer coded data. The interleaver permutes the outer coded data to produce interleaved data. The recursive inner coder codes the interleaved data to produce inner coded data. The mapping element maps the inner coded data to a symbol. The recursive inner coder has a structure which facilitates iterative decoding of the symbols at a decoder system. The recursive inner coder and the mapping element are selected to maximize the effective free Euclidean distance of a trellis coded modulator formed from the recursive inner coder and the mapping element. The decoder system includes a demodulation unit, an inner SISO (soft-input soft-output) decoder, a deinterleaver, an outer SISO decoder, and an interleaver.

Abstract: When a convolution code is decoded, electric power consumption is suppressed keeping error correction capability. In a Viterbi decoder which decodes received signal, a convolution code, having plural series with a soft decision Viterbi decoding method, an estimation control unit estimates quality of the received signal and outputs a control signal according to the quality to a branch metric calculation data obtaining unit. The branch metric calculation data obtaining unit performs logical combination operation between digital multi-value data expressing amplitude of the received signal and the control signal, and thereby, outputs the digital multi-value data directly to a decoding execution unit if the quality of the received signal is lower than a prescribed level, and outputs the digital multi-value data reduced by series each as branch metric calculation data to the decoding execution unit if the quality of the received signal is no less than the prescribed level.

Abstract: The disclosed technology provides systems and methods for identifying potential error locations, patterns, and likelihood metrics in connection with trellis-based detection/decoding. In one aspect of the invention, the disclosed technology detects information that was previously encoded based on a trellis, and decodes the detected information based on the trellis to provide decoded information. The decoded information corresponds to a winning path through the trellis that ends at a winning state. The disclosed technology can identify one or more alternate paths through the trellis that also end at the winning state, and can generate a potential error pattern for each of the alternate paths.

Abstract: The present invention relates to a Viterbi decoder and a Viterbi decoding method in a register exchange method. The Viterbi decoder receives an encoded bit sequence of a convolutional encoding method from a channel, generates an expanded encoded bit sequence by cyclically adding a part of the encoded bit sequence or the entire encoded bit sequence to the encoded bit sequence more than one time, performs a Viterbi decoding operation in a register exchange method, and generates decoded data. In addition, the Viterbi decoder selects an end bit sequence corresponding to the number of the unit of encoded bits among the decoded data, rearranges an order of the end bit sequence, and generates final decoded data.

Abstract: The present invention relates to differential, locally updating Viterbi decoder characterized in that it contains connection management block (802, 810, 812) which enables decoding a bit per cycle by trellis diagram uniting (810) and distributing procedure (812). Furthermore, the invention is also characterized in that it contains a path metric update block, in which the monotonical growth of state metrics is avoided by a bounding procedure in a path metric update (808).

Abstract: Embodiments of the invention provide a decoder arrangement (400), wherein a decoder (420) which is adapted to decode a bitstream which has been encoded with a non-recursive convolutional encoder is used to at least partially perform the decoding of a recursive convolutionally encoded bitstream, with pre- or post-processing (410) of the bitstream being performed to complete the decoding. More particularly, in one embodiment of the invention a recursively encoded bitstream is input into a. conventional decoder (420) which is adapted to decode a non-recursively encoded bitstream. The resulting intermediate output does not represent the correct decoded bitstream, but can then be subject to a post-processing step in the form of a non-recursive encoding operation (410), which effectively completes the decoding operation and provides as its output the correct decoded bitstream. Both hard decision or soft decision inputs can be used.

Abstract: In one embodiment a wireless communication device is provided that: acquires a phase rotation angle in the propagation channel which phase rotation angle is contained in a received symbol and that performs rotation compensation of the acquired phase rotation angle for the received symbol; generates a coordinate value of the respective I, Q axis in the signal constellation on which the information of the respective reference signal point is set; for the respective transmission bit, obtains respective probabilities that the transmission bit is 0 and 1 by making a distance determination of the distance between the received symbol after the rotation compensation and the respective reference signal level on only one of the I and Q axes; and makes a likelihood determination of the bit value of the respective transmission bit in accordance with a probability value obtained.

Abstract: A circular Viterbi decoder is capable of improving a data decoding speed without being limited by a sampling speed of a sampling and holding circuit. An analog Viterbi decoder includes: a clock divider which generates a plurality of clock signals by dividing a clock frequency of an externally-input clock signal, a plurality of sampling and holding units which sample and hold input analog data according to the clock signals generated from the clock divider, and a multiplexer which sequentially and alternately outputs the analog data sampled and held by the sampling and holding units.

Abstract: A method for selecting a signal to noise ratio for a communications code includes obtaining extrinsic information transfer (EXIT) information for a repeat-zigzag Hadamard (RZH) code responsive to a Hadamard order and a signal to noise ratio, determining code parameters for an irregular repeat zigzag Hadamard (IRZH) code for a corresponding code rate in response to the obtained EXIT values, and repeating the step of obtaining the EXIT information for a different signal to noise ratio if the corresponding code rate is other than a selected rate. The corresponding code rate is related to a bit error rate. In a preferred embodiment, the step of obtaining EXIT information includes one of obtaining an EXIT curve for repeat-zigzag Hadamard code by Monte Carlo simulation using serial decoding or obtaining an EXIT function for parallel decoding of the repeat-zigzag Hadamard code by using equations.

Abstract: A MIMO receiver implements a method for the soft bit metric calculation with linear MIMO detection for LDPC codes, after linear matrix inversion MIMO detection. In the receiver, a detector detects the estimated symbol and the noise variance. Further, a soft metric calculation unit computes the distance between the estimated symbol and the constellation point, and then divides the distance by the noise variance to determine the soft bit metrics.

Abstract: A reconfigurable maximum a-posteriori probability (MAP) calculation circuit for decoding binary and duo-binary code. The reconfigurable MAP calculation circuit comprises M memory banks for storing N input data samples. Each input data sample comprises systematic data, non-interleaved parity data and interleaved parity data. The N input data samples are divided into M logical blocks and input data samples from each logical block are stored in each of the M memory banks. The reconfigurable MAP calculation circuit comprises M processing units. Each processing unit processes one of the M logical blocks. The reconfigurable MAP calculation circuit comprises a communication switch for coupling the M processing units to the M memory banks such that the M processing units simultaneously access input data samples from each of the M logical blocks in each of the M memory banks without collision.

Abstract: The disclosed technology provides a less resource intensive way to decode a parity check code using a modified min-sum algorithm. For a particular parity check constraint that includes n variable nodes, an LDPC decoder can compute soft information for one of the variable nodes based on combinations of soft information from other variable nodes, wherein each combination includes soft information from at most a number d of other variable nodes. In one embodiment, soft information from one of the other variable nodes is used in a combination only if it corresponds to a non-most-likely value for the other variable node.

Abstract: A detector includes a Viterbi based detector and an erasure detector that detects as erasures one or more bits associated with a decoding window in which survivor paths do not merge within the decoding window.

Abstract: A system and method for correcting errors in an ECC block using soft-decision data. In an embodiment, a soft-decision ECC decoding method, uses “soft” data indicative of how reliable bits of data are when read out. Such reliability information may be used to identify particular symbols with a higher likelihood of error such that these symbols may be changed in an attempt to reduce the total number of errors in the data. In an embodiment, a soft-decision ECC decoding path may include a reliability checker operable to receive bits of data read from a data store and operable to associate a reliability factor with each bit of data. Then, an update module may iteratively change bits or groups of bits based upon an ordering of the reliability factors.

Abstract: A method and apparatus encode a source data stream via convolutional encoding or selected encoding scheme. Plural encoded data streams are interleaved and transmitted on a transmission channel. Data groups generated via convolutional or selected encoding are interleaved via time-interleaving functions to disperse selected bits within puncture groups of the data groups, bits in between data groups, and bits in selected sets of data groups to facilitate reconstruction of the source data stream from at least a portion of the interleaved data stream received on at least one transmission channel. The time-interleaving functions are selected to facilitate reconstruction of the source data stream from one transmission channel following continuous blockage. Subsets of bits of puncture groups are selected to allow reconstruction of the source data stream from more than one of plural transmission channels using a minimum number of subsets.

Abstract: Embodiments of a method and apparatus for a transceiver decoding an Ethernet signal. The method includes receiving an Ethernet bit stream. The bit stream is at least one of low-complexity decoded by a low-complexity decoder of the transceiver or high-complexity decoded by a high-complexity decoder of the transceiver. If the bit stream fails a low-complexity decoding test, then the bit stream is high-complexity decoded. The low-complexity decoding and high complexity decoding are iteratively repeated until the bit stream passes the low-complexity decoding test.

Abstract: An improved Viterbi detector is disclosed in which each branch metric is calculated based on noise statistics that depend on the signal hypothesis corresponding to the branch. Also disclosed is a method of reducing the complexity of the branch metric calculations by clustering branches corresponding to signals with similar signal-dependent noise statistics. A feature of this architecture is that the branch metrics (and their corresponding square difference operators) are clustered into multiple groups, where all the members of each group draw input from a single, shared noise predictive filter corresponding to the group. In recording technologies as practiced today, physical imperfections in the representation of recorded user data in the recording medium itself are becoming the dominate source of noise in the read back data. This noise is highly dependent on what was (intended to be) written in the medium. The disclosed Viterbi detector exploits this statistical dependence of the noise on the signal.

Abstract: A system for processing a data signal (such as an ADSL or VDSL signal) includes a first decoder unit, such as a convolutional decoder or a QAM decoder, for receiving the data signal, decoding the second level of encoding and outputting a decoded signal and a first error indication signal indicative of errors in the decoded signal. A redundancy decoder employs the decoded signal and the first error indication signal (or transformed versions thereof) to perform redundancy decoding.

Abstract: A DTV transmitter includes a pre-processor which pre-processes enhanced data by coding the enhanced data for forward error correction (FEC) and expanding the FEC-coded enhanced data, a data formatter which generates enhanced data packets having the pre-processed enhanced data and known data, and a multiplexer which multiplexes the enhanced data packets with main data packets. The DTV transmitter further includes an RS encoder which adds systematic parity data to each main data packet and adds RS parity place holders to each enhanced data packet, and a data interleaver which interleaves the RS-coded main and enhanced data packets and outputs a group of interleaved data packets having a head, a body, and a tail. The body includes a plurality of consecutive enhanced data packets, to which a known data sequence is periodically inserted.

Abstract: A quadrature amplitude modulation trellis coded modulation (QAM-TCM) decoding apparatus and the related method that receives and decodes a QAM signal. The QAM-TCM decoding apparatus includes an in-phase least significant bit (LSB) decoding path, which includes a in-phase Viterbi decoder for executing a decoding procedure on at least one LSB corresponding to an in-phase component of the QAM signal, a quadrature-phase LSB decoding path, which includes a quadrature-phase Viterbi decoder for executing a decoding procedure on at least one LSB corresponding to a quadrature-phase component of the QAM signal, and a most significant bit (MSB) decoding path for executing a decoding procedure on MSB portions corresponding to the in-phase or the quadrature-phase of the QAM signal.

Abstract: An input control apparatus capable of suppressing characteristic deterioration, reducing the circuit scale of a turbo decoder and effectively using memory of the turbo decoder. In this apparatus, control section (110) acquires information on a coding rate and coding block length of a received signal, determines the number of bits of systematic part Y1, and parity parts Y2 and Y3 in accordance with the coding rate and/or coding block length and so that the number of bits of one sequence of the parity parts falls below the number of bits of systematic part Y1 and controls bit number reduction section (109) so that the determined number of bits is obtained. Bit number reduction section (109) reduces the number of bits of systematic part Y1, and parity parts Y2 and Y3 output from separation section (108) under the control of control section (110) and decoder (111) performs turbo decoding using each sequence reduced by bit number reduction section (109).

Abstract: A path memory circuit for use in a Viterbi decoding process performed based on state transitions through a number n (n is a positive integer) of states. The path memory circuit includes a memory area A formed by the storage circuits of the first to ith (i is an integer from 0 to M) stages; a memory area B formed by the selective storage circuits that select and hold a decoding result for any state k (k is integer from 1 to n) of the storage circuits from the i+1th stage to the Mth stage; and a memory area C formed by the selective storage circuits other than the memory area A and the memory area B.

Abstract: A plurality of decoding metrics for a current frame may be generated based on a correlation set for a current frame and a correlation set for at least one previous frame. Whether a signal is present on a control channel may then be determined based on the generated decoding metrics.

Abstract: A method for field error checking begins by decoding a predetermined pattern of a field of a frame to produce a decoded pattern. The method continues by determining, for the decoded pattern, a path metric distance of a predetermined state of a plurality of states of the decoding. The method continues by comparing the path metric distance with an excepted path metric distance for the predetermined state. The method continues by indicating a field error when the path metric distance compares unfavorably with the excepted path metric distance.

Abstract: Two levels of error correction decoding are performed using first and second level decoders. A composite code formed by combining an inner component code and an outer component code can be used to decode the data and correct any errors. Performing two level decoding using a composite code allows the size of the inner parity block to be reduced to a single Reed-Solomon symbol while keeping a good code rate. The first level decoder generates soft information. The soft information can indicate a most likely error event for each possible syndrome value of the inner component code. The soft information can also include error metric values for each of the most likely error events. The second level decoder generates corrected syndrome values based on the soft information using the outer component code. The most likely trellis path that corresponds to the corrected syndrome values is then selected.

Abstract: A Viterbi decoding circuit performs Viterbi decoding on the basis of a reproduced signal obtained by reading an optical disc. A decoded bit sequence is fed to a first specific pattern detection circuit and a first reverse pattern detection circuit. A path metric difference ?M is fed to a reproduced signal evaluation circuit. The reproduced signal evaluation circuit extracts path metric differences for a specific pattern and a reverse pattern detected by the first specific pattern detection circuit and the first reverse pattern detection circuit and evaluates the reproduced signal on the basis of results. The evaluation uses not only the bit sequence for which the ideal SAM value is a minimum. The invention achieves accurate evaluation for reproduction.

Abstract: A method and system for recovering useful information, in particular useful information transmitted in digital form on terrestrial or satellite-based information paths, for example as voice, image or data signal, from channel-coded data streams encoded with turbo codes with a predefined code rate is disclosed. The data streams are received by a turbo decoder with a presettable number of decoder components and subsequently decoded in an iterative process according to the MAP and/or Max-Log-MAP standard. The iterative process is controlled by a stop criterion, wherein after termination of the iterative process in the turbo decoder at least one of the decoder components, in particular the associated lattice diagram, is used for an additional decoding process that is different from the MAP and/or Max-Log-MAP standard. This approach lowers the error floor of the turbo code.

Abstract: ACS (Add Compare Select) implementation for radix-4 SOVA (Soft-Output Viterbi Algorithm). Two trellis stages are processed simultaneously and in parallel with one another (e.g., during a single clock cycle) thereby significantly increasing data throughput. During each processing iteration, an ACS module generates a hard decision for each of two trellis stages, as well as a corresponding reliability for each of the two hard decisions. Also, the ACS module is operative to generate the updated state metric for the state at the current trellis stage. Multiple operations are performed simultaneously and in parallel, and control logic circuitry and/or operations employed to select which of the multiple simultaneously-generated resultants is to be employed for each of the hard decisions, reliabilities, and next state metric for the current trellis stage.

Abstract: One embodiment of the present includes a heterogenous, high-performance, scalable processor having at least one W-type sub-processor capable of processing W bits in parallel, W being an integer value, at least one N-type sub-processor capable of processing N bits in parallel, N being an integer value smaller than W by a factor of two. The processor further includes a shared bus coupling the at least one W-type sub-processor and at least one N-type sub-processor and memory shared coupled to the at least one W-type sub-processor and the at least one N-type sub-processor, wherein the W-type sub-processor rearranges memory to accommodate execution of applications allowing for fast operations.

Abstract: A method and system for decoding video, voice, and/or speech data using redundancy and physical constraints are presented. Video, voice, and/or speech bit sequences may be decoded in a multilayer process based on a decoding algorithm and at least one physical constraint. For voice applications, the decoding algorithm may be based on the Viterbi algorithm. At least one estimated bit sequence may be selected by performing searches that start from trellis junctions determined during by the decoding algorithm. The estimated bit sequences may be selected based on corresponding redundancy verification parameters. At least one physical constraint test may be performed on the selected estimated bit sequences to select a decoded output bit sequence.

Abstract: Register exchange network for radix-4 SOVA (Soft-Output Viterbi Algorithm). Two trellis stages are processed simultaneously and in parallel with one another (e.g., during a single clock cycle) thereby significantly increasing data throughput. Any one or more modules within an REX (Register Exchange) module are implemented using a radix-4 architecture to increase data throughput. Any one or more of a SMU (Survivor Memory Unit), a PED (Path Equivalency Detector), and a RMU (Reliability Measure Unit) are implemented in accordance with the principles of radix-4 decoding processing.

Abstract: A method and apparatus are disclosed for improving the maximum data rate of reduced-state Viterbi detectors with local feedback in magnetic recording systems. A read channel signal is processed in a magnetic recording device by precomputing branch metrics, intersymbol interference estimates or intersymbol interference-free signal estimates for speculative sequences of one or more channel symbols; selecting one of the precomputed values based on at least one decision from at least one corresponding state; and selecting a path having a best path metric for a given state.

Abstract: Novel systems and methods are described in which performance of equalizers can be improved by reducing the effects of error propagation in equalizers that use a Viterbi Decoder. Systems and methods of symbol correction in prediction decision feedback equalization architectures are described including systems and methods that include an enhanced Viterbi decoder and novel methods of symbol correction to obtain better system performance. The use of a blending algorithm is described to reduce errors in symbol decoding. Histories of deep trace back depth symbols can be maintained to enable more accurate decisions. Systems and methods described can provide advantage in the feedback path of adaptive equalizers in trellis decoders. The invention provides novel techniques for improving the performance of equalizers by reducing the effects of error propagation in equalizers that use a Viterbi Decoder.

Abstract: Methods, apparatuses, and systems are presented for extracting information from a received signal resulting from a process capable of being represented as a finite state machine having a plurality of states, wherein transitions between the states can be represented by a trellis spanning a plurality of time indices, involving calculating branch metrics taking into account the received signal, calculating state metrics at each time index by taking into account the branch metrics and using a pipelined process, wherein the pipelined process is used to calculate state metrics at a first time index, wherein the pipelined process is then used to calculate state metrics at one or more non-adjacent time indices, and wherein the pipelined process is then used to calculate state metrics at an adjacent time index, and generating at least one output taking into account state metrics for states associated with at least one selected path through the trellis.

Abstract: Various approaches to recover data are described. An one example, an encoded data stream is processed in a first channel decoder producing a channel decoder output. The channel decoder output and the encoded data stream are processed in an error compensation unit to compensate the channel decoder output for low frequency noise and produce an error compensated data stream. The error compensated data stream is processed in a second channel decoder to produce a recovered data stream, wherein the recovered data stream has a reduction in the number of errors as compared to the encoded data stream. Systems to iteratively recover data from an encoded data stream are also described.

Abstract: Outputting information for recovering a sequence of data is disclosed. Outputting includes making a decision that selects a first sequence of states corresponding to a surviving path, determining a second sequence of states corresponding to a non-surviving path associated with the decision, and defining a possible error event based at least in part on the second sequence of states.

Abstract: A bit sequence (b, b?) from QPSK or QAM symbols is decoded, in which an associated receive probability (w, w?) is assigned to each receive bit (b, b?). The receive probability (w, w?) is adaptively determined taking into account the transfer properties of the channel.

Abstract: An apparatus of generating the optimum reference level of a Viterbi decoder for an input signal includes: a first reference level detection unit detecting a first reference level using a delayed input signal from the Viterbi decoder and an output signal of the Viterbi decoder; a second reference level detection unit detecting a second reference level using input signals input after and before one clock cycle with respect to the delayed input signal and the output signal; and a control unit controlling one of the first reference level and the second reference level to be the reference level of the Viterbi decoder by using a result of comparison between a first square level error for the first reference level calculated in the first reference level detection unit and a second square level error for the second reference level calculated in the second reference level detection unit.

Abstract: A decoding apparatus, decoding the LDPC code using a message passing algorithm, sets a message as a log likelihood ratio having, as a base, a real number “a” which is a power of 2, and includes a check node processing calculating unit for receiving a message from a bit node to calculate a message from a check node. The check node processing calculating unit includes a converter for converting an absolute value x of the message to output f (x) and a converting unit supplied as an input y with a sum of the absolute values x of the message from the totality of the bit nodes less one, converted by the converter, subdividing the input y in preset domains and for converting the number in the domain into g (y), and expresses the boundary values of the domains of the input y and f (x) by a power of 2.

Abstract: A-decoding-apparatus includes first-equalization-unit configured to obtain an-equalized-bit-string subjected to hard-decision by equalizing the-input-signal, and to obtain reliability-value-data as soft-decision which is indicating reliability of the-hard-decision with respect to each bit of the-equalized-bit-string, second-equalization-unit configured to obtain a plurality of candidates of the-equalized-bit-string subjected to hard-decision by equalizing the-first-signal, conversion-unit configured to covert the-reliability-value-data corresponding to the-candidates of the-equalized-bit-string, decoding-unit configured to obtain a-bit-string by performing error-correction decoding by using the-converted-reliability-value-date as soft-decision on the-reliability-value-data, determination-unit configured to determine whether the-bit-string obtained by the-decoding-unit contains an-error, and control-unit configured to control the-conversion-unit and the-decoding-unit based on determination-result obtained by t

Abstract: An apparatus and method of reducing power dissipation in a register exchange implementation of a Viterbi decoder used in a digital receiver or mass-storage system without degrading the bit error rate of the decoder, by selectively inhibiting data samples in the Viterbi decoder's register memory from being shifted if the data samples have converged to a single value. FIFO memories keep track of what data samples have converged, the order of the samples, and the converged data value, thereby keeping the decoded data in the FIFO synchronized with data continuing to be shifted through the register memory.

Abstract: Methods and apparatus are provided for determining survivor paths in a Viterbi detector, using a trace-ahead algorithm. A trellis memory is maintained having a depth L that stores L trellis stages, each of the L stages having a plurality, N, of trellis states; and a status memory is maintained for each of the N states of the trellis, wherein each entry in the status memory identifies a least recent trellis state stored in the trellis memory of a survivor path that begins at a given state on a side of the trellis associated with most recent states. A bit sequence of one or more of the survivor paths in the trellis is determined in an order that the bits are received by examining least and most recent trellis stages of the trellis and the status memory. One or fork memories maintain an indicator of whether a given fork is active; a list of active forks; a trellis position of active forks in the trellis; and a fork type of one or more forks in the trellis.

Abstract: A low density parity check (LDPC) code for a belief propagation decoder circuit is disclosed. LDPC code is arranged as a macro matrix (H) representing block columns and block rows of a corresponding parity check matrix (Hpc). Each non-zero entry corresponds to a permutation matrix with a shift corresponding to the position of the permutation matrix entry in the macro matrix. The block columns are grouped, so that only one column in the group contributes to the parity check sum in a row. A parity check value estimate memory is arranged in banks logically connected in various data widths and depths. A parallel adder generates extrinsic estimates for generating new parity check value estimates that are forwarded to bit update circuits for updating of probability values. Parallelism, time-sequencing of ultrawide parity check rows, and pairing of circuitry to handle ultrawide code rows, are also disclosed.

Abstract: A decoder generates distance and label metrics associated with each label of a coset transmitted in a multi-input multi-output communication system having Mt transmit antennas and Mr receive antennas by performing 2(“u+n”)(Mt?1) searches, where n is the number of encoded bits used to identify one of 2u cosets at the transmitting end and u is the number of unencoded bits used to select one of 2u labels at the transmitting end. The decoder forms an intermediate vector quantity associated with one of the transmit antennas to compute the metrics associated with each of the remaining transmit antennas. The decoder then forms a second intermediate vector quantity to compute the metrics associated with the transmit antenna that was used to form the first intermediate variable. The metrics so computed are used by a Viterbi decoder to identify the coset and the most likely transmitted label in that coset.

Abstract: A reconfigurable maximum a-posteriori probability (MAP) calculation circuit that reuses the arithmetic logic unit (ALU) hardware to calculate forward state metrics (alpha values), backward state metrics (beta values), and extrinsic information (lambda values) for the trellis associated with the MAP algorithm. The alpha, beta and lambda calculations may be performed by the same ALU hardware for both binary code (i.e., WCDMA mode) and duo-binary code (i.e, WiBro mode).