Abstract: A decoder includes circuitry and multiple Variable-Node Circuits (VNCs). The VNCs individually hold one or more variables of an Error Correction Code (ECC) that is representable by a plurality of check equations defined over the variables. The circuitry is configured to receive a code word including variables having m-bit values that was encoded using the ECC, to further receive reliability levels assigned respectively to the variables, to decode the code word by applying to the code word a sequence of iterations, including deciding in a given iteration whether a given VNC is to be processed or skipped in that iteration, depending on the reliability levels assigned to the variables of the given VNC, and, when the given VNC is selected for processing, to make a decision whether or not to update one or more of the variables of the given VNC, and to apply the decision by the given VNC.

Abstract: Provided are a data receiving device and a corresponding method for receiving the data. The data receiving device comprises a path control logic configured to store L symbol paths, where L is a natural number equal to or greater than 2, L feedback filters configured to calculate L inter-symbol interferences (ISI) for the L symbol paths, respectively, L operators configured to remove the L inter-symbol interferences from an output of a feed-forward equalizer, and a path metric calculator configured to receive outputs of the L operators and calculate a path metric for each of the L symbol paths, wherein the path control logic is configured to select L values among the calculated path metrics for the L symbol paths to update the L symbol paths.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to determine memory access integrity based on feedback from memory. An example apparatus includes an access reconstruction controller including an output, a first input configured to be coupled to memory, and a second input configured to be coupled to a memory signal generator; a comparator including a first input coupled to the output of the access reconstruction controller, a second input configured to be coupled to an arbiter, and an output configured to be coupled to the arbiter; and a data integrity monitor including an input coupled to the second input of the comparator and configured to be coupled to the arbiter and an output coupled to the output of the comparator and configured to be coupled to the arbiter.

Abstract: There is provided mechanisms for decoding an encoded sequence into a decoded sequence. A method is performed by an information decoder. The method comprises obtaining a channel output. The channel output represents the encoded sequence as passed through a communications channel. The encoded sequence has been encoded using a polar code. The polar code is representable by a code diagram. The method comprises successively decoding the channel output into the decoded sequence by traversing the code diagram. The method comprises, whilst traversing the code diagram, determining a bit score term for each potential decoding decision on one or more bits being decoded. The method comprises, whilst traversing the code diagram, adding an adjustment term to each bit score term to form a candidate score for said each potential decoding decision. The successive decoding is repeated until all bits of the channel output have been decoded, resulting in at least two candidate decoded sequences.

Abstract: A decoding circuit and a decoding method based on the Viterbi algorithm are provided. The decoding method includes the following steps: decoding an encoded data based on the Viterbi algorithm to generate a decoded data; performing error correction on the decoded data to obtain a data content of the encoded data; comparing the decoded data and the data content to generate bit correction information; using the encoded data to calculate multiple first branch metrics based on the Viterbi algorithm, the first branch metrics corresponding to a target bit of the data content; adjusting at least one of the first branch metrics based on the data content and the bit correction information to generate multiple second branch metrics; and selecting the first branch metrics or the second branch metrics based on the bit correction information.

Abstract: This application provides a polar code encoding and decoding method and apparatus and a device. An example method includes: sequentially configuring, by a sending device, information bits and first check bits on subchannels in a first subchannel set, and configuring frozen bits on subchannels in a second subchannel set, where the subchannels in the first subchannel set are sorted according to a natural order of serial numbers of the subchannels; and performing polarization encoding on bits on the subchannels to obtain an encoded sequence. In this way, encoding efficiency and decoding efficiency are improved.

Abstract: A system includes a state-dependent action policy and a state-dependent transition policy. The state-dependent action policy determines an action based on environment states and a current agent state selected from a predetermined group of agent states. The state-dependent transition policy is implemented using one or more machine learning models and is configured to control transitions between agent states from the predetermined group of agent states.

Abstract: Embodiments described herein provide a code generation mechanism (FIG. 3, 301) in a Polar encoder (FIG. 2, 204) to determine a bit type (FIG. 3, 312) corresponding to each coded bit in the Polar code before sending the data bits for encoding (FIG. 3, 303). For example, each bit in the Polar code is determined to have a bit type of a frozen bit, parity bit, an information bit, or a cyclic redundancy check (CRC) bit based at least on the respective reliability index of the bit from a pre-computed reliability index lookup table (FIG. 4A, 411). In this way, the bit type determination can be completed in one loop by iterating the list of entries in the pre-computed reliability index lookup table.

Abstract: An instance node management method is disclosed, which includes: creating a primary instance node for an application hosted on a cloud platform to run an instance of the application; determining, according to running start information of the primary instance node, a minimum resource configuration specification required by a secondary instance node of the application, where the secondary instance node is configured to replace the primary instance node when the primary instance node is faulty; and creating the secondary instance node according to the minimum resource configuration specification. The instance node management method as provided can reduce occupancy of a spare resource and increase an application hosting capability and scale on the cloud platform.

Abstract: A hybrid decoding method and a gigabit Ethernet receiver using the same are provided. The hybrid decoding method and the gigabit Ethernet receiver detect and determine error propagation due to burst interference in a currently used main P-tap parallel decision feedback decoder, decode an Ethernet data stream using a trellis coded modulation (TCM) decoder, and determine a follow-up main decoding algorithm according to the decoded results of the two decoders in the same time interval to effectively prevent error propagation due to burst interference.

Abstract: Embodiments of the present invention provide an encoding/decoding method, apparatus, and system. The present invention is used to improve the decoding performance and improve accuracy of a survivor path. The method includes: encoding information bits to obtain a first-level encoded code word; obtaining a sorting value of each check bit of the first-level encoded code word, and adjusting each check bit to a corresponding position according to the sorting value of each check bit, where the sorting value refers to a value of S when the check bit is related to first S information bits of the information bits in the first-level encoded code word, and S is a non-zero integer; and performing second-level encoding on the first-level encoded code word after positions of the check bits are adjusted, thereby obtaining a second-level encoded code word. The present invention is applicable to various communication systems.

Abstract: Calculating path metrics, associated with respective states of an n-state trellis, by accumulating branch metrics in a sequence detector. Each path metric is represented by N bits plus a wrap-around bit for indicating wrap-around of the N-bit value of that path metric.

Abstract: The present invention is related to systems and methods for branch metric calculation based on multiple data streams in a data processing circuit.

Abstract: Devices, systems, methods, and other embodiments associated with generating a moving average are described. In one embodiment, a method includes inputting a new data value, wherein the new data value is a most recent data value in a series of M prior sequential data values that are input to an accumulator for the purpose of calculating a moving average having a window size of M. The method also includes detecting an error in the new data value and correcting the moving average, based at least in part, on the error.

Abstract: The present invention relates to a method for equalizing modulation symbols transmitted on a non-linear transmission channel. The equalizing method operates on a sequence of observables, each non-linearly depending on a predetermined number of consecutive modulation symbols, and is based on a Viterbi algorithm. It comprises a prior step of receiving a pilot sequence of modulation symbols and storing corresponding observables (110), said pilot sequence leading to a path passing through all the branches of the lattice. In a second step (120), for each symbol to be equalized, for each branch, a branch metric is calculated as a distance between the observable corresponding to the modulation symbol to be equalized and the observable stored for said branch.

Abstract: A channel decoder includes a demodulator, a filter, a detector module, and first and second circuits. The demodulator receives an input signal based on data read from a storage medium, and demodulates the input signal to generate a data signal. The filter generates equalized data based on the data signal. The detector module executes a Viterbi algorithm based on the equalized data to generate estimates of data originally stored in the storage medium, and based on the execution of the Viterbi algorithm, generates a first and second sets of depths. The first set of depths includes depths larger than depths in the second set of depths. The first circuit generates a first error signal based on the first set of depths. The second circuit generates a second error signal based on the second set of depths. The filter generates the equalized data based on the first and second error signals.

Abstract: Certain aspects of the present disclosure relate to techniques for generating likely demodulation candidates using Vector Candidate Sampling (VCS). VCS is used to generate high likelihood candidates for Multiple Input Multiple Output (MIMO) demodulation that approaches optimal maximum a posteriori (MAP) performance with reasonable complexity. A receive data vector is recorded corresponding to a signal received at a MIMO receiver. A plurality of likely candidates are determined for MIMO demodulation via VCS, based at least on the receive data vector. Determining the likely candidates may include perturbing the receive data vector for each candidate based on a pre-determined perturb vector, and estimating a corresponding transmit data vector based at least on the perturbed receive data vector for the candidate and an estimator matrix, wherein the likely candidate comprises the estimated data vector.

Abstract: In one embodiment, systems and methods of operating a SOVA system is disclosed that comprises determining the start and stop values for a trellis tree and using the start and stop values to determine the initial states of a plurality of branches within the trellis tree.

Abstract: A receiver system and method for recovering information from a symbol data sequence Y. The symbol data sequence Y corresponds to a symbol data sequence X that is transmitted onto the channel by a transmitter. The symbol data sequence X is generated by the transmitter based on associated information bits. At the receiver, a set of two or more processors operate in parallel on two or more overlapping subsequences of the symbol data sequence Y, where each of the two or more overlapping subsequences of the symbol data sequence Y corresponds to a respective portion of a trellis. The trellis describes redundancy in the symbol data sequence Y. The action of operating in parallel generates soft estimates for the associated information bits. The soft estimates are useable to form a receive message corresponding to the associated information bits.

Abstract: The error correcting decoding device of the present invention performs Low-Density Parity-Check (LDPC) decoding which accommodates a plurality of code rates while sharing circuits to suppress increase in circuit scale. If the set code rate is a second code rate which is a higher code rate than a first code rate, a column processing and row processing calculating unit (120A) uses a distributed submatrix in which a number of columns are selected and combined, wherein the number of columns is equal in number to the number of columns with which a first submatrix is constructed from a distributed check matrix corresponding to a second check matrix which accommodates the second code rate. At this time, the column processing and row processing calculating unit (120A) uses a distributed submatrix such that the row degree is less than or equal to the row degree of the first submatrix.

Abstract: A method and system for a sequence estimation in a receiver, such as for use when receiving a sample of a received inter-symbol correlated (ISC) signal corresponding to a transmitted vector of L symbols, with L being a integer greater than 1, and with symbol L being a most-recent symbol and symbol 1 being least recent symbol of the vector. A plurality of candidate vectors may be generated, wherein element L?m of each candidate vector holding one of a plurality of possible values of the symbol L?m, with m is an integer greater than or equal to 1, and elements L?m+1 through L of each candidate vectors holding determined filler values. A plurality of metrics may be generated based on the plurality of candidate vectors, and based on the generated plurality of metrics, a best one of the possible values of the symbol L?m may be selected.

Abstract: Techniques for wireless access point mapping are described. In at least some embodiments, various characteristics of a wireless access point are detected. Examples of such characteristics include signal strength for wireless signal transmitted by the wireless access point, identifying information for the wireless access point, data error rates for data transmitted by the wireless access point, and so forth. Characteristics of a wireless access point can be detected at multiple different geographic locations to enable a reception range mapping to be generated for the wireless access point, e.g., for an area in which signal reception for the wireless access point is qualitatively acceptable.

Abstract: Various embodiments of the present invention provide systems and methods for media defect detection. For example, a media defect detection systems is disclosed that includes a data input derived from a medium, a fast envelope calculation circuit that receives the data input and provides a fast decay envelope value based on the data input, a slow envelope calculation circuit that receives the data input and provides a slow decay envelope value based on the data input, and a media defect detection circuit. The media defect detection circuit receives the slow decay envelope value and the fast decay envelope value, calculates a ratio value of the fast decay envelope value to the slow decay envelope value, and asserts a defect output based at least in part on the comparison of the ratio value to a defect threshold value.

Abstract: A codeword that is associated with one uncorrected codeword in a set of first codewords is selected from a set of third codewords. Error correction decoding is performed on the selected codeword using a third, systematic error correction code.

Abstract: Systems and methods for transferring data over a 2-pair communication system. Two input data streams are received at a Viterbi detector. The two input data streams are converted into an output signal at the Viterbi detector. Each of the input data streams includes a first data symbol interleaved with a second data symbol. A first set of branch metric values is computed for the first data symbols of the two input data streams. A second set of branch metric values is computed for the second data symbols of the two input data streams, where the computing of the second set is based on the first set. Each of the two input data streams is de-interleaved and downsampled to generate the output signal, where the output signal includes four channels of data generated based on the first and second sets of branch metric values. Each of the four channels is of a lower data rate than each of the two input data streams.

Abstract: A mechanism is provided for effectively validating cache coherency within a processor. For each node in a set of nodes, responsive to a node in a set of nodes being a controlling node, at least one action is performed on each controlled node mapped to the controlling node. After performing the at least one action on each controlled node mapped to the controlling node or responsive to the node failing to be a controlling node, a self-modifying branch test pattern is executed based on the selected execution pattern in the condition register through the set of nodes. Responsive to the self-modifying branch test pattern ending, values output from the execution unit during execution of the self-modifying branch test pattern are compared to a set of expected results. Responsive to a match of the comparison for the execution patterns in the set of execution patterns, the execution unit is validated.

Abstract: A state metric calculator for calculating state metrics of stages in a trellis of a sequence estimation technique is described. The calculator has a processing path containing operations needed for calculating a state metric of a trellis stage from state metrics of an earlier trellis stage. One or more data stores are located in the processing path to divide the path into separate sections. The sections can then operate on the production of different state metrics to one another in, if desired, the same clock cycle.

Abstract: A method, implementable on a multiple-input, multiple-output symbol receiver, includes selecting a hypothesis for a second symbol value U2 from among the set of fixed constellation points, calculating a hypothesis for a first symbol value U1 from the resultant selected U2 value, and generating a first half of counter-hypotheses from interim results of calculating the hypotheses values.

Abstract: An iterative decoder for decoding a code block comprises a computation unit configured to perform forward and backward recursions over a code block or a code sub-block in each decoding iteration. A first forward/backward decoding scheme is used in a first iteration and a second forward/backward decoding scheme is used in a second iteration. The first and second decoding schemes are different in view of forward and backward processing.

Abstract: The present invention is a minimum cut set calculation system for calculating minimum cut sets of a fault tree with binary decision diagram (BDD), comprising: subtracting means for, from one of two sub-BDDs of an input BDD, removing redundant paths included in the other sub-BDD using a recursive function comprised of a recursive case and a base case, wherein said subtracting means comprises equivalence removing means for, when said two sub-BDDs are equivalent, outputting a terminal node 0 in said base case.

Abstract: A communication system includes: a module configured to decode a remainder portion of a receiver message using a mechanism with a compensation channel value calculated from decoding an evaluation portion of the receiver message with a different mechanism, or using a mechanism-controller generated using a mismatch characterization based on determining a partial-sensitive output and a partial-insensitive output, or a combination thereof for communicating with a device.

Abstract: A mechanism is provided for effectively validating execution units within a processor. A branch test pattern is generated for execution by an execution unit that is under validation testing. An execution pattern is selected from a set of execution patterns thereby forming a selected execution pattern. The selected execution pattern is loaded into a condition register. The branch test pattern is executed by an execution unit based on the selected execution pattern in the condition register. Responsive to the branch test pattern ending, values output from the execution unit during execution of the branch test pattern are compared to a set of expected results. Responsive to a match of the comparison, the process is repeated for each execution pattern in the set of execution patterns. Responsive to a match of the comparison for the execution patterns in the set of execution patterns, the execution unit is validated.

Abstract: A signal detector/decoder is implemented in multiple stages. The beginning stage is configured to input channel data bits and to output hard data bits based on the channel bits and a maximum likelihood (ML) path. The next stage includes a postcoder coupled to receive channel domain information from the first stage and to convert the channel domain information to user domain information. The final stage includes a reliability unit coupled to receive the user domain information from the postcoder and to output user domain soft information for the hard data bits based on the ML path estimation and the user domain information.

Abstract: An apparatus may include a channel estimation component to determine a channel estimation matrix H for a tone of a multiplicity of tones in a multiple input multiple output (MIMO) communications signal. The apparatus may further include a processor circuit coupled to the receiver component, and a flow selection component for execution on the processor circuit to calculate a figure of merit for power loss for the received tone based upon the channel estimation matrix, and based upon the calculated figure of merit, perform either a max-log calculation or a maximum likelihood calculation to determine a received signal metric, but not both calculations. Other embodiments are described and claimed.

Abstract: A communication device includes a turbo encoding section including a plurality of component encoders, wherein the plurality of component encoders within the turbo encoding section use different constraint lengths.

Abstract: Various embodiments of the present invention provide systems and methods for media defect detection. For example, a media defect detection systems is disclosed that includes a data input derived from a medium, a fast envelope calculation circuit that receives the data input and provides a fast decay envelope value based on the data input, a slow envelope calculation circuit that receives the data input and provides a slow decay envelope value based on the data input, and a media defect detection circuit. The media defect detection circuit receives the slow decay envelope value and the fast decay envelope value, calculates a ratio value of the fast decay envelope value to the slow decay envelope value, and asserts a defect output based at least in part on the comparison of the ratio value to a defect threshold value.

Abstract: A method for estimating a scrambling code used on an uplink of a WCDMA system. The scrambling code is obtained from a Gold code, sum of a first specific M-sequence of the user and of a second M-sequence known from the receiver. After sampling of the signal received at the chip frequency of the scrambling code, the successive samples are subject to a differential treatment and the sequence of differential values is multiplied by the second M-sequence. The observables thereby obtained are decoded with the aid of a belief propagation iterative decoding. The decoded values then serve to determine the content of the shift register of the generator of the first M-sequence. One then deduces therefrom the Gold code and an estimation of the scrambling code, ?.

Abstract: Provided is a receiver for processing VSB signal. The receiver includes a first equalizer/decoder unit and a second equalizer/decoder unit. The first equalizer/decoder unit performs a first equalizing operation, first TCM decoding and first RS decoding on a received symbol to output a first dibit. The second equalizer/decoder unit performs a second equalizing operation, second TCM decoding and second RS decoding on the received symbol to output a transport stream. The first dibit is provided as a priori information for a soft-decision operation of the second TCM decoding.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit having a data detection circuit is disclosed that includes: a scaling circuit, a soft output calculation circuit, and a factor calculation circuit. The scaling circuit is operable to scale a branch metric value by a scaling factor to yield a scaled output. The soft output calculation circuit is operable to calculate a soft output based at least in part on the scaled output. The factor calculation circuit operable to modify the scaling factor based at least in part on the soft output.

Abstract: A mechanism is provided for effectively validating execution units within a processor. A branch test pattern is generated for execution by an execution unit that is under validation testing. An execution pattern is selected from a set of execution patterns thereby forming a selected execution pattern. The selected execution pattern is loaded into a condition register. The branch test pattern is executed by an execution unit based on the selected execution pattern in the condition register. Responsive to the branch test pattern ending, values output from the execution unit during execution of the branch test pattern are compared to a set of expected results. Responsive to a match of the comparison, the process is repeated for each execution pattern in the set of execution patterns. Responsive to a match of the comparison for the execution patterns in the set of execution patterns, the execution unit is validated.

Abstract: The present invention is related to systems and methods for adaptive parameter modification in a data processing system.

Abstract: The present inventions are related to systems and methods for information divergence based data processing. As an example, a system is disclosed that includes a scheduling circuit operable to calculate a first quality metric using a first information divergence value calculated based at least in part on the first detected output, and to calculate a second quality metric using a second information divergence value calculated based at least in part on the second detected output. A decoder input is selected based at least in part on the first quality metric and the second quality metric.

Abstract: Methods, system and apparatuses for carrier frequency offset estimation are disclosed. The method includes: receiving a preamble sequence rn with a correlator and correlating the preamble sequence with a locally stored Barker code bn to obtain a correlation result cn; extracting peak values from every L points in cn to form a peak value sequence xn, L being a length of a Barker code that corresponds to the sampling rate; performing frequency offset estimation to xn by using at least two frequency offset estimation apparatuses, the at least two frequency offset estimation apparatuses adopting different delay parameters D; and inputting the results output from the at least two frequency offset estimation apparatuses into a frequency offset combination module to calculate a final carrier frequency offset estimate, whereby accurate frequency estimation can be achieved and an appropriate acquisition range of frequency offset can be ensured.

Abstract: One aspect provides a method. The method comprises receiving a signal comprising a sequence of encoded symbols, each corresponding to one of a plurality of possible states. For each symbol in the sequence, the method further comprises determining a set of state metrics, each representing a probability that the respective symbol corresponds to the plurality of states. The method further comprises decoding the signal by processing runs of recursions using runs of forward recursions, whereby a later state metric in the sequence is updated based on a preceding state metric, and runs of recursions using runs of reverse recursions, whereby a preceding state metric in the sequence is updated based on a later state metric. The method further comprises outputting the decoded signal to a device. The decoding comprises performing a plurality of repeated iterations over the sequence.

Abstract: Methods and devices are disclosed for encoding and decoding convolutional codes in a communication system. In various embodiments of the disclosure, a codeword comprises message data and parity data. A convolutional codeword is generated by multiplying the message data and the parity data with a convolutional polynomial. The convolutional codeword may be decoded by a convolutional code decoder that uses the convolutional polynomial and a maximum likelihood divisor to obtain a maximum likelihood message from the convolutional codeword.

Abstract: The invention disclosed in this application describes a diversity combiner that operates as a maximal ratio combiner (MRC) when no interference is detected and as a selection combiner when Orthogonal Frequency Division Multiplexing symbol errors are detected with high probability by using a symbol error detection method based on computing a symbol by symbol path error metric.

Abstract: A method for forward error correction decoding. The method generally includes steps (A) to (D). Step (A) may calculate a plurality of metrics of a codeword using a forward error correction process on a trellis having a plurality of stages. Step (B) may update the metrics over each of the stages. Step (C) may permute the metrics in each of the stages. Step (D) may generate a signal carrying a plurality of decoded bits of the codeword.

Abstract: A method of operation of a communication system includes: utilizing an estimation module estimating a log-likelihood ratio for a transmission; and utilizing a slicing module, coupled to the estimation module, slicing a constellation by: reading the log-likelihood ratio from the estimation module, defining a threshold within the constellation, and adjusting the threshold based on the log-likelihood ratio for determining a symbol.

Abstract: The present disclosure presents methods and apparatuses for enhanced received signal processing using signal-based channel impulse response (CIR) estimation. For example, according to an example method presented herein, a user equipment (UE) or a component therein may receive a signal corresponding to a transmitted signal sent by a network entity, wherein the transmitted signal comprises at least a data channel, estimate chip contents of the transmitted signal, based on the received signal including the data channel, to obtain estimated chip contents, and compute an estimated channel impulse response (CIR) based on at least the estimated chip contents. Based on this estimated CIR, the UE may thereafter reprogram a received signal reconstruction filter, perform interference cancellation procedures, and/or adjust one or more equalizer taps. By performing such functions, the UE may exhibit improved communication characteristics and enable a more robust user experience.

Abstract: Log-likelihood ratios produced by a decoder are incorporated into a soft symbol to soft bit estimation process and are used to perform improved channel estimation and impairment covariance estimation. In an example method, a plurality of soft bits and corresponding probability metrics for a series of received unknown symbols are generated. Estimates of the received unknown information symbols are then regenerated, as a function of the soft bits and corresponding probability metrics. An estimate of the average amplitude of the received unknown information symbols, or an estimate of the propagation channel response experienced by the received unknown information symbols, or both, are calculated, as a function of the regenerated symbol estimates. The results are applied to produce demodulated symbols for a second decoding iteration for the series of received unknown symbols.