Parity Bit Patents (Class 714/800)
  • Patent number: 11916572
    Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 7/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: February 27, 2024
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Heung-Mook Kim, Sun-Hyoung Kwon, Nam-Ho Hur
  • Patent number: 11881871
    Abstract: Decoding method and memory system that decodes data and estimates a weighted checksum on the decoded data to determine whether the decoding is successful. The weighted checksum is calculated based on a first group and a second group, the first group is associated with weights for high degree nodes of an irregular parity check matrix, and the second group is associated with weights for low degree nodes of the irregular parity check matrix.
    Type: Grant
    Filed: September 14, 2022
    Date of Patent: January 23, 2024
    Assignee: SK hynix Inc.
    Inventors: Fan Zhang, Haobo Wang, Meysam Asadi
  • Patent number: 11818082
    Abstract: Disclosed are systems, methods, and non-transitory computer-readable media for a hybrid physical layer that supports data communications using both Ethernet and ASA. Ethernet and ASA are communication standards that are commonly used in automotive environments; however, are not interoperable. The hybrid physical layer supports data communications using both Ethernet and ASA. For example, the hybrid physical layer may be configured into either a first mode of operation to support data communications using Ethernet or a second mode of operation to support data communications using ASA. Devices utilizing the hybrid physical layer can therefore be used with other components that utilize either communication standard.
    Type: Grant
    Filed: December 16, 2022
    Date of Patent: November 14, 2023
    Assignee: Ethernovia Inc.
    Inventors: Hossein Sedarat, Christopher Mash, Darren S. Engelkemier, Ramin Shirani, Roy T. Myers, Jr.
  • Patent number: 11799611
    Abstract: Methods, systems, and devices for wireless communication are described. A wireless device may transmit feedback, such as hybrid automatic repeat request (HARD) feedback for groups of code blocks rather than for an entire transport block or individual code blocks. The wireless device may transmit an acknowledgement (ACK) or negative-acknowledgement (NACK) to provide feedback for each code block group of a set of code block groups. An ACK may indicate that code blocks in a code block group were successfully decoded, and a NACK may indicate that at least one code block in a code block group was not successfully decoded. Wireless devices may support several techniques for grouping code blocks for feedback reporting to allow for efficient retransmissions and limited overhead. Different grouping schemes may be employed depending on system constraints, device capability, link conditions, or the like.
    Type: Grant
    Filed: November 8, 2021
    Date of Patent: October 24, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Jay Kumar Sundararajan, Renqiu Wang, Hao Xu, Naga Bhushan, Haitong Sun, Wanshi Chen
  • Patent number: 11750220
    Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). An apparatus and a method for channel encoding and decoding in a communication or broadcasting system is provided. According to the present disclosure, the method for channel encoding in a communication or broadcasting system includes determining a block size Z, and performing encoding based on the block size and a parity check matrix corresponding to the block size, in which the block size is included in any one of the plurality of block size groups and the parity check matrix is different for each block size group.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: September 5, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seho Myung, Kyungjoong Kim, Seokki Ahn, Min Jang, Hongsil Jeong
  • Patent number: 11711096
    Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 3/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: July 25, 2023
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Heung-Mook Kim, Sun-Hyoung Kwon, Nam-Ho Hur
  • Patent number: 11539456
    Abstract: Certain aspects of the present disclosure generally relate to wireless communications and, more particularly, to methods and apparatus for rate-matching a stream of bits encoded using polar codes.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: December 27, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Changlong Xu, Kai Chen, Jing Jiang, Gabi Sarkis, Hao Xu
  • Patent number: 11533127
    Abstract: Determining data availability is disclosed, including: performing a data availability challenge with respect to a claimer node to determine whether the claimer node stores at least some elements included in a base layer in a digital tree corresponding to a data entity; and publishing a first set of elements associated with the base layer of the digital tree and the data availability challenge. Furthermore, encoding auditing is disclosed, including: obtaining a first set of elements associated with a base layer of a digital tree corresponding to a data entity; and generating an encoding validity determination of the digital tree based at least in part on whether the first set of elements is usable to recover a second set of elements associated with the base layer of the digital tree.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: December 20, 2022
    Assignee: Kaleidoscope Blockchain, Inc.
    Inventors: Mingchao Yu, Sreeram Kannan, Pramod Viswanath, Songze Li, Amir Salman Avestimehr
  • Patent number: 11507671
    Abstract: An example process includes: identifying, by one or more processing devices, candidate code in executable code based on a static analysis of the executable code, where the candidate code includes code that is vulnerable to attack or the candidate code being on a path to code that is vulnerable to attack, where information related to the attack is based, at least in part, on the candidate code; customizing, by one or more processing devices, a healing template based on the information to produce a customized healing template; and inserting, by one or more processing devices, the customized healing template into a version of the executable code at a location that is based on a location of the candidate code in the executable code, where the customized healing template includes code that is executable to inhibit the attack.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: November 22, 2022
    Assignee: BLUERISC, INC.
    Inventors: Csaba Andras Moritz, Kristopher Carver, Jeffry Gummeson
  • Patent number: 11451243
    Abstract: Disclosed are a communication scheme and a system thereof for converging IoT technology and a 5G communication system for supporting a high data transmission rate beyond that of a 4G system. The disclosure can be applied to intelligent services (for example, services related to a smart home, smart building, smart city, smart car, connected car, health care, digital education, retail business, security, and safety) based on the 5G communication technology and the IoT-related technology. A decoding method includes: performing decoding through an inner code; detecting an error through an outer code; determining a re-encoding method; and performing re-encoding. A method for processing a signal includes decoding a first layer signal to determine first LDPC information bits, encoding the first LDPC information bits and a first parity bits to determine second parity bits; identifying a part of the first LDPC information bits, and decoding a second layer signal.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: September 20, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seho Myung, Min Jang, Yangsoo Kwon, Hoondong Noh
  • Patent number: 11411584
    Abstract: A data storage device is disclosed comprising a non-volatile storage medium (NVSM). A first block of data is channel encoded into first channel data based on a channel code constraint, and the first channel data is error correction encoded to generate first redundancy bits. A second block of data is channel encoded into second channel data based on the channel code constraint and the first redundancy bits, and the first channel data and the second channel data are error correction encode to generate second redundancy bits. A third block of data is channel encoded into third channel data based on the channel code constraint and the second redundancy bits. The first, second and third channel data and the first and second redundancy bits are stored in the NVSM.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: August 9, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Iouri Oboukhov, Richard L. Galbraith, Niranjay Ravindran
  • Patent number: 11372714
    Abstract: A method and a hardware accelerator device are provided for performing erasure coding on the hardware accelerator device that includes a dedicated buffer memory that is resident on the hardware accelerator device and that is connected to a second device via a bus, the method includes receiving, at the dedicated buffer memory, write data directly from the second device via the bus such that receiving the data at the dedicated buffer memory bypasses a buffer memory connected to a central processing unit (CPU), performing, at the hardware accelerator, an erasure coding operation on the write data received at the dedicated buffer memory to generate parity data based on the received write data, transmitting the parity data directly to a storage device connected to the hardware accelerator device via the bus such that transmitting the parity data bypasses the buffer memory connected to the CPU.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: June 28, 2022
    Assignee: EIDETIC COMMUNICATIONS INC.
    Inventors: Stephen Bates, Saeed Fouladi Fard
  • Patent number: 11314587
    Abstract: A method of correcting one or more bit errors in a memory device includes retrieving a codeword from a memory device. The codeword includes a data and an error correcting code. The method further includes determining whether the one or more bit errors are present in the retrieved codeword and correcting the retrieved codeword for the one bit error in response to determining one bit error is present in the retrieved codeword. The method also includes flipping a bit of the retrieved codeword in response to determining a plurality of bit errors is present in the retrieved codeword and correcting the retrieved codeword for the plurality of bit errors based on the bit-flipped codeword.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: April 26, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Shih-Lien Linus Lu
  • Patent number: 11309916
    Abstract: Disclosed are devices, systems and methods for error correction encoding and decoding. A memory controller includes an error correction encoder for generating a codeword by performing error correction encoding, using a parity check matrix including a plurality of sub-matrices; and an error correction decoder for performing error correction decoding on a read vector corresponding to the codeword on a column layer basis while sequentially selecting column layers of the parity check matrix used for the error correction encoding, in the error correction decoding, the column layer including a set of columns of the parity check matrix. Rows included in the parity check matrix are grouped into a plurality of row groups, and at most one cyclic permutation matrix (CPM) is included for each column layer in each of the row groups.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: April 19, 2022
    Assignee: SK hynix Inc.
    Inventors: Dae Sung Kim, Jang Seob Kim
  • Patent number: 11295794
    Abstract: According to one embodiment, a memory system includes a plurality of memory packages, on-die termination (ODT) circuits, and a controller. The plurality of memory packages are coupled by a common bus and arranged in groups, each group includes a pair of memory packages facing each other, and each memory package includes a plurality of memory chips. The ODT circuits are respectively disposed in the memory packages. The ODT circuits are on/off controlled based on an asserted state of a chip enable signal CEn acquired using a periodic signal of at least two cycles.
    Type: Grant
    Filed: February 9, 2021
    Date of Patent: April 5, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Kiyotaro Itagaki
  • Patent number: 11265014
    Abstract: Certain aspects of the present disclosure provide an efficiently decodable QC-LDPC code which is based on a base matrix, the base matrix being formed by columns and rows, the columns being dividable into one or more columns corresponding to punctured variable nodes and columns corresponding to non-punctured variable nodes. Apparatus at a transmitting side includes a encoder configured to encode a sequence of information bits based on the base matrix. Apparatus at a receiving side configured to receive a codeword in accordance with a radio technology across a wireless channel. The apparatus at the receiving side includes a decoder configured to decode the codeword based on the base matrix.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: March 1, 2022
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Yurii Sergeevich Shutkin, Pavel Anatolyevich Panteleev, Aleksey Alexandrovich Letunovskiy, Elyar Eldarovich Gasanov, Gleb Vyacheslavovich Kalachev, Ivan Leonidovich Mazurenko
  • Patent number: 11133825
    Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). An apparatus and a method for channel encoding and decoding in a communication or broadcasting system is provided. According to the present disclosure, the method for channel encoding in a communication or broadcasting system includes determining a block size Z, and performing encoding based on the block size and a parity check matrix corresponding to the block size, in which the block size is included in any one of the plurality of block size groups and the parity check matrix is different for each block size group.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: September 28, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seho Myung, Kyungjoong Kim, Seokki Ahn, Min Jang, Hongsil Jeong
  • Patent number: 11108410
    Abstract: A decoder circuit includes a low-density parity-check (LDPC) repository, an LDPC code configurator, and LDPC decoding circuitry. The LDPC repository stores parity-check information associated with one or more LDPC codes. The LDPC code configurator may receive a first LDPC configuration describing a parity-check matrix for a first LDPC code and may update the parity-check information in the LDPC repository to reflect the parity-check matrix for the first LDPC code. The LDPC decoding circuitry may receive a first codeword encoded in accordance with the LDPC code. More specifically, the LDPC decoding circuitry may be configured to read the parity-check information associated with the first LDPC code from the LDPC repository and iteratively decode the first codeword using the parity-check information associated with the first LDPC code.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: August 31, 2021
    Assignee: Xilinx, Inc.
    Inventors: Richard L. Walke, Christopher H. Dick, Nihat E. Tunali
  • Patent number: 11074083
    Abstract: Example methods and apparatus for fast loading a kernel image file are provided. A multi-core processor includes a first core group and a second core group. The second core group includes a plurality of cores. In one example method, the first core group obtains a plurality of data blocks in a compressed kernel image file from a nonvolatile storage, and checks the currently obtained current data block. The current data block is put into a decompression queue in response to determining that the data block is correct. At least two of the plurality of cores in the second core group obtain the data block from the decompression queue, and after obtaining a plurality of data blocks, decompress the plurality of obtained data blocks into a memory in parallel to obtain the kernel image file.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: July 27, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventor: Huifeng Hu
  • Patent number: 10990479
    Abstract: An apparatus comprises at least one processing device comprising a processor coupled to a memory. The processing device is configured to select a stripe column size for stripes of a data storage system, to determine a first compress block size for a first one of the stripes based on compressibility of data to be stored, to select a first prime number for computing parity blocks for the first stripe and a first number of sub-stripes for splitting stripe columns of the first stripe, to generate metadata specifying the first compress block size, the first prime number and the first number of sub-stripes for the first stripe, and to store data compressed using the first compress block size in the first stripe. The first prime number and first number of sub-stripes for the first stripe is different than a second prime number and second number of sub-stripes for a second stripe.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: April 27, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Zvi Schneider, Marcelo Taube, Lior Kamran, Alex Soukhman, David Krakov
  • Patent number: 10901837
    Abstract: The present disclosure includes apparatuses and methods for ECC operation associated with memory. One example apparatus comprises a controller configured to perform an error correction code (ECC) operation on a codeword stored in the memory, wherein the codeword includes a first number of ECC bits and the first number of ECC bits are generated based on an encoding matrix, wherein each row of the encoding matrix has an odd number of bits having a binary value of 1.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: January 26, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Gerard A. Kreifels
  • Patent number: 10887067
    Abstract: A coding scheme determining method and apparatus are provided. In various embodiments, a base station device sends, to a terminal device, higher layer control signaling, physical layer control signaling, or a synchronization signal that carries coding scheme indication information. In some embodiments, a terminal device sends, to a base station device, a capability information report message that carries coding scheme indication information, so that the base station device or the terminal device can clearly and flexibly indicate a coding scheme. At least one information block size IBS greater than or equal to a preset first specified value X is determined, and an IBS is selected from the at least one IBS to code an information block of bits or a code block of the information block of bits. X and a coding scheme are determined by a scenario, information type, and/or service type.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: January 5, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Yong Xie, Jun Chen, Yalin Liu, Rongdao Yu, Yinggang Du
  • Patent number: 10885969
    Abstract: Disclosed herein is a semiconductor device that includes an access control circuit generating an internal command based on a verification result signal and an external command. The external command indicates at least one of a first command that enables the access control circuit to access a first circuit and a second command that enables the access control circuit not to access the first circuit or enables the access control circuit to maintain a current state of the first circuit. The access control circuit, when the verification result signal indicates a first logic level, generates the internal command based on the external command. The access control circuit, when the verification result signal indicates a second logic level, generates the internal command that corresponds to a second command even if the external command indicates a first command.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: January 5, 2021
    Assignee: LONGITUDE LICENSING LIMITED
    Inventor: Chikara Kondo
  • Patent number: 10877837
    Abstract: Disclosed is a method for automatically recovering data of an electronically erasable programmable read only memory (EEPROM) storing configuration information of a slave device by a programmable logic controller (PLC) communication module using an EtherCAT network when the data of the EEPROM is modified or incorrect.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: December 29, 2020
    Assignee: LSIS CO., LTD.
    Inventor: Hyung-Lae Kim
  • Patent number: 10879929
    Abstract: The invention relates to the field of decoders, more specifically, to a decoding method of LDPC (Low Density Parity Check Code). The decoding method comprising: in the rwsr (Row-Wise Scanning Round) phase, the recovery circuit reads a plurality of sign bits, the absolute value of a minimum value, the absolute value of a second smallest value and the absolute value of a third smallest value which are stored previously, and they are output by a comparison and a selector, the output of the comparator and selector is shifted, and then is combined with each sign bit to obtain an update message of the previous check node, the update message is subtracted from the posterior probability by the addition circuit to obtain an input of the update unit.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: December 29, 2020
    Assignee: AMLOGIC (SHANGHAI) CO., LTD
    Inventors: Xiaotong Liu, Xiao Zhang
  • Patent number: 10860422
    Abstract: A method for performing data management in a memory device includes: receiving a set of data from a host device positioned outside the memory device; encoding the set of data according to a first sub-matrix of a predetermined parity-check matrix to generate a partial parity-check code; performing post-processing upon the partial parity-check code according to a predetermined post-processing matrix to generate a parity-check code of the set of data, where the predetermined post-processing matrix is not equivalent to any inverse matrix of a transpose matrix of a second sub-matrix of the predetermined parity-check matrix; and writing/programming a codeword of the set of data into a non-volatile memory of the memory device to allow the memory device to perform error correction when reading the set of data from the non-volatile memory. An associated memory device and a controller thereof are also provided.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: December 8, 2020
    Assignee: Silicon Motion, Inc.
    Inventor: Yu-Luen Wang
  • Patent number: 10839931
    Abstract: The present disclosure relates to a structure which includes a memory which is configured to enable zero test time built-in self-test (BIST) at a read/write port while concurrently performing at least one functional read operation at a read port.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: November 17, 2020
    Assignee: MARVELL ASIA PTE, LTD.
    Inventors: Igor Arsovski, Eric D. Hunt-Schroeder, Michael A. Ziegerhofer
  • Patent number: 10833792
    Abstract: An overlapped multiplexing-based modulation and demodulation method and device are disclosed. In the modulation method, a precoding structure is used, and a transmit end first performs parity check product code-based coding on an input information sequence, generates a factor graph for a coding result and according to a coding rule, then performs overlapped multiplexing-based modulation and coding, and transmits a coded signal by using an antenna. In the demodulation method, a signal is transmitted by using a channel, and after receiving the signal by using an antenna, a receive end first performs digital signal processing, including processes such as synchronization and equalization, then performs overlapped multiplexing-based demodulation and decoding, and finally performs factor graph-based belief propagation decoding on a decoding result, to finally obtain a decoded sequence.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: November 10, 2020
    Assignee: SHENZHEN KUANG-CHI HEZHONG TECHNOLOGY LTD
    Inventors: Ruopeng Liu, Chunlin Ji, Hao Zheng, Shasha Zhang
  • Patent number: 10795759
    Abstract: Apparatuses and methods for error correction coding and data bus inversion for semiconductor memories are described. An example apparatus includes an I/O circuit configured to receive first data and first ECC data associated with the first data, a memory array, and a control circuit. The control circuit is coupled between the I/O circuit and the memory array. The control circuit is configured to execute first ECC-decoding to produce corrected first data and corrected first ECC data responsive, at least in part, to the first data and the first ECC data. The control circuit is further configured to store both the corrected first data and the corrected first ECC data into the memory array.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: October 6, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Yoshiro Riho, Atsushi Shimizu, Sang-Kyun Park, Jongtae Kwak
  • Patent number: 10771095
    Abstract: A region specifying unit specifies a first region where a regular bit string is in a transmission frame, a second region which has a bit string similar to a defined bit string, and a third region which has a non-regular bit string and extracts a difference between the bit string in the second region and the defined bit string. A first CRC acquisition unit acquires a first CRC corresponding to the regular bit string. A second CRC acquisition unit acquires a second CRC corresponding to the defined bit string. A differential CRC acquisition unit acquires a differential CRC corresponding to the extracted difference. A third CRC generation unit generates a third CRC corresponding to a bit string in the third region. A frame CRC generation unit generates a CRC of the transmission frame using the first CRC, the second CRC, the differential CRC, and the third CRC.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: September 8, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Kiyohito Miyazaki
  • Patent number: 10771191
    Abstract: For correction coding of a source file for transmission, the source file is divided into a plurality of groups each having a plurality of source packets. Each group is arranged into a matrix format, and braided forward error correction (FEC) packets are generated for each column, row and diagonal of a respective group by XOR'ing the source packets from the corresponding column, row and diagonal. Then, low density parity check (LDPC) FEC packets are generated for the respective group of source packets and corresponding braided FEC packets. The FEC packets generated in this manner, which are referred to as continuous FEC packets, are transmitted to a receiver component, and upon reception, an iteration of braided FEC decoding and LDPC FEC decoding is applied to the received continuous FEC packets, until all the source packets are recovered and the source file is reconstructed or until there is no more incoming packets.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: September 8, 2020
    Assignee: KenCast, Inc.
    Inventor: Weimin Fang
  • Patent number: 10725992
    Abstract: An apparatus has processing circuitry for processing instructions from multiple threads. A storage structure is shared between the threads and has a number of entries. Indexing circuitry generates a target index value identifying an entry of the storage structure to be accessed in response to a request from the processing circuitry specifying a requested index value corresponding to information to be accessed from the storage structure. The indexing circuitry generates the target index value as a function of the requested index value and a key value selected depending on which of the threads trigger the request. The key value for at least one of the threads is updated from time to time.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: July 28, 2020
    Assignee: ARM Limited
    Inventors: Mitchell Bryan Hayenga, Curtis Glenn Dunham, Dam Sunwoo
  • Patent number: 10727875
    Abstract: An encoder and decoder using LDPC-CC which avoid lowering the transmission efficiency of information while not deteriorating error correction performance, even at termination; and an encoding method of the same. A termination sequence length determining unit determines the sequence length of a termination sequence transmitted added to the end of an information sequence, according to the information length (information size) and encoding rate of the information sequence. A parity calculation unit carries out LDPC-CC coding on the information sequence and the known-information sequence necessary for generating a termination sequence of the determined termination sequence length, and calculates a parity sequence.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: July 28, 2020
    Assignee: Panasonic Corporation
    Inventors: Yutaka Murakami, Hisao Koga, Nobutaka Kodama
  • Patent number: 10721022
    Abstract: A master includes a transmission/reception unit which transmits/receives a signal to/from a slave, and an error detection unit which detects error occurrence by performing parity check to data received by the transmission/reception unit. Then, the error detection unit performs error detection assuming one bit of 2-bit parity included in the data received by the transmission/reception unit as even parity, and the other bit as odd parity. The present technology can be applied to a bus IF which performs communication in compliance with, for example, an I3C standard.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: July 21, 2020
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Hiroo Takahashi, Takashi Yokokawa, Sonfun Lee, Naohiro Koshisaka
  • Patent number: 10715821
    Abstract: A method for decoding a transform block of quantized transform coefficients. The method includes decoding, from an encoded bitstream, a predetermined number of coefficients of the quantized transform coefficients, the transform block includes the predetermined number of coefficients and subsequent quantized transform coefficients; determining a value for the predetermined number of coefficients; decoding, from the encoded bitstream, a subsequent quantized transform coefficient of the subsequent quantized transform coefficients; and determining whether to decode an end-of-block (EOB) indicator based on the value that is determined for the predetermined number of coefficients.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: July 14, 2020
    Assignee: GOOGLE LLC
    Inventor: Dake He
  • Patent number: 10701399
    Abstract: In a method to reconstruct a high dynamic range video signal, a decoder receives a base layer standard dynamic range video signal, an enhancement layer video signal, and a metadata bitstream for a reference processing unit. A decoder reconstructs a high-dynamic range video output signal based on the base layer video signal, the enhancement layer video signal, and the data syntax and metadata specified by the metadata bitstream.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: June 30, 2020
    Assignees: Dolby Laboratories Licensing Corporation, Dolby International AB
    Inventors: Klaas Heinrich Schueuer, David Brooks, Satoshi Teshigawara, Tao Chen
  • Patent number: 10678634
    Abstract: A fault detection circuit generates a current parity bit for configuration data currently stored in a configuration register during each clock cycle, and compares the current parity bit with a previous parity bit generated during a previous clock cycle. An error signal is asserted when a mismatch is detected, indicating that the configuration register data erroneously changed due to a random hardware fault. Detection output circuitry is used to disable the error signal output driver using existing register input control signals, which prevents false error signals during intentional configuration data update operations. A parity input multiplexer, also controlled in response to the existing register input control signals, facilitates a parity update mode during intentional configuration data update operations, whereby updated parity values are generated for new/updated configuration data bytes before being written into the configuration registers.
    Type: Grant
    Filed: January 21, 2019
    Date of Patent: June 9, 2020
    Assignee: Synopsys, Inc.
    Inventor: Harsharaj Ellur
  • Patent number: 10651974
    Abstract: A network device receives a packet having i) a first field that is to be updated by the network device, and ii) a second field that includes current error detection information corresponding to content of the packet, the content including the first field. The network device determines an update value that is to be added to a current value of the first field to generate a new value of the first field. The network device generates new error detection information using the current error detection information and the update value, and without using the current value of the first field. The network device modifies the second field to include the new error detection information, and modifies the first field to include the new value.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: May 12, 2020
    Assignee: Marvell Asia Pte, Ltd.
    Inventor: Tal Mizrahi
  • Patent number: 10637503
    Abstract: The present disclosure relates to methods and systems for decoding a low density parity check (LDPC) encoded codeword. The methods may include receiving a codeword over a data channel. The codeword may be encoded with a preset number of data bits having one or more shortened data bits. The methods may also include obtaining a parity check matrix that defines relationships between a plurality of variable nodes and a plurality of check nodes. The methods may further include decoding the codeword by iteratively estimating values with respect to the codeword at the plurality of variable nodes and the plurality of check nodes. During each iteration, a same part of the plurality of variable nodes related to one or more shortened data bits are skipped from estimation.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: April 28, 2020
    Assignee: INNOGRIT TECHNOLOGIES CO., LTD.
    Inventor: Yuan-Mao Chang
  • Patent number: 10623139
    Abstract: A pre-5th-generation (pre-5G) or 5G communication system for supporting higher data rates beyond a 4th-generation (4G) communication system, such as long term evolution (LTE) is provided. A channel encoding method in a communication or broadcasting system includes identifying an input bit size, determining a block size (Z), determining a low density parity check (LDPC) sequence to perform LDPC encoding, and performing the LDPC encoding based on the LDPC sequence and the block size.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: April 14, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seho Myung, Kyungjoong Kim, Seokki Ahn, Hongsil Jeong, Min Jang
  • Patent number: 10599957
    Abstract: A system and method for detecting data drift is disclosed. The system may be configured to perform a method, the method including receiving model training data and generating a predictive model. Generating the predictive model may include model training or hyperparameter tuning. The method may include receiving model input data and generating predicted data using the predictive model, based on the model input data. The method may include receiving event data and detecting data drift based on the predicted data and the event data. The method may include receiving current data and detecting data drift based on the data profile of the current data. The method may include model training and detecting data drift based on a difference in a trained model parameter from a baseline model parameter. The method may include hyperparameter tuning and detecting data drift based on a difference in a tuned hyperparameter from a baseline hyperparameter.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: March 24, 2020
    Assignee: Capital One Services, LLC
    Inventors: Austin Walters, Jeremy Goodsitt, Anh Truong, Fardin Abdi Taghi Abad, Mark Watson, Vincent Pham, Kate Key, Reza Farivar
  • Patent number: 10572338
    Abstract: The present disclosure includes apparatuses and methods for estimating an error rate associated with memory. A number of embodiments include sensing data stored in a memory, performing an error detection operation on the sensed data, determining a quantity of parity violations associated with the error detection operation, and estimating an error rate associated with the memory based on the determined quantity of parity violations.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: February 25, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Sivagnanam Parthasarathy, Mustafa N. Kaynak, Patrick R. Khayat, Nicholas J. Richardson
  • Patent number: 10560216
    Abstract: Fifth Generation (5G) or pre-5G communication system for supporting a data transfer rate higher than that of a fourth Generation (4G) communication system, such as Long Term Evolution (LTE), and subsequent systems. The present disclosure provides a method for transmitting a signal by a transmission terminal in a communication system using a Low Density Parity Check (LDPC) code. The method include receiving a change request for changing a coding rate of the LDPC code, from a reception terminal; determining a first coding rate based on the change request; and transmitting information on the first coding rate in respond to the change request, to a reception terminal, wherein the change request for changing the coding rate comprises at least one of information indicating a coding rate determined by the reception terminal, or information indicating a state of the reception terminal.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: February 11, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chi-Woo Lim, Jae-Yoel Kim, Woo-Myoung Park, Seok-Ki Ahn, Min Jang
  • Patent number: 10523366
    Abstract: A message-passing decoder operates by storing, at a check node, a minimum value, a next-to-minimum value, an edge location of the minimum value, and information regarding the signs of incoming messages. For an edge which is not the location of a previous minimum value, the minimum value and the next-to-minimum value, and the location of the minimum value, are set based on the magnitude of an incoming message. For an edge which is the location of the previous minimum value, the minimum value and the next-to-minimum value are set based on the magnitude of an incoming message, and when the magnitude of the incoming message is at most equal to the previous next-to-minimum value, the location of the minimum value is set to the respective edge, and when the magnitude of the incoming message is greater than the previous next-to-minimum value, the location of the minimum value is approximated.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: December 31, 2019
    Assignee: Marvell International Ltd.
    Inventor: Panu Chaichanavong
  • Patent number: 10523236
    Abstract: A method employed in a low-density parity-check code decoder includes: receiving a specific data portion of a first codeword; calculating a flipping function value of the specific data portion of the first codeword according to the specific data portion by using checking equations of a parity check matrix to calculate checking values of the specific data portion; and determining whether to flip the specific data portion of the first codeword by comparing the flipping function value with a flipping threshold which has been calculated based on a plurality of flipping function values of a plurality of previous data portions earlier than the specific data portion.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: December 31, 2019
    Assignee: Silicon Motion, Inc.
    Inventor: Shiuan-Hao Kuo
  • Patent number: 10484130
    Abstract: Embodiments of this disclosure enhance the error detection performance of parallel polar encoding by cross-concatenating parity bits between segments of information bits transmitted over different sets of sub-channels. In one embodiment, a first segment of information bits is transmitted over a first set of sub-channels, and at least a second segment of information bits, and a masked parity bit, are transmitted over a second set of sub-channels. A value of the masked parity bit is equal to a bitwise combination of a first parity bit computed from the first segment of information bits and a second parity bit computed from the second segment of information bits. The bitwise combination may be a bitwise AND, a bitwise OR, or a bitwise XOR of the respective parity bits.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: November 19, 2019
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Huazi Zhang, Gongzheng Zhang, Rong Li, Jun Wang, Wen Tong, Yiqun Ge
  • Patent number: 10462491
    Abstract: In a method to reconstruct a high dynamic range video signal, a decoder receives a base layer standard dynamic range video signal, an enhancement layer video signal, a metadata bitstream for a reference processing unit and a CRC code related to the metadata. A decoder reconstructs a high-dynamic range video output signal based on the base layer video signal, the enhancement layer video signal, and the data syntax and metadata specified by the metadata bitstream.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: October 29, 2019
    Assignees: Dolby Laboratories Licensing Corporation, Dolby International AB
    Inventors: Klaas Heinrich Schueuer, David Brooks, Satoshi Teshigawara, Tao Chen
  • Patent number: 10432220
    Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 7/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: October 1, 2019
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Heung-Mook Kim, Sun-Hyoung Kwon, Nam-Ho Hur
  • Patent number: 10389383
    Abstract: Techniques are described for encoding information data bits using a low-density parity-check matrix optimized for a Low-Density Parity-Check (LDPC) encoder. In an example, the parity-check matrix includes a first matrix and a second matrix. The second matrix is a square matrix, and is also a block diagonal matrix that includes a set of square submatrices located on the diagonal of the block diagonal matrix. An intermediate vector is generated based on the information data bits and the first matrix, and a parity vector of a codeword is generated based on the intermediate vector and the second matrix.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: August 20, 2019
    Assignee: SK Hynix Inc.
    Inventors: Chenrong Xiong, Fan Zhang, Aman Bhatia, Abhiram Prabhakar, Yu Cai, Naveen Kumar
  • Patent number: 10374632
    Abstract: Systems and methods for data transport in optical communications systems, including a transmitter for encoding a received information sequence by constructing an outer and inner quasi cyclic-low-density parity check (QC-LDPC) code. The encoding includes dividing the received information sequence into a plurality of messages of equal length, encoding each of the messages into a codeword to generate a plurality of outer codewords, cascading the plurality of outer codewords to generate a bit sequence, and executing inner encoding to encode each of the plurality of outer codewords into codewords in QC-LDPC inner code. A receiver decodes a received data stream based on the QC-LDPC inner code using two-phase decoding including iteratively performing at least one of inner/outer and outer/inner decoding until a threshold condition is reached.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: August 6, 2019
    Assignee: NEC Corporation
    Inventors: Shaoliang Zhang, Fatih Yaman, Ting Wang, Yoshihisa Inada