Abstract: Embodiments of the disclosure provide a comparison system including at least one comparison circuit, the comparison circuit including: a common circuit, connected to a power supply signal and a ground signal, and configured to control output of the power supply signal or the ground signal based on a first signal and a second signal which are inverted; a first logical circuit, connected to the common circuit, and configured to receive a third signal and a fourth signal which are inverted, and output a first operation signal which is an exclusive OR (XOR) of the first signal and the third signal; and a second logical circuit, connected to the common circuit, and configured to receive the third signal and the fourth signal, and output a second operation signal which is a not exclusive OR (XNOR) of the first signal and the third signal.

Abstract: Techniques are described for joint encoding and decoding of information symbols. In one embodiment, a method for joint encoding includes, in part, obtaining a sequence of information symbols, generating a plurality of cyclic codewords each corresponding to a portion of the sequence of information symbols, jointly encoding the plurality of cyclic codewords to generate at least one combined codeword, and providing the combined codeword to a device. The at least one combined codeword may be generated through Galois Fourier Transform (GFT).

Abstract: An error correction system includes M decoding units, each configured to perform decoding on the X first operation codes and the Y second operation codes; the decoding unit includes: a decoder, configured to receive the X first operation codes and output N first decoded signals, each corresponding to a respective one bit of the N data; a first AND gate unit, configured to receive and perform a logical AND operation on Z selected operation codes; an NOR gate unit, configured to receive and perform a logical NOR operation on (Y?Z) unselected operation codes; and N second AND gate units, each having an input terminal connected to an output terminal of the first AND gate unit, an output terminal of the NOR gate unit and one of the first decoded signals.

Abstract: A method for performing low density parity check (LDPC) coding of a transmitter in a wireless communication system, according to the present disclosure, may comprise the steps of: acquiring a proto-matrix corresponding to a protograph; on the basis of weights and lifting factors of columns of the proto-matrix, acquiring one or more permuted vectors corresponding to each of the columns, a first permuted vector included in the one or more permuted vectors having been randomly generated; distributing the one or more permuted vectors for each row of a corresponding column; on the basis of the distributed one or more permuted vectors, acquiring a plurality of lifted sub matrices corresponding to a plurality of elements of the proto-matrix; generating a base graph on the basis of the plurality of lifted sub matrices; generating a parity check matrix (PCM) on the basis of the base graph; and performing LDPC coding by using the PCM.

Abstract: Various embodiments relate to a method for storing and reading data from a memory. Data words stored in the memory may be grouped, and word specific parity information and shared parity information is generated, and the shared parity information is distributed among the group of words. During reading of a word, if more errors are detected than can be corrected with word parity data, the shared parity data is retrieved and used to make the error corrections.

Abstract: Various embodiments described herein provide for a mechanism for detecting failure in the operation of FEC of a physical layer device, such as a physical layer device of a networking application that seeks to meet a functional safety standard (e.g., ISO 26262). In particular, some embodiments described herein provide one of several methods for detecting a failure in the operation of a FEC decoder of a physical layer device.

Abstract: Host data is written to a set of pages of a page stripe of a storage area of a memory sub-system. A set of exclusive or (XOR) parity values corresponding to the host data written to a portion of the set of pages of the storage area is generated. An additional XOR parity value is generated by executing an XOR operation using the set of XOR parity values. Parity data including the set of XOR parity values and the additional XOR parity value is stored in a cache memory of the memory sub-system. The parity data is written to an available page stripe of the storage area.

Abstract: Devices and techniques for disposable parity are described herein. First and second portions of data can be obtained, and respective parity values stored in adjacent memory locations. An entry mapping the respective parity values to the first and second portions of data is updated when the parity values are stored. If an error occurs when writing a portion of data, the mapping entry is used to retrieve the parity data to correct the error. Otherwise, the parity data is discarded.

Abstract: The present disclosure relates to a 5th generation (5G) or pre-5G communication system for supporting a higher data transfer rate beyond a 4th generation (4G) communication system such as long term evolution (LTE). The present disclosure relates to encoding and decoding using a polar code in a wireless communication system. A method for operation of a first device in a wireless communication system may comprise the steps of: among sub-blocks including at least one node, identifying at least one inactive sub-block to deactivate the node operation in the sub-blocks; encoding data by using a construction matrix determined on the basis of the at least one inactive sub-block; and transmitting the encoded data to a second device.

Abstract: The present disclosure relates to an electronic system for computing items of an outer product matrix, for each item of at least part of the items of the matrix. The system is configured to receive a pair of real numbers of two vectors, the pair corresponding to the item. The system is further configured to compute a stochastic representation of the real numbers resulting in two sets of bits, the set of bits comprising a subset of bits representing the real number and a sign bit indicative of the sign of the real number. The system is further configured to perform a sequence of digital operations using the two sets of bits to provide a representation of the item.

Abstract: A circuit and methods of operation thereof are provided for robust protection against soft errors. The circuit includes a first set of storage elements coupled to and configured to sample a set of data inputs at a first set of times. The circuit includes a second set of storage elements coupled to and configured to sample the set of data inputs at a second set of times. A first parity generator generates a first parity check for the set of data inputs and a second parity generator generates a second parity check for output of the first set of storage elements. An error correction unit compares the first parity check and the second parity check to detect occurrences of error conditions in the circuit. The error correction unit may control output or operating characteristics of the circuit as a result of error conditions detected.

Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 7/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

Abstract: Proposed are concepts for providing resilience (i.e., fault tolerance) for the temporary data needs of a distributed file system. Such concepts may, for instance, provide a virtual storage layer in a data node of a distributed file system. The virtual storage layer may provide resilience for the temporary data needs of a Massively Parallel Processing (MPP) SQL on Hadoop engine.

Abstract: Exemplary methods, apparatuses, and systems include receiving read operations. The read operations are divided into a current set of a sequence of read operations and one or more other sets of sequences of read operations. An aggressor read operation is selected from the current set. A data integrity scan is performed on a victim of the aggressor read operation. A read margin for a victim of the aggressor read operation is determined based on the error rate. An identifier associated with the aggressor is added to a cache and a counter for the identifier added to the cache is initialized based upon the determined read margin.

Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 3/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). A channel encoding method in a communication or broadcasting system includes identifying an input bit size, determining a block size (Z), determining an LDPC sequence for LDPC encoding, and performing the LDPC encoding based on the LDPC sequence and the block size.

Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). A channel encoding method in a communication or broadcasting system includes identifying an input bit size, determining a block size (Z), determining an LDPC sequence for LDPC encoding, and performing the LDPC encoding based on the LDPC sequence and the block size.

Abstract: A method and a device of selecting a base graph of a low-density parity-check code are provided. The method includes: acquiring a data information length and a channel coding rate of to-be-encoded data; determining a target base graph selection strategy according to the data information length and an information length range of a base graph; determining a target base graph for the to-be-encoded data according to the target base graph selection strategy and the channel coding rate.

Abstract: A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding, an interleaver configured to interleave the LDPC codeword, and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver performs interleaving by dividing the LDPC codeword into a plurality of groups, rearranging an order of the plurality of groups in group units, and dividing the plurality of rearranged groups based on a modulation order according to the modulation method.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 4096-symbol mapping.

Abstract: Embodiments of the invention provide a check node processing unit configured to determine at least one check node message to decode a signal encoded using a NB-LDPC code, the check node processing unit comprising: a data link to one or more message presorting units to determine permuted variable node messages by applying permutations to at least three variable node messages generated by variable node processing units; a syndrome calculation unit to determine a set of syndromes comprising binary values from the permuted variable node messages; a decorrelation and permutation unit configured, for each check node message of a given index, to: determine a permuted index by applying the inverse of the one or more permutations; select at least one valid syndrome in the set of syndromes; and determine at least one candidate check node component; and a selection unit to determine at least one check node message from the candidate check node component.

Abstract: Methods and devices for encoding source words and decoding codewords wherein encoding a source word includes: receiving a 1×K source word row vector ?; and generating a 1×N codeword vector c=?·G, wherein G is a K×N generator matrix derived from a parity check matrix HI; and wherein the parity check matrix HI is derived from a base parity check matrix H by applying an optimized lifting matrix to the base parity check matrix H.

Abstract: A semiconductor memory system including: a semiconductor memory device suitable for storing a codeword; and an LDPC decoder suitable for decoding the codeword to generate decoded data, wherein the LDPC decoder includes: a message passing decoding component suitable for performing a first decoding operation of decoding the codeword, and calculating the minimum value among numbers of UCNs; and an error path detection component suitable for detecting error path candidates using a tree in which each of UCNs corresponding to the minimum value is set to a root node, sorting the detected error path candidates in ascending order of maximum LLRs, resetting symbol values and LLRs of variable nodes in the error path candidates, and providing the message passing decoding unit with information on the reset symbol values and LLRs.

Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 3/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

Abstract: Systems, methods and apparatus select a code book based on channel conditions and performance of a demodulator or demapper in a wireless receiver. The method may include determining that the receiver in a first wireless communication apparatus is configured for iteratively processing signals received from a channel, selecting a code book for use in communicating over the channel based on conditions affecting transmission of the signals through the channel and performance information associated with a demapper in the receiver, and identifying the selected code book in one or more control channels transmitted to a second wireless communication apparatus.

Abstract: This application relates to communicating information between communication devices. A channel coding method is disclosed. A communication device obtains an input sequence of K bits. The communication device encodes the input sequence using a low density parity check (LDPC) matrix H, to obtain an encoded sequence. The LDPC matrix H is determined according to a base matrix and a lifting factor Z. The base matrix includes m rows and n columns, m is greater than or equal to 5, and n is greater than or equal to 27. The lifting factor Z satisfies a relationship of 22*Z?K. According to the encoding method provided in the embodiments, information bit sequences of a plurality of lengths can be encoded for transmission between the communication devices.

Abstract: An error-handling method, an associated data storage device and the controller thereof are provided. The error-handling method may include: uploading an error-handling program to a buffer memory equipped with error correction code (ECC) protection capability; in response to at least one error, interrupting execution of a current procedure and activating an interruption service; executing the error-handling program on the buffer memory; disabling a transmission interface circuit; resetting at least one hardware engine and at least one NV memory element; performing cache rearrangement regarding a data cache within the data storage device, and programming rearranged cache data into the NV memory element, to perform data recovery; and through activating a watchdog module and the transmission interface circuit and relinking with a host device, completing soft reset to make the data storage device operate normally again.

Abstract: A storage device includes a storage controller, non-volatile memory, volatile memory and a communication interface configured to connect to external volatile memory of a host system. The storage controller is configured to receive data from the host system for storing in the non-volatile memory, buffer the data in the volatile memory, obtain parity data corresponding to the buffered data from an external volatile memory within the host system, compute XOR parity data for the buffered data based on the parity data and the buffered data, store the computed XOR parity data on the external volatile memory, and write the data from the host to the non-volatile memory.

Abstract: Devices and methods may be used to append a scalable (1) of parity bits in a data packet that scales with a number of data bits in a payload of the data packet. The parity bits may be generated utilizing a table of entries. In some examples, each entry in the table corresponds to a number of the data bits to be included in the payload; and each column of the table may be used to generate a corresponding parity bit of the one or more parity bits.

Abstract: An apparatus includes a plurality of translation circuits, a logic circuit and a comparison circuit. The translation circuits may be configured to generate (i) a plurality of first check values by translating a plurality of input values into a codomain, and (ii) a second check value by translating an output value into the codomain. The output value may be previously generated in response to the input values and stored in a memory. The logic circuit may be configured to generate a third check value in the codomain in response to the first check values. The comparison circuit may be configured to generate an error signal by comparing the second check value with the third check value. A mismatch in the comparison may detect a corruption of the output value.

Abstract: Devices and techniques for disposable parity are described herein. First and second portions of data can be obtained, and respective parity values stored in adjacent memory locations. An entry mapping the respective parity values to the first and second portions of data is updated when the parity values are stored. If an error occurs when writing a portion of data, the mapping entry is used to retrieve the parity data to correct the error. Otherwise, the parity data is discarded.

Abstract: An error correction code (ECC) encoder includes a plurality of exclusive OR (XOR) gates configured to receive a “k”-bit original data in parallel and configured to perform a plurality of XOR operations to the “k”-bit original data to output a “(n?k)”-bit parity data. The “k”-bit original data and the “(n?k)”-bit parity data form an “n”-bit codeword, “k” denotes a natural number and “n” denotes a natural number which is greater than “k”.

Abstract: An error injected error correction code (ECC) word generator generates a set of ECC code words injected with bit errors for being read by an ECC decoder and error reporting hardware. The set of the error injected ECC words has a binomial distribution with regard to a number of the bit errors in a given ECC word of the set. The set of error injected ECC words has a predetermined average ratio of bit errors.

Abstract: A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder which encodes input bits including outer encoded bits to generate an LDPC codeword including the input bits and parity bits to be transmitted to a receiver in a current frame; a puncturer which punctures a part of the parity bits which is not transmitted in the current frame; and an additional parity generator which selects at least a part of the parity bits to generate additional parity bits transmitted to the receiver in a previous frame of the current frame, wherein a number of the additional parity bits is determined based on a number of the outer encoded bits and a number of the parity bits left after the puncturing.

Abstract: Disclosed relates to a decoder for LDPC code, including: a variable node processing unit; a check node processing unit; a memory for storing iterative messages of edges of a parity-check matrix for LDPC code; and a controller for controlling the node processing units to perform iterations of decoding until the decoding ends, wherein, in each iteration of decoding, the controller controls the variable node processing unit to compute variable node messages in a traversing manner for all variable nodes and updates the iterative messages in the memory according to the computed variable node messages, and controls the check node processing unit to compute check node messages in a traversing manner for all check nodes and updates the iterative messages in the memory according to the computed check node messages.

Abstract: The disclosed embodiments are directed to systems, devices, and methods for iterative message-passing decoding. In one embodiment, a method is disclosed comprising decoding a first codeword at a storage device using a detector and a decoder, the first codeword comprising a set of symbols from a first set of codewords; assigning, via the decoding, a set of confidence levels for each symbol in the first codeword; transmitting, by the storage device, the confidence levels to an iterative decoder; generating, by the iterative decoder, a second codeword based on the set of confidence levels, the second codeword excluding at least one symbol in the set of symbols; and iteratively decoding, by the iterative decoder, the second codeword using an erasure decoder; and transmitting, by the iterative decoder, soft information generated by the erasure decoder to the storage device for subsequent decoding by the storage device.

Abstract: Devices and methods may be used to append a scalable number of parity bits in a data packet that scales with a number of data bits in a payload of the data packet. The parity bits may be generated utilizing a table of entries. In some examples, each entry in the table corresponds to a number of the data bits to be included in the payload; and each column of the table may be used to generate a corresponding parity bit of the one or more parity bits.

Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). An apparatus and a method for channel encoding and decoding in a communication or broadcasting system is provided. According to the present disclosure, the method for channel encoding in a communication or broadcasting system includes determining a block size Z, and performing encoding based on the block size and a parity check matrix corresponding to the block size, in which the block size is included in any one of the plurality of block size groups and the parity check matrix is different for each block size group.

Abstract: At least a method and an apparatus are presented for decoding a signal. For example, a decoder is presented for determining an estimate of an encoded signal. The decoder comprises one or more variable node processing units and one or more check node processing units configured to exchange messages, each message comprising one or more components, a component comprising a symbol and a reliability metric associated with the symbol. The at least one check processing unit is further configured to calculate at two or more elementary check node processors a set of syndromes from at least three permuted messages, a syndrome comprising a binary vector; generate at least one check node message from the set of syndromes depending on the binary vector, and send the at least one check node message to a signal estimation unit.

Abstract: Aspects of the present disclosure relate to parity-check matrix (P-matrix) rotation in low-density parity check (LDPC) coding. The P-matrix rotation may be performed by a plurality of shift registers, where each shift register is configured to receive a respective set of bits corresponding to a respective column in the P-matrix. Each cycle, the shift registers may then incrementally rotate their respective sets of bits to achieve a respective shift amount up to a maximum shift amount per cycle. During a cycle, if the shift amount produced by a shift register results in a degree of rotation corresponding to an element within the respective column of the P-matrix, the shift register may output the rotated set of bits for further processing.

Abstract: Devices and methods may be used to append a scalable (1) of parity bits in a data packet that scales with a number of data bits in a payload of the data packet. The parity bits may be generated utilizing a table of entries. In some examples, each entry in the table corresponds to a number of the data bits to be included in the payload; and each column of the table may be used to generate a corresponding parity bit of the one or more parity bits.

Abstract: A network for an aircraft including a master device and slave devices connected in daisy-chain arrangement series. Each slave device has a unique identifier. The master transmits polling data packets along the slave devices, each including only one identifier. Polling data packets are transmitted in successive sequences, each including for each slave device only one polling data packet and including the polling data packets in a predetermined order. Each slave device includes a first data interface for connection in an upstream direction, a second data interface for connection in the downstream direction, and a processing unit to compare for each received polling data packet the identifier thereof with the identifier of the respective slave device, and output a response data packet to the master device if the two identifiers match, and forward the polling data packet to the second interface at least if the two identifiers do not match.

Abstract: System and method of verifying validity of a metadata modification request to prevent improper metadata operations. During initialization of a volume in a storage device and once a metadata area is reserved for a metadata structure, information characterizing the metadata structure and metadata area is stored in the storage device, which may be in the form of an area legend composed of descriptors such as a magic signature, a node size, a clump size of reservation, and extent of the metadata area. Responsive to a request for operating on metadata, relevant information provided in the request is verified against the stored characteristic information. If the verification discovers an inconsistency between the information provided in the request and the stored characteristic information, the request modification is treated as invalid and blocked from operation.

Abstract: A Low-Density Parity-Check (LDPC) decoder and a method for LDPC decoding are provided. The LDPC decoder receives a soft-decision input codeword block in which the probability of a bit being a “0” or a “1” is represented as a log-likelihood ratio (LLR). During LDPC decoding, a sequence of hardware logic units iteratively updates the soft-decision input codeword block until a valid codeword is found or a maximum number of decoding iterations is reached. Each hardware logic unit comprises a check node (CN) update logic unit and a variable node (VN) update logic unit. The CN update logic units are coupled via a closed CN path, and the VN update logic units are coupled via a closed VN path. Aspects of this LDPC decoder alleviate the global routing and energy efficiency challenges of traditional LDPC decoders, to enable multi-rate, multi-Gb/s decoding without compromising error correction performance in next-generation systems and future CMOS technology nodes.

Abstract: Optical fiber data communications are described. A controller can determine chromatic dispersion of an optical signal that is to be demodulated using coherent detection. The controller can then determine the chromatic dispersion of another optical signal that is to be demodulated using direct detection. The chromatic dispersion of the other optical signal can then be adjusted to account for chromatic dispersion experienced by the other optical signal when it propagated through an optical fiber.

Abstract: A data structure of a check matrix for the error correction code is a data structure of a check matrix for an error correction code, in which the error correction code is the LDPC code, and in which the check matrix has a matrix structure in which rows are rearranged for submatrices consisting of a part of columns of the check matrix. Moreover, in the method and device for varying the coding rate of the error correction code, a puncture position that is determined in accordance with a puncture position determination signal is a puncture position with which a number of columns in which two or more 1s are contained in a region of the check matrix that is directly affected by puncturing is minimized.

Abstract: A method, apparatus, and non-transitory computer-readable recording medium for generating an algebraic Spatially-Coupled Low-Density Parity-Check (SC LDPC) code are provided. The method includes selecting an LDPC block code over a finite field GF(q) with a girth of at least 6; constructing a parity-check matrix H from the selected LDPC block code; replicating H a user-definable number of times to form a two-dimensional array Hrep; constructing a masking matrix W with a user-definable spatially-coupled pattern; and masking a sub-matrix of Hrep using W to obtain a spatially-coupled parity-check matrix HSC, wherein a null space of HSC is the algebraic SC LDPC code.

Abstract: A low density parity check (LDPC) decoder, including a memory configured to store a log-likelihood ratio (LLR) value of bits output from a demapper, and an LLR message exchanged between a variable node and an inspection node. The LDPC decoder further includes a node processor configured to select a decoding algorithm from a first algorithm and a second algorithm based on a code rate of an LDPC code, and decode the LLR message based on the selected decoding algorithm.

Abstract: A controller of a non-volatile memory system may be configured to identify bits of data to be stored in memory elements of non-volatile memory that are identified as unreliable. The controller may be configured to bias at least some of these bits to a predetermined logic value at which the bits are likely to be read from the unreliable memory elements. The controller may do so using a biasing key that the controller generates based on identification of the bits. Subsequently, when the data is read, the controller may assign log likelihood ratio values for the bits to correspond to a percent likelihood of the bits being biased to the predetermined logic value. The bits may also be unbiased using the biasing key.

Abstract: A data processing apparatus includes a cache memory supporting parallel data loads involving both a first address and a second address. The first address is compared with TAG values stored within a first value store and the second address is compared in parallel with TAG values stored within a second value store. The second value store contains a proper subset of the data value stored within the first value store.