Storage Accessing (e.g., Address Parity Check) Patents (Class 714/805)
  • Patent number: 11393510
    Abstract: An example method of encoding data attributes by data stream identifiers may include: receiving a plurality of data items to be written to a storage device; identifying, among the plurality of data items, a first data item and a second data item sharing a data attribute; generate a data stream identifier comprising an encoded form of the data attribute; and transmitting, to a controller of the storage device, one or more write commands comprising the first data item and the second data item, wherein each write command further specifies the data stream identifier.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: July 19, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Paul A. Suhler, Ram Krishan Kaul, Michael B. Danielson
  • Patent number: 11115056
    Abstract: Systems for location selection based on erasure code techniques are provided. One system includes a monitor module that monitors data speed characteristics for one or more locations on a storage device. Additionally, the system includes a classification module that determines an erasure code technique for an application, wherein data associated with the application is stored on a storage device. Also, the system includes a selection module that selects a location in one or more locations for storing data based on monitored data speed characteristics and a determined erasure code technique.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: September 7, 2021
    Assignee: International Business Machines Corporation
    Inventors: Sasikanth Eda, Poornima Gupte, Sukumar Vankadhara, Sandeep Ramesh Patil
  • Patent number: 11106530
    Abstract: A variety of applications can include apparatus and/or methods that provide parity data protection to data in a memory system for a limited period of time and not stored as permanent parity data in a non-volatile memory. Parity data can be accumulated in a volatile memory for data programmed via a group of access lies having a specified number of access lines in the group. A read verify can be issued to selected pages after programming finishes at the end of programming via the access lines of the group. With the programming of the data determined to be acceptable at the end of programming via the last of the access lines of the group, the parity data in the volatile memory can be discarded and accumulation can begin for a next group having a specified number of access lines. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: August 31, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Chun Sum Yeung, Falgun G. Trivedi, Harish Reddy Singidi, Xiangang Luo, Preston Allen Thomson, Ting Luo, Jianmin Huang
  • Patent number: 11055172
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for safety mechanisms to actively detect address faults. An example system includes a first parity generator, a second parity generator, and a parity checker. The first parity generator is to generate a first parity based on a first address information. The first address information corresponds to a desired location to store data in a memory storage array. The second parity generator is to generate a second parity based on a second address information. The second address information corresponding to an actual location where the data is stored in the memory storage array. The parity checker is to compare the first parity and the second parity to detect a fault.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: July 6, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: David Peter Foley
  • Patent number: 11005598
    Abstract: A forward error correction decoder for packing error information of a codeword in the space that was previously occupied by the parity symbols in the decoder output is presented. Specifically, the decoder summarizes error information of the codeword in a summary vector having the size no greater than the total size of the parity symbols. The decoder then outputs the message symbols from the codeword and the summary error vector, which provides the error information of the received codeword but only requires a bandwidth that is no greater than the bandwidth previously used for transmitting the parity symbols.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: May 11, 2021
    Assignee: XILINX, INC.
    Inventor: Ben J. Jones
  • Patent number: 10942849
    Abstract: An apparatus includes a host device and a data storage device. The host device is configured to store a first translation map for converting a logical sector to a logical erase unit. The data storage device includes a plurality of flash memory devices and a memory controller operationally coupled with the flash memory devices, each of the flash memory devices being arranged into a plurality of erase units, each of the erase units having a plurality of pages for storing data. The memory controller is configured to receive a second translation map from the host device, the second translation map for converting a logical erase unit to a physical erase unit within the flash memory devices, and store the second translation map in a memory module on the data storage device.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: March 9, 2021
    Assignee: Google LLC
    Inventors: Christopher John Sabol, Slava Pestov, Thomas Wyatt Craig, Manuel Enrique Benitez, Monish Shah, Daniel Ari Ehrenberg
  • Patent number: 10916311
    Abstract: Provided are a flash memory and an operation method thereof. The flash memory includes a memory cell array, a controller and a register. The register stores read parameters that include a read voltage value and a read pass voltage value. The controller is configured to perform the read operation on a selected page according to the read parameters to read out the raw data stored in the selected page, determine whether the raw data includes an error bit, and in response to determining that the raw data includes the error bit, update the read parameters by decreasing the read voltage value and/or increasing the read pass voltage value.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: February 9, 2021
    Assignee: GigaDevice Semiconductor (Beijing) Inc.
    Inventor: Minyi Chen
  • Patent number: 10908993
    Abstract: A memory controller is disclosed. The memory controller may include read circuitry to request a value at an address stored in a plurality of data chips, parity circuitry to calculate a parity from original data received from the plurality of the data chips, pollution pattern analysis circuitry to compare the parity with a plurality of pollution patterns programmed into the plurality of the data chips to identify a data chip with an error, and error correction circuitry to correct the error in the original data received from the identified data chip with the error.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: February 2, 2021
    Inventors: Dimin Niu, Mu-Tien Chang, Hongzhong Zheng, Hyun-Joong Kim, Won-Hyung Song, Jangseok Choi
  • Patent number: 10872014
    Abstract: A memory controller is disclosed. The memory controller may include read circuitry to request a value at an address stored in a plurality of data chips, parity circuitry to calculate a parity from original data received from the plurality of the data chips, pollution pattern analysis circuitry to compare the parity with a plurality of pollution patterns programmed into the plurality of the data chips to identify a data chip with an error, and error correction circuitry to correct the error in the original data received from the identified data chip with the error.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: December 22, 2020
    Inventors: Dimin Niu, Mu-Tien Chang, Hongzhong Zheng, Hyun-Joong Kim, Won-Hyung Song, Jangseok Choi
  • Patent number: 10839867
    Abstract: The present disclosure includes apparatuses and methods related to parity determinations using sensing circuitry. An example method can include protecting, using sensing circuitry, a number of data values stored in a respective number of memory cells coupled to a sense line of an array by determining a parity value corresponding to the number of data values without transferring data from the array via an input/output line. The parity value can be determined by a number of XOR operations, for instance. The method can include storing the parity value in another memory cell coupled to the sense line.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: November 17, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Troy A. Manning, Richard C. Murphy
  • Patent number: 10782879
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory including physical blocks, and a controller. The controller manages namespaces. The namespaces include at least a first namespace for storing a first type of data, and a second namespace for storing a second type of data having a lower update frequency than the first type of data. The controller allocates a first number of physical blocks as a physical resource for the first namespace, and allocates a second number of physical blocks as a physical resource for the second namespace, based on a request from a host device specifying an amount of physical resources to be secured for each of the namespaces.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: September 22, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Shinichi Kanno
  • Patent number: 10636577
    Abstract: Safe handling of link errors in a Peripheral Component Interconnect (PCI) express (PCIE) device is disclosed. In one aspect, safe handling of link errors involves detecting errors in a PCIE link and maintaining the PCIE link by preventing the reporting of detected errors and providing safe data to a host in communication with the PCIE link. A PCIE link can be established between a host (incorporating a root complex) and an endpoint device, through which the host can request the performance of operations (e.g., read data, write data) by the endpoint device. Circuitry and/or software can monitor the PCIE link and perform safe handling of link errors when they occur. The circuitry detects link errors and consumes them in such a manner that the host is unaware that an error has occurred and only safe (e.g., non-corrupted) data is provided to the host.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: April 28, 2020
    Assignee: Qualcomm Incorporated
    Inventors: William Bakshi, Nabeel Achlaug
  • Patent number: 10621336
    Abstract: Technologies for software attack detection include a computing device with a processor and a memory external to the processor. The processor originates a memory transaction with an associated secure enclave status bit that indicates whether the memory transaction originated in a secure execution mode, such as from a secure enclave. The processor computes an error-correcting code (ECC) based as a function of memory transaction data and the secure enclave status bit, and performs the memory transaction based on the ECC and the memory transaction data using the memory of the computing device. The processor may store the ECC and the memory transaction data to memory. The processor may load a stored ECC and data from the memory and compare the computed ECC to the stored ECC to detect memory transactions with an invalid secure enclave status bit. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 26, 2015
    Date of Patent: April 14, 2020
    Assignee: Intel Corporation
    Inventors: Bin Xing, Krystof C. Zmudzinski, Wei Wu, Shih-Lien L. Lu, Carlos V. Rozas, Francis X. McKeen, Siddhartha Chhabra, Mark W. Shanahan
  • Patent number: 10482009
    Abstract: An apparatus includes a host device and a data storage device. The host device is configured to store a first translation map for converting a logical sector to a logical erase unit. The data storage device includes a plurality of flash memory devices and a memory controller operationally coupled with the flash memory devices, each of the flash memory devices being arranged into a plurality of erase units, each of the erase units having a plurality of pages for storing data. The memory controller is configured to receive a second translation map from the host device, the second translation map for converting a logical erase unit to a physical erase unit within the flash memory devices, and store the second translation map in a memory module on the data storage device.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 19, 2019
    Assignee: GOOGLE LLC
    Inventors: Christopher John Sabol, Slava Pestov, Thomas W. Craig, Manuel Enrique Benitez, Monish Shah, Daniel A. Ehrenberg
  • Patent number: 10467098
    Abstract: A method for performing an initialization or a reset of a port of an integrated circuit includes: receiving in a device for supervising ports, from a central processing unit of the integrated circuit, a port initialization signal comprising port initialization data and one or more parity bits; inverting in the device for supervising ports the one or more parity bits in accordance with the port initialization signal; providing the port initialization signal comprising the port initialization data and the inverted one or more parity bits to the port of the integrated circuit; on receipt of the port initialization signal at the port, inverting again in the port the inverted one or more parity bits, thereby obtaining the original one or more parity bits and storing the port initialization data and the just obtained original one or more parity bits.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: November 5, 2019
    Assignee: MELEXIS TECHNOLOGIES NV
    Inventors: Philippe Laugier, Benoit Heroux, Thomas Freitag
  • Patent number: 10304519
    Abstract: The present disclosure includes apparatuses and methods related to determining an XOR value in memory. An example method can include performing a NAND operation on a data value stored in a first memory cell and a data value stored in a second memory cell. The method can include performing an OR operation on the data values stored in the first and second memory cells. The method can include performing an AND operation on the result of the NAND operation and a result of the OR operation without transferring data from the memory array via an input/output (I/O) line.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: May 28, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Troy A. Manning
  • Patent number: 10241878
    Abstract: A system and method is disclosed for storing a block of data in a distributed data-storage system. An example method includes identifying a list of a plurality of disks in the distributed data-storage system, randomly selecting a disk from the list of the plurality of disks and adding the selected disk to a subset of disks allocated for a copyset, and continuously performing the step of randomly selecting the disk and adding the disk to the subset of disks until the copyset contains a predetermined amount of allocated disks from the distributed data-storage system. Furthermore, this process is repeated to perform a plurality of copysets. Once the copysets are defined, the method further includes dividing the block of data into a number of data chunks equal to the predetermined amount of allocated disks, and, distributing the data chunks onto disks of one of the plurality of the copysets.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: March 26, 2019
    Assignee: Acronis International GmbH
    Inventors: Lyudmila Ivanichkina, Kirill Korotaev, Stanislav Protasov, Serguei Beloussov, Mark Smulevich
  • Patent number: 10210040
    Abstract: Multi-dimensional parity checker (MDPC) systems and related methods are disclosed to check parity of data regions within external memories. In one embodiment, the MDPC system includes a control register and a parity checker. The parity checker receives data segments accessed from the data region. The parity checker generates and accumulates multi-dimensional parity bits for the data segments and subsequently compares accumulated bits to expected multi-dimensional parity bits to generate multi-dimensional error syndrome bits representing identified comparison errors. The parity checker also determines a syndrome state based upon the multi-dimensional syndrome bits and stores the syndrome state within the control register. The parity checker operates in different modes based upon different values stored in an operational mode field of the control register.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: February 19, 2019
    Assignee: NXP USA, Inc.
    Inventors: Joseph C. Circello, David J. Schimke
  • Patent number: 10185613
    Abstract: The present disclosure is related to devices, systems, and methods for determining errors from logs. An example device can include instructions to analyze a log of a log source, determine an error in the log, the error resulting from a user action with respect to the log source, and provide a portion of the log associated with the error to a user interface.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: January 22, 2019
    Assignee: VMware, Inc.
    Inventors: Vardan Movsisyan, Hovhannes Bolibekyan
  • Patent number: 10133629
    Abstract: The present disclosure relates to methods and systems for implementing redundancy in memory controllers. The disclosed systems and methods utilize a row of memory blocks, such that each memory block in the row is associated with an independent media unit. Failures of the media units are not correlated, and therefore, a failure in one unit does not affect the data stored in the other units. Parity information associated with the data stored in the memory blocks is stored in a separate memory block. If the data in a single memory block has been corrupted, the data stored in the remaining memory blocks and the parity information is used to retrieve the corrupted data.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: November 20, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ashish Singhai, Ashwin Narasimha, Kenneth Alan Okin
  • Patent number: 10103748
    Abstract: A decoding method, a memory control circuit unit and a memory storage device are provided. The decoding method includes: transmitting a read command sequence for reading a plurality of memory cells in order to obtain a plurality of bits, and obtaining a plurality of reliability information corresponding to each of the bits. The decoding method also includes: calculating a sum of a plurality of reliability information matching a check condition among the plurality of reliability information, and adding a balance information to the sum in order to obtain a weight corresponding to a first bit among the bits and a first syndrome. The decoding method further includes: determining whether the bits have at least one error, and if the bits have the at least one error, executing an iteration decoding procedure according to the weight.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: October 16, 2018
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Pei-Jung Hsu
  • Patent number: 9543035
    Abstract: In one aspect, the present disclosure provides a storage device for accounting for transmission errors to improve a usable life span of memory blocks. In some embodiments, the storage device includes: a memory array including a plurality of memory blocks; and a memory controller in communication with the memory array via an interface, wherein the memory controller is configured to detect an error event associated with data from one of the plurality of memory blocks; determine an origin of the error event; increment an error count if the origin of the error event indicates a data error in the one of the plurality of memory blocks and not if the origin of the error event indicates a transmission error; compare the error count to a threshold value; and mark the one of the plurality of memory blocks as bad when the error count exceeds the threshold value.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: January 10, 2017
    Assignee: HGST TECHNOLOGIES SANTA ANA, INC.
    Inventor: Tsan Lin Chen
  • Patent number: 9239753
    Abstract: In one embodiment, a system includes a memory, and a memory controller coupled to the memory via an address bus, a data bus, and an error code bus. The memory stores data at an address and stores an error code at the address. The error code is generated based on a function of the corresponding data and address.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: January 19, 2016
    Assignee: Cavium, Inc.
    Inventors: Aseem Maheshwari, Michael S. Bertone, Richard E. Kessler
  • Patent number: 9208027
    Abstract: Address error detection including a method that receives a read address corresponding to a read location in a memory. Data is read from the read location in the memory. The data is transformed at a computer based on the data and the read address to produce read data. Error correction codes (ECC) bits associated the read data are read from the read location in the memory. The ECC bits were generated based on the write data. It is determined whether the read data has an address error responsive to the read data and the ECC bits associated with the write data. An error is generated in response to determining that the read address has an address error.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: December 8, 2015
    Assignee: International Business Machines Corporation
    Inventor: Richard Nicholas
  • Patent number: 9202573
    Abstract: A partial voltage level read is made on memory cells of a solid state memory device during a voltage settling time after the memory cells are charged (e.g., by a pulse from a charge pump). Digital values representing partial voltage levels are checked for errors (e.g., by an error correction code (ECC) engine). If the values can be corrected, then the values are released for host access. If the values cannot be corrected, then a full voltage read is performed on the memory cells after the voltage levels have substantially settled. Digital values corresponding to the full voltage reads can be released for host access. The use of partial voltage reads results in faster read of solid state memory devices.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: December 1, 2015
    Assignee: Apple Inc.
    Inventors: Michael J. Cornwell, Christopher P. Dudte
  • Patent number: 9170894
    Abstract: Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: October 27, 2015
    Assignee: Rambus Inc.
    Inventors: Ian Shaeffer, Craig E. Hampel
  • Patent number: 9164893
    Abstract: A semiconductor memory device includes a plurality of memory strings each of which includes a series of memory cells that each store data having n bits (n?3), word lines, each connected in common to memory cells of different memory strings, and a control circuit which controls a first write operation and a second write operation. The first write operation includes a first step where a middle threshold voltage distribution is formed in memory cells and a second step following the first step where threshold voltages of some of the memory cells are increased, and the second write operation includes a step where threshold voltage distributions which correspond to the data having n bits is formed in the memory cells, wherein a write verify operation is performed after the first step but not after the second step of the first write operation.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: October 20, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masaki Fujiu
  • Patent number: 9121694
    Abstract: A position detection device includes a first member, a second member, a plurality of detected components, a detector group, and a controller. The second member is opposed the first member and is configured to move relative to the first member in a specific direction. The plurality of detected components are disposed on the first member and faces the second member. The detector group is disposed on the second member and includes a plurality of detectors configured to detect the plurality of detected components. The controller is configured to detect a relative position of the second member relative to the first member based on a detection pattern in which detection results of the plurality of detectors are arranged in a row.
    Type: Grant
    Filed: May 17, 2013
    Date of Patent: September 1, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Tetsuya Mori, Jun Saiki
  • Patent number: 9003153
    Abstract: A memory controller, system and method for storing data blocks in a plurality of physically distinct non-volatile memory devices, each being independently written to or read from. The method includes generating one or more error checking data blocks based upon the plurality of data blocks; and storing the plurality of data blocks and the error checking data block(s) in the distinct physical non-volatile memory devices, with each data block in a different physical memory device. The method links the addresses of the data blocks and the error checking data block(s) in a cyclical link so that any entry to one of the data blocks will result in a link to all of the other data blocks. The memory controller has a processor and a memory for storing programming code for performing the foregoing method.
    Type: Grant
    Filed: November 8, 2010
    Date of Patent: April 7, 2015
    Assignee: Greenliant LLC
    Inventor: Siamak Arya
  • Patent number: 8977925
    Abstract: A method for ordering trapping sets to find one or more dominant trapping sets includes analyzing a trapping set and a random set of codewords to generate a distance value for each trapping set, and ordering the trapping sets by the distance value. Distance values may be determined for each trapping set by tracking a vote count wherein a correct decode at a certain noise level produces a “right” vote and an incorrect decode at a certain noise level produces a “left” vote. A certain threshold number of “left” votes terminates processing at that noise level.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: March 10, 2015
    Assignee: LSI Corporation
    Inventors: Denis Vladimirovich Zaytsev, Denis Vasilievich Parfenov, Yang Han, Ivan Leonidovich Mazurenko, Dmitry Nicolaevich Babin
  • Patent number: 8977944
    Abstract: In one embodiment, a system includes a memory, and a memory controller coupled to the memory via an address bus, a data bus, and an error code bus. The memory stores data at an address and stores an error code at the address. The error code is generated based on a function of the corresponding data and address.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: March 10, 2015
    Assignee: Cavium, Inc.
    Inventors: Aseem Maheshwari, Michael S. Bertone, Richard E. Kessler
  • Patent number: 8972837
    Abstract: Methods and apparatus are provided for reading and writing data in q-level cells of solid-state memory, where q>2. Input data is encoded into codewords having N qary symbols, wherein the symbols of each codeword satisfy a single-parity-check condition. Each symbol is written in a respective cell of the solid state memory by setting the cell to a level dependent on the qary value of the symbol. Memory cells are read to obtain read signals corresponding to respective codewords. The codewords corresponding to respective read signals are detected by relating the read signals to a predetermined set of N-symbol vectors of one of which each possible codeword is a permutation.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Thomas Mittelholzer, Nikolaos Papandreou, Charalampos Pozidis
  • Patent number: 8966345
    Abstract: Embodiments of apparatus, methods, systems, and devices are described herein for selective error correction in memory with multiple operation modes. In various embodiments, an error correction block (e.g., of a memory controller) may be configured to perform error correction on data read from a first portion of a memory based on a corresponding error correction code read from a second portion of the memory, and to calculate and store the error correction code. A control block coupled to the error correction block may be configured to selectively enable/disable the error correction block to perform the error correction, and to calculate and store the error correction code, based at least in part on a current operation mode of the memory.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: February 24, 2015
    Assignee: Intel Corporation
    Inventors: Christopher B. Wilkerson, Alaa R. Alameldeen, Shih-Lien L. Lu
  • Patent number: 8924835
    Abstract: Aspects of the disclosure pertain to a system and method for promoting improved error detection efficiency in a Content-Addressable Memory (CAM). The system and method provide CAM continuous error detection with interleave parity. The system continuously monitors for changes in cell contents and, when (e.g., as soon as) a soft error occurs, the error detection output bit for that entry will change, causing an error flag at chip level. The system can then immediately stop compare operations and rewrite the failing entry. Separate read operations are not needed to check for errors, thereby decreasing overall dynamic power usage and increasing possible search frequency for the system.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: December 30, 2014
    Assignee: LSI Corporation
    Inventors: Gordon W. Priebe, Carl W. Swanson, David B. Grover, Christopher D. Browning
  • Patent number: 8910030
    Abstract: A parity pattern defines a repeated distribution of parity blocks within a distributed parity disk array (“DPDA”). The parity pattern identifies on which disks the parity block or blocks for a stripe are located. When a new disk is added to the DPDA, the parity pattern is modified so that the distribution of parity blocks within the parity pattern is even. Parity blocks within the DPDA are then redistributed to conform with the modified parity pattern.
    Type: Grant
    Filed: April 22, 2013
    Date of Patent: December 9, 2014
    Assignee: NetApp, Inc.
    Inventor: Atul Goel
  • Patent number: 8902893
    Abstract: A packet processing apparatus includes a packet identifying unit and a packet modifying unit. The packet identifying unit is utilized for receiving a plurality of packets and checking identification information and data length information which are derived from the received packets to identify first packets from the received packets. The packet modifying unit is coupled to the packet identifying unit, and is utilized for checking payloads of the first packets to identify second packets from the first packets, where each of the second packets has specific data included in a payload thereof, and for modifying at least the payload of each of the second packets.
    Type: Grant
    Filed: December 8, 2009
    Date of Patent: December 2, 2014
    Assignee: Mediatek Inc.
    Inventors: Chin-Wang Yeh, You-Min Yeh, Rong-Liang Chiou, Yu-Hsiung Deng, Ching-Chieh Wang
  • Patent number: 8887024
    Abstract: Modulation and coding schemes are provided for improved performance of wireless communications systems to support services and applications for terminals with operational requirements at relatively low Es/N0 ratios and terminals at relatively high Es/N0 ratios. The new modulation and coding schemes provide new BCH codes, low density parity check (LDPC) codes and interleaving methods. The modulation and coding schemes also provide new modulation signal constellations.
    Type: Grant
    Filed: February 10, 2013
    Date of Patent: November 11, 2014
    Assignee: Hughes Network Systems, LLC
    Inventors: Mustafa Eroz, Lin-Nan Lee
  • Patent number: 8832528
    Abstract: In various embodiments, an apparatus, system, and method may increase data integrity in a redundant storage system. In one embodiment, a request is received for data stored at a storage system having a plurality of storage elements, where one or more of the plurality of storage elements include parity information. A determination is made that one of the plurality of storage elements is unavailable, the unavailable storage element being a functional storage element and including at least a portion of the data. Responsive to the determination, the data is reconstructed based on at least a portion of the parity information and data from one or more of the plurality of storage elements other than the unavailable storage element; a response is provided to the request such that the response includes the reconstructed data.
    Type: Grant
    Filed: May 18, 2010
    Date of Patent: September 9, 2014
    Assignee: Fusion-io, Inc.
    Inventors: Jonathan Thatcher, David Flynn, Joshua Aune, Jeremy Fillingim, Bill Inskeep, John Strasser, Kevin Vigor
  • Patent number: 8812933
    Abstract: A memory system includes a nonvolatile memory device and a memory controller configured to control the nonvolatile memory device and configured to provide the nonvolatile memory device with error flag information including error location information of an error of data read from the nonvolatile memory device.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: August 19, 2014
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventors: Sang-Hyun Joo, Kitae Park, Sangyong Yoon, Jinman Han
  • Patent number: 8799745
    Abstract: A controller of a storage control apparatus creates a fixed value, which is one or higher values conforming to a prescribed data pattern, with respect to first data, which is smaller than the size of a storage area of a storage device, creates a guarantee code related to a data area comprising the first data and the fixed value, and writes the data group comprising the data area and the guarantee code to the storage area. The controller reads a data group from the storage area, and determines whether or not more errors than the number of errors correctable by the guarantee code are included in this data group. In a case where the result of this determination is affirmative, the controller determines whether or not an error exists in the fixed value inside the data group.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: August 5, 2014
    Assignee: Hitachi, Ltd.
    Inventor: Hideyuki Koseki
  • Patent number: 8762818
    Abstract: System and methods for performing decoding error detection in a storage device are provided. Data bits of a data polynomial may be retrieved from a storage device. The data bits may be arranged in a first order. Error correction may be performed on the retrieved data bits of the data polynomial to produce an error polynomial based on error correction parity information encoded in the data polynomial. Bits of the error polynomial are arranged in a second order that is reverse to the first order. A first remainder of the error polynomial may be computed based on data bits corresponding to the data polynomial arranged in the second order. An error in the error polynomial may be detected based on the computed first remainder.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: June 24, 2014
    Assignee: Marvell International Ltd.
    Inventor: Fei Sun
  • Publication number: 20140173378
    Abstract: A processor system as presented herein includes a processor core, cache memory coupled to the processor core, a memory controller coupled to the cache memory, and a system memory component coupled to the memory controller. The system memory component includes a plurality of independent memory channels configured to store data blocks, wherein the memory controller controls the storing of parity bits in at least one of the plurality of independent memory channels. In some implementations, the system memory is realized as a die-stacked memory component.
    Type: Application
    Filed: December 19, 2012
    Publication date: June 19, 2014
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: James M. O'Connor, Vilas K. Sridharan, Gabriel H. Loh
  • Patent number: 8707110
    Abstract: Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: April 22, 2014
    Assignee: Rambus Inc.
    Inventors: Ian Shaeffer, Craig E. Hampel
  • Patent number: 8694866
    Abstract: MDS (maximum distance separable) array codes are widely used in storage systems to protect data against erasures. The rebuilding ratio problem is addressed and efficient parity codes are proposed. A controller as disclosed is configured for receiving configuration data at the controller that indicates operating features of the array and determining a parity code for operation of the array according to a permutation, wherein the configuration data specifies the array as comprising nodes defined by A=(ai,j) with size rm×k for some integers k,m, and wherein for T={v0 , . . . , Vk-1} ?Zrm a subset of vectors of size k, where for each v=(v1, . . . , vm)?T, gcd (v1, . . . , vm, r), where gcd is the greatest common divisor, such that for any l, 0?l?r?1, and v ?T, the code values are determined by the permutation fvl:[0,rm?1]?[0,rm?1]by fvl(x)=x+lv.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: April 8, 2014
    Assignee: California Institute of Technology
    Inventors: Itzhak Tamo, Zhiying Wang, Jehoshua Bruck
  • Publication number: 20140089755
    Abstract: Method and apparatus to efficiently detect/correct memory errors. A command and an address associated with a data transaction may be received. Parity information associated with the command/address may be received. In response to detecting a parity error, a data array of a memory device may be locked. An indicator indicating the parity error may be sent. A first portion of a memory page to store data may be reserved. A second portion of the memory page to store error correction codes associated with the data may be reserved. The second portion's size may equal or exceed the error correction code capacity needed for the maximum possible data stored in the first portion. A cache line of data may be stored in the first portion. An error correction code associated with the cache line of data may be stored in the second portion.
    Type: Application
    Filed: September 27, 2012
    Publication date: March 27, 2014
    Inventors: Shveta KANTAMSETTI, Antonio JUAN, Hoi M. NG, Warren R. MORROW, Isaac HERNANDEZ, Pau CABRE, Thomas S. NG, Tsun Ho LIU, Rongchun SUN, Jessica LEUNG, Mohamedsha MALIKANSARI, Henry STRACOVSKY
  • Publication number: 20140089769
    Abstract: Aspects of the disclosure pertain to a system and method for promoting improved error detection efficiency in a Content-Addressable Memory (CAM). The system and method provide CAM continuous error detection with interleave parity. The system continuously monitors for changes in cell contents and, when (e.g., as soon as) a soft error occurs, the error detection output bit for that entry will change, causing an error flag at chip level. The system can then immediately stop compare operations and rewrite the failing entry. Separate read operations are not needed to check for errors, thereby decreasing overall dynamic power usage and increasing possible search frequency for the system.
    Type: Application
    Filed: September 27, 2012
    Publication date: March 27, 2014
    Applicant: LSI Corporation
    Inventors: Gordon W. Priebe, Carl W. Swanson, David B. Grover, Christopher D. Browning
  • Patent number: 8683292
    Abstract: A multiple access scheme is described. One or more encoders are configured to encode a plurality of bit streams using Low Density Parity Check (LDPC) coding. The bit streams correspond to a respective plurality of terminals. The plurality of bit streams are converted to provide a multiple access scheme for the terminals.
    Type: Grant
    Filed: March 9, 2013
    Date of Patent: March 25, 2014
    Assignee: Hughes Network Systems, LLC
    Inventors: Lin-Nan Lee, Mustafa Eroz
  • Patent number: 8683308
    Abstract: Each of (n?1) 2-bit checking units, where n is an integer larger than or equal to 4, receives n-bit redundant encoded data generated from 1-bit input data, and outputs 2-bit check data based on a result of comparison between bits of the encoded data, combinations of the bits differing in each comparison. An all-bit checking unit outputs all-bit check data based on exclusive ORs of all-bit of the encoded data. An error detecting unit detects errors in the encoded data on the basis of the (n?1) sets of 2-bit check data and the all-bit check data, and outputs the input data on the basis of the result of error detection.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: March 25, 2014
    Assignee: Fujitsu Limited
    Inventors: Nina Tsukamoto, Toshihiro Tomozaki, Terumasa Haneda
  • Patent number: 8671330
    Abstract: According to one embodiment, a storage device includes an error detector, a check module, and a replacement module. The error detector detects a bit error that occurs in entry data related to conversion to a physical address corresponding to a logical address based on an error detecting code assigned to the entry data. The check module checks, based on data obtained by inverting one bit among all bits of the entry data and on data read out from the physical address indicated by the obtained data, whether or not the obtained data is normal entry data. The replacement module replaces the entry data where the bit error is detected with the checked normal entry data.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: March 11, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yutaka Komagome
  • Patent number: 8659959
    Abstract: An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: February 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kyu-Hyoun Kim, George L. Chiu, Paul W. Coteus, Daniel M. Dreps, Kevin C. Gower, Hillery C. Hunter, Charles A. Kilmer, Warren E. Maule