Abstract: Techniques are disclosed for processor synchronization within a reconfigurable computing environment for processor array redundancy. Processing elements are configured within a reconfigurable fabric to implement two or more redundant processors, where the two or more redundant processors are enabled for coincident operation. An agent is loaded on each of the two or more redundant processors, where the agent performs a function requiring data validation. The agent is fired on each of the two or more redundant processors to commence coincident operation. The coincident operation can include a lockstep operation. An output data result from each of the two or more redundant processors is compared to enable a data validation result. The data validation result is propagated. The propagating the data validation result can be based on comparing valid output data or can be based on comparing invalid output data.

Abstract: An address and a control data accessed when the CPU performs the program calculation in the control data memory of the control system controller are transmitted to the standby system controller, in the standby system controller, the control data transmitted from the control system controller to the address transmitted from the control system controller before the program calculation of the CPU of the standby system controller is expanded, the control data equalization of the control system controller and the standby system controller is performed, the control data is efficiently transmitted from the control system controller to the standby system controller, thus, the processing performance of the duplexing process control device is improved.

Abstract: An error management system may be provided. The error management system may include an error analysis unit configured to generate error correction counting values by counting error correction occurrences in a plurality of management blocks and generate permanent error block information for defining whether errors generated in the plurality of management blocks are a permanent error or a temporary error by comparing the error correction counting values and at least one reference value. The error management system may include a block control unit configured to replace an address signal with a new address signal when a management block selected according to the address signal among the plurality of management blocks is previously designated in the permanent error block information.

Abstract: Systems and computer-implemented methods for executing a command in an autonomous vehicle are provided, including the steps of: generating at least three independent vehicle data-sets; transmitting the at least three independent vehicle data-sets to at least three command determination modules, respectively; and, at each one of the at least three command determination modules, using the respective received vehicle data-set to determine a command. The method further includes the step of, during a monitoring phase, comparing the commands to each other to determine if any one of these commands is desynchronized from the other commands. If a command is determined to be desynchronized from the other commands during the monitoring phase, the method includes the step of excluding the command determination module which determined the desynchronized command.

Abstract: A post package repair (PPR) device is disclosed, which relates to a technology for masking a rupture operation in case of a post package repair (PPR) operation. The post package repair (PPR) device includes: a plurality of bank groups, each including a fuse indicating repair information, configured to share a predetermined number of fuses; a resource detection unit configured to generate a resource signal which determines whether the fuses from among the plurality of bank groups are available; and a masking controller configured to output a masking signal which prevents repeated execution of a rupture operation when there is no unused fuse in response to the resource signal and a bank active signal.

Abstract: Circuitry, systems and methods for testing integrated circuits for the presence of anomalies. Techniques include applying a plurality of inputs to an integrated circuit under test to obtain a first plurality of measurements at least partially characterizing power leakage in the integrated circuit under test, encode the first plurality of measurements, by computing a plurality of random linear combinations of measurements in the first plurality of measurements, to obtain a second plurality of encoded measurements determining whether the integrated circuit under test contains at least one anomaly based, at least in part, on the second plurality of encoded measurements.

Abstract: In a Forward Error Correction (FEC) technique, parity vectors are computed such that: each parity vector spans a set of frames; a subset of bits of each frame is associated with parity bits in each parity vector; and a location of parity bits associated with one frame in one parity vector is different from that of parity bits associated with the frame in another parity vector. Values of decoded bits of a first frame are deduced from known parity bits of a first parity vector having an effective length of one frame. For parity vectors having, an effective length greater than one frame, a Log Likelihood Ratio of each unknown parity bit associated with the first frame is updated based on known and unknown parity bits of each parity vector. The first frame is decoded using the deduced bit values and the updated LLR values.

Abstract: A signal selection and fault detection system is provided. The system includes four input equalization circuits each configured to receive an input signal from an associated sensor, wherein the input signal is indicative of a parameter measured by the associated sensor, and output an equalized signal based on the received input signal. The system further includes a five-input output selection circuit coupled to the four input equalization circuits, the five-input output selection circuit configured to receive an equalized signal from each of the four input equalization circuits, receive a previous frame output signal, and select an output signal from the four equalized signals and the previous frame output signal.

Abstract: A mechanism is described for achieving high memory reliability, availability, and serviceability (RAS) according to one embodiment of the invention. A method of embodiments of the invention includes detecting a permanent failure of a first memory device of a plurality of memory devices of a first channel of a memory system at a computing system, and eliminating the first failure by merging a first error-correction code (ECC) locator device of the first channel with a second ECC locator device of a second channel, wherein merging is performed at the second channel.

Abstract: A semiconductor memory apparatus including a test circuit configured for generating compressed data by comparing and compressing data stored in a plurality of memory cells inside a memory bank during a first test mode, and configured for outputting the compressed data as test data to an input/output pad through one selected global line during the first test mode, and the test circuit is configured for transmitting the compressed data to a plurality of global lines during a second test mode, combining the compressed data loaded in the respective global lines during the second test mode, and outputting the combination result as the test data to the input/output pad during the second test mode.

Abstract: A third party that performs data stream computation is requested to return not only the solution to the computation, but also “annotations” to the original data stream. The annotations are then used by the data owner (in actuality, a “verifier” associated with the data owner) to check the results of the third party's computations. As implemented, the verifier combines the annotations with the original data, performs some computations, and is then assured of the correctness of the provided solution. The cost of verification is significantly lower to the data owner than the cost of fully processing the data “in house”.

Abstract: Systems and methods for 1553 bus operation self checking are provided. In one embodiment, a fault tolerant computer comprises a self-checking processor pair that includes a master processor, a checking processor, and self-checking pair logic; a 1553 bus transceiver; and a device comprising 1553 self-checking logic coupled between the self-checking processor pair and the 1553 bus transceiver, wherein the 1553 self-checking logic manages data communication between the 1553 bus transceiver and the self-checking processor pair. The 1553 self-checking logic includes a primary logic and a secondary logic that operate in lock-step. When the 1553 self-checking logic writes data to the 1553 bus transceiver, the 1553 self-checking logic compares a first 1553 formatted message generated by the primary logic to a second 1553 formatted message generated by the secondary logic, and generates an error indication when the first 1553 formatted message does not match the second 1553 formatted message.

Abstract: A data transmitting device determines a coding rate used to perform error correction coding processing for data transmitted to a data receiving device based on information relating to the function of concealing an error occurring in data transmitted from the data transmitting device, the function being provided in the data receiving device. Then, the data transmitting device performs the error correction coding processing for data transmitted to the data receiving device based on the determined coding rate, and transmits the data subjected to the error correction coding processing to the data receiving device.

Abstract: A memory controller includes first and second interface controllers configured to exchange data with external devices, and an internal block connected between the first and second interface controllers. The first and second interface controllers exchange data received from the external devices and at least one parity bit corresponding to the received data through the internal block.

Abstract: An apparatus and method for soft-error resilience or correction with the ability to perform a manufacturing test operation, a slow-speed snapshot operation, a slow-speed signature analysis operation, an at-speed signature analysis operation, a defect tolerance operation, or any combination of the above operations. In one embodiment, an apparatus includes a system circuit, a shadow circuit, and an output joining circuit for soft-error resilience. The output joining circuit coupled to the output terminals of the system circuit and the shadow circuit includes at least an S-element for defect tolerance. In another embodiment, an apparatus includes a system circuit, a shadow circuit, a debug circuit, and an output joining circuit for soft-error correction. The output joining circuit coupled to the output terminals of the system circuit, the shadow circuit, and the debug circuit includes at least a V-element for defect tolerance.

Abstract: Methods and apparatus are provided for verifying the integrity of a signal transmitted across a multiple rail data bus. The method and apparatus provide for independently processing a signal by a first processor and a second processor, the first and second processors being connected in parallel thereby generating a first processed signal and a second processed signal. Each of the processed signals is split into a first component sequence and a second component sequence, the first component sequences being different from the second component sequences. It is then determined that the first component sequences are not identical and that the second component sequences are not identical. If either of the first component sequences is not identical, or if either of the second component sequences is not identical, then an error signal is transmitted to a receiving device via a first or second rail of the bus.

Abstract: A wireless communication apparatus that includes a first format detecting unit detecting a format by executing signal processing on a preamble of a received packet before decoding, an estimating unit using the preamble to carry out multiple types of estimations, and a decoding unit decoding the received packet in accordance with the detected format based on the estimations. The apparatus further includes a second format detecting unit detecting the format of the received packet based on decoded control information in the preamble of the received packet, an error detection determination unit, when the format detected by the first format detecting unit differs from the format detected by the second format detecting unit, determining that the format detected by the first format detecting unit is an error, and a control unit controlling operations of the estimating unit and the decoding unit based on a determined result.

Abstract: A built-in self test circuit includes a pattern generator, an elastic buffer, a symbol detector, and a comparison unit. A pattern generator generates a first test pattern to test a port under test and then a result pattern is gotten and stored in the elastic buffer. The symbol detector detects if a starting symbol exists in the test result pattern. If it exists, a second test pattern is generated to be compared with the test result pattern. As a result, a reliability of data transmission of the port under test is determined.

Abstract: A wireless communication apparatus performs data communication with a base station using a plurality of transport channels (TRCHs) that share a frequency band, and selects a reference TRCH using coding schemes of data to be transmitted using the TRCHs. After that, the wireless communication apparatus performs outer loop control so that a block error rate (BLER) of the data to be transmitted using the reference TRCH is set to a target BLER.

Abstract: This invention provides a system and method that can employ a low-instruction-per-second (lower-power), highly parallel processor architecture to perform the low-precision computations. These are aggregated at high-precision by an aggregator. Either a high-precision processor arrangement, or a low-precision processor arrangement, employing soft-ware-based high-precision program instructions performs the less-frequent, generally slower high-precision computations of the aggregated, more-frequent low-precision computations. One final aggregator totals all low-precision computations and another high-precision aggregator totals all high-precision computations. An equal number of low precision computations are used to generate the error value that is subtracted from the low-precision average. A plurality of lower-power processors can be arrayed to provide the low-precision computation function.

Abstract: A method for measuring multimedia communication quality is disclosed. The multimedia video communication quality may be objectively reflected through the embedment and extraction of digital watermark under a precondition that the quality of the multimedia video data is not obviously affected. In the invention, each frame of the multimedia video data is uniformly divided into blocks of equal size and watermark data is embedded in each of the blocks, so that the watermark may be uniformly distributed. The multimedia video data are divided into groups, and the watermark is embedded in a part of the frames with equal interval between the frames in each group to reduce the effect of the watermark on the data. The watermark information is directly embedded in the spatial domain of the original video data.

Abstract: Processors, microprocessors and logical block systems and methods, error detection systems and methods, and integrated circuits are disclosed. In an embodiment, a logic-based computing system includes a first processing core; a second processing core generated from the first processing core and including an inverted logical equivalent of the first processing core such that an output of the second processing core is a complement of an output of the first processing core; and comparator logic coupled to receive the outputs of the first and second processing cores as inputs and provide an error output if the output of the second processing core is not the complement of the output of the first processing core.

Abstract: A built-in self test circuit includes a pattern generator, an elastic buffer, a symbol detector, and a comparison unit. A pattern generator generates a first test pattern to test a port under test and then a result pattern is gotten and stored in the elastic buffer. The symbol detector detects if a starting symbol exists in the test result pattern. If it exists, a second test pattern is generated to be compared with the test result pattern. As a result, a reliability of data transmission of the port under test is determined.

Abstract: Methods and apparatus are provided for verifying the integrity of a signal transmitted across a multiple rail data bus. The method and apparatus provide for independently processing a signal by a first processor and a second processor, the first and second processors being connected in parallel thereby generating a first processed signal and a second processed signal. Each of the processed signals is split into a first component sequence and a second component sequence, the first component sequences being different from the second component sequences. It is then determined that the first component sequences are not identical and that the second component sequences are not identical. If either of the first component sequences is not identical, or if either of the second component sequences is not identical, then an error signal is transmitted to a receiving device via a first or second rail of the bus.

Abstract: The correction of errors in the transport and processing of qubits makes use of logical qubits made up of a plurality of physical qubits. The process takes place on a spatial array of physical qubit sites arranged with a quasi-2-dimensional topology having a first line of physical qubit sites and second line of physical qubit sites, where the first and second lines are arranged in parallel, with the sites of the first line in registration with corresponding sites in the second line. Between the first and second lines of physical qubit sites are a plurality of logic function gates, each comprised of a first physical qubit gate site associated with a first physical qubit site in the first line, and a second physical qubit gate site associated with the physical qubit site in the second line that corresponds to the first physical qubit site.

Abstract: An integrity unit can be calculated from a first data unit, and a first storage device can be requested to store the first data unit. A second storage device, which can be separate from and/or a different type of device from the first storage device, can be requested to store metadata, which includes the integrity unit, in nonvolatile memory. Also, a second data unit can be received from the first storage device in response to a request for the first data unit. The integrity unit can be received from the second storage device, and the second data unit and the integrity unit can be analyzed to determine whether the second data unit matches the first data unit. Alternatively, a first integrity unit can be stored in a metadata region of a nonvolatile memory block, where the block also stores the data from which the first integrity unit was calculated.

Abstract: A method and apparatus to read information from an information storage medium using a read channel, where that read channel includes a data cache. The invention generates an analog waveform comprising the information, and provides that analog waveform to a read channel, and generates a digital signal from that analog waveform using one or more first operating parameters. The method error corrects that digital signal at an actual error correction rate, and determines if the actual error correction rate is greater than an error correction rate threshold. If the actual error correction rate exceeds the error correction rate threshold, then the method captures the digital signal, stores that captured data in a data cache, reads that digital signal from the cache, generates one or more second operating parameters, and provides those one or more second operating parameters to the read channel.

Abstract: This invention provides a system and method that can employ a low-instruction-per-second (lower-power), highly parallel processor architecture to perform the low-precision computations. These are aggregated at high-precision by an aggregator. Either a high-precision processor arrangement, or a low-precision processor arrangement, employing soft-ware-based high-precision program instructions performs the less-frequent, generally slower high-precision computations of the aggregated, more-frequent low-precision computations. One final aggregator totals all low-precision computations and another high-precision aggregator totals all high-precision computations. An equal number of low precision computations are used to generate the error value that is subtracted from the low-precision average. A plurality of lower-power processors can be arrayed to provide the low-precision computation function.

Abstract: Extra traffic paths are provided in a communication network including at least two protection channels associated to respective transmission channels. Each protection channel admits an active state for carrying, in the presence of a failure in the associated transmission channel, traffic to be carried by the associated transmission channel, and a stand-by state, wherein the protection channel is adapted to carry extra traffic. The protection channels are run in a sub-network connection protection scheme, whereby one of the protection channels in its stand-by state is adapted to ensure recovery of extra traffic carried by the other protection channel while the other protection channel is switched to its active state or is subject to failure.

Abstract: A logic circuit comprises a logic module comprising a functional logic block supplying a functional result, and a functional flip-flop receiving the functional result and supplying a synchronous result. A module for checking the functional logic block comprises a checking logic block executing the same logic function as the functional logic block and supplying a checking result, checking synchronous flip-flops for applying data present at the input of the functional logic block to the input of the checking logic block, and means for comparing the functional result and the checking result and for supplying a first error signal.

Abstract: A system and method for communicating information in a wireless cooperative relay network of nodes, the nodes including a source, a set of relays, and a destination. The source broadcasts a code word encoded as a data stream using a rateless code. The relays receive the data stream, decode the data stream to recover the code word, and reencode and transmit the recovered code word as the data stream with the rateless code. The destination receives and decodes the reencoded data streams to recover the code word.

Abstract: Techniques are provided for selecting status data. Redundant views are obtained from multiple synchronous redundant devices. It is determined that the redundant views from the multiple synchronous redundant devices are conflicting. A redundant view score is calculated for each of the redundant views based on one or more characteristics from each of at least two characteristic types, wherein the characteristics are associated with weighted scores. One of the redundant views is selected based on the calculated redundant view score for each of the redundant views.

Abstract: A packet transmission device that is connected to a plurality of communication lines, and transmits a packet received, includes a failure detecting unit that monitors a condition of the communication lines, and detects a failure in the communication lines; and a packet transmitting unit that transmits, when the failure detecting unit detects a failure in a communication line, and when a packet having a same transmission-destination address as an address corresponding to a port of the communication line in which the failure has been detected is received, the packet from all preset ports.

Abstract: Provided is a compensating device for a received data can be used in a wide application by a single apparatus for various wiring configurations and transmission media.

Abstract: A method for monitoring the availability of a data processing system is proposed. For example, the system runs a management application, which involves the periodic transmission of blocks of data from multiple local computers to a central computer. In the method of the invention, whenever a block of data must be transmitted by a generic local computer, an expected transmission delay of a next block of data is estimated; this information is then attached to the block of data. As a result, the central computer receiving the updated block of data can calculate an expected receiving time of the next block of data accordingly. If the next block of data is not received in due time, the central computer determines a failure of the local computer. Preferably, the central computer also scans a subset of ports of the local computer, so as to ascertain whether the problem is due to a temporary unavailability of the application or to an actual crash of the local computer.

Abstract: A parallel processing apparatus dynamically switching over a circuit configuration includes a plurality of computing elements, a network establishing connections between the plural computing elements, a plurality of selectors provided corresponding to the plurality of computing elements within the network and controlling outputs from the computing elements, first local memories stored with data used for the operations by the computing elements and connected to the respective computing elements, and second local memories stored with data used for controlling the connections by the selectors and connected to the respective selectors.

Abstract: In a communication system 10, a method and apparatus provide for decoding a sequence of turbo encoded data symbols. The channel nodes Rx, Ry and Rz are updated based on a received channel output, and the outgoing messages from symbol nodes (701, 707, 708) are initialized. The symbol nodes symbol nodes (701, 707, 708) are in communication with the channel nodes Rx, Ry and Rz. Updates of computational nodes C (704) and D (706) at different time instances are performed in accordance with a triggering schedule.

Abstract: A memory device uses data compression to read data from an array of the memory during testing. The compressed data is either a logic one, logic zero or tri-state, depending upon the data read from the array. Output drivers of the memory are placed in a tri-state condition in response to a detected read error. Non-compressed internal I/O lines are used during testing to provide control signals to the driver circuitry to selectively place drivers in the tri-state mode. Once a tri-state is detected four columns of memory cells can be replaced with four columns of redundant memory cells without requiring additional non-compressed testing.

Abstract: In one embodiment, a method for identifying links in a system under evaluation includes assigning unique identifiers to drivers of the system, emitting the identifiers from the drivers on associated links, collecting data received by receivers of the system, and comparing the driver identifiers with the data received by the receivers to determine which drivers are linked to which receivers.

Abstract: A logic circuit comprises a logic module comprising a functional synchronous flip-flop receiving a functional result comprising several bits in parallel, and supplying a synchronous result. A module for checking the integrity of the functional flip-flop comprises a first coding block receiving the functional result and supplying a first code, a second coding block receiving the synchronous result and supplying a second code, a checking synchronous flip-flop receiving the first code and supplying a third code, and a comparator for comparing the second code with the third code and for supplying a first error signal.

Abstract: A method of lost-cycle measurement using a cycle counter. In some embodiments, the lost-cycle measurement method comprises: getting a current cycle counter value; finding a number of elapsed cycles between the current cycle counter value and a preceding cycle counter value; determining whether the number of elapsed cycles is indicative of lost cycles; and repeating.

Abstract: One embodiment of the present invention provides a system that facilitates detecting and correcting errors. The system operates by receiving a data packet comprised of p words on a communication pathway, wherein each bit of a word is received on a separate data line in a set of data lines that comprise the communication pathway. The system also receives a time signature t on the communication pathway, wherein t contains per-bit error information for the p words in the data packet. As the data packet is received, the system performs an error-detection operation on each data bit of the data packet in parallel, wherein the error-detection operation generates per-bit error information for each bit position across the p words in the data packet. Finally, the system compares the generated per-bit error-information with the corresponding per-bit error information in the time signature t to determine if there exists an error.

Abstract: Disclosed is a method and system for modeling invariant relationships between flow intensity measurements in a distributed system. In the method, a measurement is randomly selected from a plurality of flow intensity measurements. The method searched for relationships between the randomly selected measurement and each remaining one of the plurality of flow intensity measurements, and each of the flow intensity measurements having a relationship with the randomly selected measurement is grouped into a cluster with the randomly selected measurement. The method than determines relationships between all of the flow intensity measurements in the cluster. This method is repeated with the remaining flow intensity measurements until all of the flow intensity measurements are grouped into a cluster.

Abstract: A method and an apparatus for requesting packet redelivery in a mobile ad hoc network environment. The method includes receiving a first packet periodically broadcasted, extracting packet delivery information of a second packet from the first packet, the second packet including data generated by an application program, determining loss of the second packet based on the packet delivery information, and broadcasting a request packet to request redelivery of the second packet, when it is determined that the second packet is lost.

Abstract: A cryptographic system includes encryption logic that is configured to encrypt input data by performing a mask operation on the input data using an address associated with the input data.

Abstract: A computer system which may allow a centerplaneless design. The computer system may include various client circuit boards including processor circuit boards, memory circuit boards and switch circuit boards. The processor circuit boards may each include at least one processor, while the memory circuit boards may each include memory which is accessible by each processor. The switch circuit boards may include a plurality of detachable connectors for interconnecting each of the processor circuit boards to each of the memory circuit boards. At least one of the switch circuit boards may convey redundant memory access information. Each of the boards may be hot swappable.

Abstract: A new method for the detection and correction of environmentally induced functional interrupts (or “hangs”) induced in computers or microprocessors caused by external sources of single event upsets (SEU) which propagate into the internal control functions, or circuits, of the microprocessor. This method is named Hardened Core (or H-Core) and is based upon the addition of an environmentally hardened circuit added into the computer system and connected to the microprocessor to provide monitoring and interrupt or reset to the microprocessor when a functional interrupt occurs. The Hardened Core method can be combined with another method for the detection and correction of single bit errors or faults induced in a computer or microprocessor caused by external sources SEUs.

Abstract: A system and method to transmit and receive forward error corrected data in a diversity communications system is provided. Using diversity techniques, multiple copies of the transmitted data are received with varying degrees of corruption due to channel impairments. In addition to the multiple copies of forward error corrected data, an additional data set of implicit parity bits is used in the data decoding process, wherein the reliability of these parity bits is assumed to be very high. The implicit parity bits are not transmitted or received by the system, but are introduced in the receivers' decoding process. These implicit parity bits add an extra highly reliable dimension of forward error correction codes. Therefore the present system and methods provide an improved data decoding process with high coding gain and channel efficiency, while minimizing system resources.

Abstract: The present invention relates to a method and an universal module for testing functions of communication ports of a computer, including both parallel port and serial port. The module includes a logic control unit and connects to a communication port (a serial or a parallel port) for testing the open or short conditions of the ports through walk 1? and a walk 0? logic tests. The testing module not only can check the open condition of a parallel port, but also can check the open and short conditions of a parallel port and a serial port.

Abstract: A new method for the detection and correction of environmentally induced functional interrupts (or “hangs”) induced in computers or microprocessors caused by external sources of single event upsets (SEU) which propagate into the internal control functions, or circuits, of the microprocessor. This method is named Hardened Core (or H-Core) and is based upon the addition of an environmentally hardened circuit added into the computer system and connected to the microprocessor to provide monitoring and interrupt or reset to the microprocessor when a functional interrupt occurs. The Hardened Core method can be combined with another method for the detection and correction of single bit errors or faults induced in a computer or microprocessor caused by external sources SEUs.