Abstract: A method of testing a plurality of memory blocks of an integrated circuit in parallel, wherein each memory block comprising data bit storage cells in an array of rows and columns, and wherein each row of storage cells is addressable to store a word of data bits having a width determined by the number of columns of the array, comprises the steps of: writing test data words in parallel to the rows of the plurality of memory blocks; reading out test data words in parallel from the rows of the plurality of memory blocks to a corresponding plurality of on-chip data word comparators; presenting corresponding expected data words in parallel to the plurality of on-chip data word comparators for comparison with the read out data words of the corresponding memory blocks; concurrently comparing corresponding data bits of the read out data words and expected data words in corresponding data bit comparators to generate a column status bit for each data bit comparison; latching the column status bit of a mismatch bit compa

Abstract: The systems and methods described herein provide a redundant communication path. The systems and methods can provide a second source for the same data under many circumstances. These circumstances can include, for example, 1) when data incurs errors during transmission in the communication link network, 2) when a communication link in the communication link network experiences transient blockage, 3) when a communication link experiences prolonged or indefinite blockage, and 4) when an optical transceiver unit within the communication link network experiences a hardware failure and is unable to perform its tasks.

Abstract: Methods and systems for streaming data in a network. Whether the network is experiencing high packet loss may be determined by a rate control module. If high packet loss is experienced, data is encoded into multiple streams by a coder using temporal domain partitioning. If high packet loss is not experienced, then data may is encoded by using frequency domain partitioning. Unequal error protection is applied to each of the streams so more important bit planes in a bit of a stream are provided with more error protection than less important bit planes. The streams are transmitted along, respectively, independent paths to a decoder. The streams are decoded, and errors in the decoded streams are corrected by using information from one or more of the other decoded streams. The decoded corrected streams are reconstructed into the data.

Abstract: A memory device uses data compression to read data from an array of the memory during testing. The compressed data is either a logic one, logic zero or tri-state, depending upon the data read from the array. Output drivers of the memory are placed in a tri-state condition in response to a detected read error. Non-compressed internal I/O lines are used during testing to provide control signals to the driver circuitry to selectively place drivers in the tri-state mode. Once a tri-state is detected four columns of memory cells can be replaced with four columns of redundant memory cells without requiring additional non-compressed testing.

Abstract: In a preferred embodiment, the invention provides a circuit and method for a high reliability triple redundant latch with integrated testability. Three settable memory elements set an identical logical value into each settable memory element. After the settable memory elements are set, three voting structures with inputs from the first, second, and third settable memory elements, determine the logical value held on each of the settable memory elements. Data may be scanned into and out of the second settable memory element. Data is propagated through the buffer into the third settable memory element. The third settable memory element may be used to scan data out of the triple redundant latch. The propagation delay through a latch is the only propagation delay of the triple redundant latch.

Abstract: The invention relates to a receiving circuit for receiving message signals, having a first sampler for converting the message signal into a first sampled signal by a first sampling method, having at least one second sampler connected in parallel with the first sampler for converting the message signal into a second sampled signal by a second sampling method, and having an analyzing unit for decoding the first sampled signal and/or the second sampled signal and checking them for errors.

Abstract: Architecture, circuitry, and methods are provided for programming, writing to, or reading from one or more integrated circuits which may be arranged upon a printed circuit board. Programming and read/write operations can, therefore, be done after integrated circuits are populated upon a printed circuit board to control those integrated circuits using a standard JTAG interface, well-known as the IEEE Std. 1149.1 interface. A shift register used to control one or more electronic subcomponents can be programmed, written to, or read from using JTAG programming languages. However, the shift register, or multiple shift registers, used to control electronic subcomponents need not be JTAG compliant.

Abstract: The present invention provides a word voter for redundant systems with n modules wherein each of these n modules generates a word output. The word voter receives word outputs from each of the n modules. A voter decision is generated by the word voter utilizing a word basis of the word output of each of the n modules. The voter is based on a majority voting principle. The advantage of the present invention is that the word voter can be used to design redundant systems, such as, but not limited to, TMR systems, that are protected against common mode and multiple output failures. In addition, another advantage of the present invention is that is provides for a technique to efficiently design a TMR simplex system. The present invention provides a word voter for hardware systems.

Abstract: The present invention relates to a method of supervising parallel processors in a data system that comprises a first system CP-A and a second system CP-B. The method comprises the steps of: generating a first status word STWA in the first system CP-A and a parallel second status word STWB in the second system CP-B; generating in the first system CP-A a first check code CCA from the first status word STWA; generating in the second system CP-B a second check code CCB from the second status word STWB; sending the first check code CCA from the first system CP-A to the second system CP-B; and recreating the first data word STWA in the second system CP-B by evaluating the first check code CCA, the second check code CCB and the second data word STWB.

Abstract: Fault tolerance is provided in a cross-connect system having only duplicated switch fabrics, instead of the triplicated switch fabrics of the prior art. In addition to the two information switch fabrics, the cross-connect system has a relatively small code switch fabric which switches check-code signals generated at each input interface for each input signal sent to an information switch fabric. Fault-detection and error-recovery components in each output interface (1) generate local check-code signals for each outgoing signals received from an information switch fabric and (2) compare those local check-code signals to the corresponding check-code signal received from the code switch fabric to detect a failure and to select a healthy signal as the output signal for that output interface. In one embodiment, input and output interfaces are clustered, and the corresponding input and output check-code signals are multiplexed, for even greater savings in overhead (e.g.

Abstract: A configuration for testing an integrated semiconductor memory having a control I/O terminal and data I/O terminals, is described, and in which case test signals are prescribed by a test unit. The configuration has a circuit inserted into the signal path between the test unit and the memory. The circuit contains a data writing device for receiving test data from the test unit and for outputting the test data to the memory, a control signal writing device for receiving test control signals of a control channel of the test unit and for outputting the test control signals to the memory, and a reading/coding device for receiving response data signals and response control signals from the memory. The reading/coding device codes the received response data signals with the response control signals and outputs the coded response signals to the test unit.

Abstract: There is provided an image failure detection unit in redundant duplex transmission in which a failure occurring on a regular link is detected at in real time, and the link is instantaneously switched to a normal backup link, thereby preventing any failure from occurring on an output image or reducing the failure. Units for calculation of the image features calculate image features of links A and B, respectively. A comparison unit compares the image features, and then, it is judged that both of the links are normal if there is not difference between the image features. To the contrary, if there is a difference, it is judged that there is a probability of occurrence of a failure on one of the links. Thereafter, a normal/corrupted information memory stores a small region relating to the image features. Units for detection of image feature differences determine image feature differences for the links, respectively.

Abstract: The use of radio technology for transmission of EMERGENCY-OFF, START-, STOP- and process and confirmation signals from industrial processing machines, such as numerically controlled machine tools and robots, by radio is described. There is no need for any additional safety measures for the START and process signals by means of a confirmation signal, provided the control functions satisfy appropriate safety requirements. To this end, safety-relevant signals are physically detected on at least two channels at the transmitter end, the detected data are logically transmitted by at least two channels using a safety technique by radio to a receiver end, and the received data are likewise physically processed and monitored on at least two channels at the receiver end.

Abstract: In a method for data transmission in which the binary original data (D0, . . . , Dm) is transferred from a transmitter to a unit of a receiver (1), selected preferably by means of a binary base address (A0, . . . , An), preferably to a register (80, . . . , 87), where the original data (D0, . . . , Dm) and preferably also the base address (A0, . . . , An) are transmitted through one or several data lines, the inverted original data (inversion data) (D0′, . . . , Dm′) and preferably also the complementary base address (complementary address) (A0′, . . . , An′, Ak) are transmitted by the transmitter. The transmitted inversion data (D0′, . . . , Dm′) and preferably the transmitted complementary address (A0′, . . . , An′, Ak) are inverted in the receiver, the transmitted base address (A0, . . . , An) and the transmitted original data (D0, . . . , Dm) are compared with the inverted complementary address (A0′, . . .

Abstract: A method and apparatus for error checking in a digital scanning device. An error detection pattern is written into each of a plurality of parallel data streams. Each of the data streams is then transmitted through a separate parallel data channel. The error detection patterns in the data streams are then concurrently compared to one another to check for an error condition of the data stream. If the error detection patterns are not received substantially concurrently, an error condition is considered to have occurred. The error detection pattern may comprise end of scan, end of sheet or First-In First-Out (FIFO) buffer data. While all error conditions are false, printing and data transmission continue. Printing and data transmission are terminated if any error condition is true, and an error notification message is generated.

Abstract: The present invention concerns a method of protecting the transmission of cells in a telecommunication system, the method consisting, on the transmitter side, of simultaneously transmitting two identical flows of cells on two distinct physical links and, on the receiver side, of receiving each of the two flows of cells respectively transmitted on the said two links and selecting one of them. The method further consists, on the transmitter side, of inserting, regularly in each of the flows, cells serving as markers and thus delimiting blocks of cells or sets of blocks of cells, and, on the receiver side, of selecting, block after block or group of blocks after group of blocks, the block or group of blocks from the flow of cells which has the fewer transmission errors compared with the block or group of blocks of the same order number in the other flow.

Abstract: Correction of errors and losses in a receiver-driven layered multicast (RLM) of real-time media over a network is augmented using one or more layers of error correction information. Each receiver separately optimizes the quality of received information by subscribing to at least one error correction layer. Ideally, each source layer in a RLM has one or more associated multicasted error correction data streams. Each error correction layer contains information for replacing lost packets from the associated source layer. More than one error correction layer is proposed to correct for lost packets in other error correction layers. Error correction streams are preferably generated using a pseudo-Automatic Repeat Request (ARQ) wherein a broadcaster sends both the source packets in a primary stream and delayed versions thereof in one or more redundant streams. A hybrid technique combines the psuedo-ARQ method with an adaptation of Forward Error Correction (FEC) techniques.

Abstract: The present invention discloses a method and system for testing imbedded logic arrays. An imbedded logic array is first tested for read/write functionality and then a test sequence is run to test the imbedded logic function. The method of the present invention writes a first data pattern to all addresses in an imbedded logic array. Next a second data pattern is written to a specific address followed by a read selecting all addresses concurrently. The output of the imbedded logic array, during this test, is the logic combination of the first data pattern and the second data pattern at the address where the second data pattern was written. By comparing the imbedded logic array output to an expected output the imbedded logic of the array is tested. The present invention anticipates imbedded logic arrays where the expected data output is not a previously written pattern.

Abstract: A radiation hard logic device such as a divider is disclosed. The logic device includes a voter module to determine an error free logic device output, a feedback module to generate a correction signal and provide the signal to a logic correction module to correct the erroneous device output at substantially the same time that the erroneous logic device is presented to the logic correction module.

Abstract: A semiconductor memory device having a parallel data test scheme is disclosed. The semiconductor memory includes an array that is partitioned into array portions with each array portion further divided into sub-arrays and banks. Each array portion providing data bits to a data compression circuit. The data compression circuit includes data compare sections and ripple sections. The data compare sections include data compare circuits that compare the data bits provided by each array portion and each provide a compare output to the ripple sections. The ripple sections are coupled together in series and provide global data compare outputs. A multiplexer selects between a data bit and the global data compare outputs to provide either a data output or a data comparison output to the output pin.

Abstract: An assembly comprising two micro-controllers (MC1, MC2) separately receiving specific and synchronous information (input states) in order to process it and supply respective outputs (S1, S2) and which are connected through links (C1, C2) to make the running of the programs consistent, and a comparator (K) receiving the outputs (S1, S2) from the micro-controllers (MC1, MC2) in order to transmit a signal in the event of nonconformity. A re-writable memory is respectively associated with each micro-controller (MC1, MC2). An interface common to the two micro-controllers (MC1, MC2) is connected to them through a common micro-controller MC3 in order to write the parameterization data for the functions of the two mic-o-controllers (MC1, MC2) by means of the common micro-controller (MC3).

Abstract: A method of checking data integrity in a computer system which includes the acts of: transmitting primary data from a primary device to a primary CRC circuit; transmitting secondary data from a secondary device to a secondary CRC circuit, wherein the primary data and the secondary data are transmitted to their respective CRC circuits concurrently; generating a primary CRC value; generating a secondary CRC value, wherein the primary and secondary CRC values are generated concurrently; and comparing the primary CRC value with the secondary CRC value in order to generate a compare value.

Abstract: An error processing circuit for a receiving location of a system for transferring binary data in the form of pulse sequences, wherein the system has a number of receiving locations connected via a double-line bus having a first line and a second line. The circuit includes a data output, a decoder having three decoder outputs, of which a first decoder output associated with both lines delivers a first decoder output signal dependent on the difference between the potential values of both lines, a second decoder output associated with the first line delivers a second decoder output signal dependent on the difference between the potential value of the first line and a first mean potential value, and a third decoder output associated with the second line delivers a third decoder output signal dependent on the difference between the potential value of the second line and a second mean potential value.

Abstract: The present invention relates to a method of utilizing information made available in a bit error check of data words belonging to instructions read into a processor having a first (11) and a second (11′) calculating unit which operate in parallel with one another, a so-called double processor mode. The processor structure also comprises a third and a fourth calculating unit (13, 13′) intended for continuously checking for possible bit errors in read-in data words, a comparator (14) for comparing output data from parallel operating units (11, 11′), a diagnostic unit (15) adapted to determine which of the calculating units delivered correct output data when detecting a difference in output data in the comparator (14), and a control unit (16) adapted to control that the output data from the processor structure (1) originates from a calculating unit that has delivered correct output data.

Abstract: A read/write preamplifier circuit is provided that includes a fault detecting circuit that detects when two or more read/write preamplifiers are concurrently selected for communicating with their associated data heads and means for notifying the drive controller of that condition. In one embodiment of the invention, the means for notifying the drive controller that two or more preamplifiers are concurrently selected includes a data storage register that is readable by the drive controller and that has a fault flag which is set when two or more preamplifiers are concurrently selected. Also, in one embodiment, the fault detecting circuit includes a fault-detect transistor that drives a predetermined current if the preamplifier is elected. The collectors of the fault-detect transistors of each preamplifier are electronically coupled to each other and to a sensing circuit that senses if the fault-detect transistors of two or more preamplifiers are concurrently driving the predetermined current.

Abstract: A test system for testing a semiconductor device by having a number of test channels (tester pins) corresponding to the number of terminal pins of the semiconductor device to be tested includes: a tester controller for controlling various operations in the tests system including test patterns to be applied to the device under test, timings and waveforms of the test patterns; a test unit for generating the test patterns and expected value patterns with predetermined timings based on control signals from the tester controller; a pin assignment converter provided between the tester controller and the test unit for providing conversion data showing a conversion relationship between physical pin numbers of the test unit and supplemental tester pin numbers which have been replaced with defective tester pins to the test unit; a test head having drivers for supplying the test patterns from the test unit to the semiconductor device with predetermined amplitudes and comparators for detecting levels of output signals fr

Abstract: There is provided an apparatus for processing data for generating an error correction product code block devised so as to maintain the current level of redundancy after the error correcting ability is modified as a result of advancement of semiconductor and data recording/transmission technologies. Unlike any known technique of configuring a Reed-Solomon error correcting product code block of (M+P0)×(N+PI) bytes for an information data of (M×N) bytes, an error correcting product code block data structure is obtained by configuring a (K×(M+1)×(N+P))-byte Reed-Solomon error correcting product code block for (K×M×N)-byte data, making K variable to consequently make the entire size of the Reed-Solomon error correcting product code block variable. At the same time, the error correcting ability varies in proportion to the value of K without increasing redundancy.

Abstract: A method of and an apparatus for duplicating direct access storage devices (DASDs) such as hard disk drives (HDDs). The apparatus includes a portable HDD duplicator which can be connected to an existing personal computer (PC), and perform fast data duplication directly from a source HDD to a multiplicity of target HDDs simultaneously. The method includes the steps of providing direct data paths between the source HDD and the target HDDs and performing high speed data duplication and comparison functions by reading the source HDD and writing to the target HDDs at the same time.

Abstract: Apparatus and method to improve the speed of electronic file transfer between remote computers by parallel processing. The most common transfer protocol is the File Transfer Protocol (FTP) Though the Internet is the most popular means by which users electronically transport data, the Internet's Transport Control Protocol/Internet Protocol ("TCP/IP") model, upon which FTP operates, does not adequately support the transfer of large data sets over long distances. Typical transfers between distant sites linked via the Internet have throughputs of about 20 Kilobytes per second ("Kb/sec") or less, and they are prone to dropping packets or losing connections. Making FTP parallel makes transfers up to five times faster, that is, it offers transfer rates of up to 100 Kb/sec. FTP is operated in parallel by segmenting a file into discrete packets, simultaneously transmitting these packets to the receiving computer, and reassembling the packets into the original file.

Abstract: An single event upset (SEU) tolerant system for detecting and correcting an SEU includes a decision element (200) for receiving a plurality of outputs (120) from a plurality of signal generators (105) and producing an output (130) therefrom. The decision element includes voters which provide two levels of voting for the plurality of redundant outputs (120). First-level voters (300) provide intermediate voted outputs (315) which are received by a second-level voter to determine an output (130). An output disabler (400) determines when an output is provided external to the decision element. A plurality of comparators (210) receive intermediate voted outputs (315) from first-level voters and compare with a plurality of outputs from a plurality of signal generators to determine upset detected signals (125). An upset detected signal controls the selection of feedback for an element having experienced an SEU.

Abstract: Methods and associated apparatus for automatically synchronizing the operating code between a plurality of controllers. In a first embodiment after the spare controller is swapped into the storage subsystem, if the native controller determines that the spare controller's operating code is incompatible with the native controller's operating code, then the native controller notifies the spare controller that synchronization is required between both controllers. The native controller creates an image of its operating code including configuration parameters, and copies this "synch info" into a reserved area of cache memory. The spare controller's main CPU utilizes mirroring routines to copy the operating code and configuration parameters into a reserved area of its cache memory. After the transfer is complete, the spare controller's main CPU loads the operating code and configuration parameters into its program memory and resets itself to operate with the modified program memory.

Abstract: The present invention relates to a disc array apparatus assuring that even if contradiction is detected in matching of parity data during a read parity check, correct host data is Restructured and can always be transferred to the host. The disc array apparatus of the present invention is particularly applicable to disc drives in the RAID configuration. For example, in a disc array apparatus of the present invention implementing RAID level 3, the disc array apparatus adds CRC data to data transferred from a host computer, divides the data, generates parity from the divided data, and stores the data and the parity data into the disc drives. During a read operation, the disc array apparatus of the present invention executes a read parity check.

Abstract: There is disclosed a parallel test circuit for a semiconductor memory device having a memory army with a plurality of memory cells and a plurality of comparators used for high-speed memory cell test, including a plurality of fist comparators performing first comparison with respect to data transmitted through a plurality of data output lines formed near memory blocks of the memory array; a plurality of second comparators coupled in common with each output terminal of the first comparators and performing second comparison with respect to output data of the first comparators; a multiplexer multiplexing output of the second comparator; first and second switches alternatively connected to an output terminal of the multiplexer; and a data output buffer coupled in common with output terminals of the first and second switches and buffering outputs of the first and second switches.

Abstract: A pair of substantially identical integrated circuit elements, in the form of microprocessors, are operated in response to the same instruction and data signals that are accessed from a memory by one of the integrated circuits. The accessed instruction and data signal are supplied, via a synchronous interface, to the second integrated circuit, which operates thinking that the supplied data and instruction signals were accessed by it in response to address and control signals. The states of the two integrated circuits are applied to comparator circuitry, both via buffered paths. The comparator circuitry is operated in response to control signals produced by the first integrated circuit to effect comparison on only those signals that are valid at any particular moment in time. Clock-synchronizing circuitry is included to ensure that predetermined state transitions of the clocks used to operate the first and second integrated circuit occur within a prescribed time period.