Comparison Of Data Patents (Class 714/819)
  • Patent number: 10454788
    Abstract: In accordance with an embodiment, described herein is a system and method for providing multitenancy support in a platform as a service or cloud computing environment. A platform component enables a service runtime to be shared by multiple tenants, by providing each tenant with a dedicated share or slice of a runtime instance. Each share/slice can be isolated from other shares/slices with respect to factors such as, for example, configuration, or quality of service. In accordance with an embodiment, during provisioning of a particular service runtime, a runtime definition associated with the service runtime can be utilized, for example by a service management engine, to configure the platform component to install one or more services within the service runtime. A particular service and its service runtimes can also be provisioned, within one or more runtime pools, according to a service runtime definition and placement configuration.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: October 22, 2019
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Rajiv Mordani, Nazrul Islam, Sivakumar Thyagarajan, Bhavanishankara Sapaliga
  • Patent number: 10423506
    Abstract: A System, Computer program product, and computer-executable method of rebuilding a failed data storage device within a storage architecture including a plurality of protection domains including two or more data storage devices, wherein a RAID protection is generated over volumes provided from the plurality of protection domains, the System, Computer program product, and computer-executable method including receiving a notification of a failed data storage device of the data storage devices within a first protection domain of the plurality of protection domains and rebuilding the failed data storage device using reserved data storage within a first data storage device within the first protection domain.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: September 24, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Assaf Natanzon, Erez Webman
  • Patent number: 10419301
    Abstract: In accordance with an embodiment, described herein is a system and method for providing multitenancy support in a platform as a service or cloud computing environment. A platform component enables a service runtime to be shared by multiple tenants, by providing each tenant with a dedicated share or slice of a runtime instance. Each share/slice can be isolated from other shares/slices with respect to factors such as, for example, configuration, or quality of service. In accordance with an embodiment, during provisioning of a particular service runtime, a runtime definition associated with the service runtime can be utilized, for example by a service management engine, to configure the platform component to install one or more services within the service runtime. A particular service and its service runtimes can also be provisioned, within one or more runtime pools, according to a service runtime definition and placement configuration.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: September 17, 2019
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Rajiv Mordani, Nazrul Islam, Sivakumar Thyagarajan, Bhavanishankara Sapaliga
  • Patent number: 10049072
    Abstract: A method is described, for use in a data processing system, the system having a node and a communication link, wherein the communication link is coupled to the node. The method can comprise obtaining first digital signal information associated with a first signal, transmitting the first signal from the node to the communication link, receiving a second signal from the communication link at the node, and analyzing the second signal to obtain second digital signal information. The method can further include combining first digital signal information with second digital signal information and flagging a combination outside a predetermined condition space. Further, an apparatus, for use in the data processing system is described that can be operative to perform the method. A data processing system is also described.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: August 14, 2018
    Assignee: Infineon Technologies AG
    Inventor: Achim Vowe
  • Patent number: 10025666
    Abstract: A method for surveying a data storage subsystem for latent errors before a failing disk drive of the data storage subsystem fails and recovering unreadable data usable to reconstruct data of the failing disk drive. The method includes determining that a disk drive of a plurality of disk drives of the data storage subsystem meets a threshold for being identified as a failing disk drive, and prior to failure of the failing disk drive, surveying at least a portion of the data on the remaining plurality of disk drives to identify data storage areas with latent errors. The identified data storage areas may be reconstructed utilizing, at least in part, data stored on the failing disk drive.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: July 17, 2018
    Assignee: Dell International L.L.C.
    Inventors: Anthony J. Floeder, Derek J. Anderson
  • Patent number: 10026089
    Abstract: The disclosure is directed to a system, method, and computer program for dynamically identify a merchant associated with an authorization request for a payment card, wherein a merchant identifier in the authorization request is unrecognized. A plurality of unique signatures is created for each of a plurality of registered merchants, wherein the signatures for each registered merchant are based on values of merchant attributes associated with the registered merchant. In response to the system receiving an authorization request for a payment card that includes an unrecognized merchant identifier used to process authorization requests, a plurality of unique signatures is generated for the unrecognized merchant based on a combination of merchant attributes in the authorization request. A payment processing system then determines if the signatures match one of the signatures previously created for the registered merchants.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: July 17, 2018
    Assignee: Marqeta, Inc.
    Inventors: Anthony Ford, Jason M. Gardner, Mark Lopez, David Matter, Jatin P. Salla
  • Patent number: 9870618
    Abstract: An apparatus for identifying a candidate area in a first image corresponding to an object in a second image, includes a memory and a processor to divide the plurality of candidate areas into a plurality of small candidate areas, divide an image area of the object into a plurality of small areas, perform first comparison processing for a first part, when there is a first candidate area lacking image information of the small candidate area corresponding to the first part, perform second comparison processing for a second part, predict missing result on the small candidate area corresponding to the first part in the first candidate area based on a result of the first comparison processing on a candidate area other than the first candidate area, and a result of the second comparison processing on the plurality of candidate areas, and identify the candidate area based on a prediction.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: January 16, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Mingxie Zheng, Akihiro Minagawa, Yusuke Uehara, Kentaro Tsuji, Yuji Matsuda, Nobuhiro Miyazaki
  • Patent number: 9767457
    Abstract: The disclosure is directed to a system, method, and computer program for dynamically identify a merchant associated with an authorization request for a payment card, wherein a merchant identifier in the authorization request is unrecognized. A plurality of unique signatures is created for each of a plurality of registered merchants, wherein the signatures for each registered merchant are based on values of merchant attributes associated with the registered merchant. In response to the system receiving an authorization request for a payment card that includes an unrecognized merchant identifier used to process authorization requests, a plurality of unique signatures is generated for the unrecognized merchant based on a combination of merchant attributes in the authorization request. A payment processing system then determines if the signatures match one of the signatures previously created for the registered merchants.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: September 19, 2017
    Assignee: Marqeta, Inc.
    Inventors: Anthony Ford, Jason M. Gardner, Mark Lopez, David Matter, Jatin P. Salla
  • Patent number: 9760364
    Abstract: Software extensions for applications of an enterprise system may be developed in a test system. An adaptation transport module accesses, in the test system, a collection of adaptation objects where each adaptation object includes a semantic representation of a software extension for an application of an enterprise system and at least one associated software object. The transport module processes the collection by: generating staging data based on a type of each adaptation object; exporting the collection from the test system; performing checks on each adaptation object based on the staging data; and importing the collection to the enterprise system. The transport module installs each of the software extensions on the application, using the at least one associated software object for each, based on the results of the checks of each respective adaptation object. The staging data may be written to a file in a common directory shared by both systems.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: September 12, 2017
    Assignee: SAP SE
    Inventors: Thomas Wieczorek, Kai Dehmann, Tamara Weckwerth
  • Patent number: 9542304
    Abstract: Technologies are provided herein for automated operating system installation. Through the concepts and technologies presented herein, the process of installing multiple operating systems on a system under test (“SUT”) can be automated and monitored, thereby permitting the unattended installation of the operating systems. Multiple operating systems can be installed and errors detected during the installations can be logged in an automated fashion, thereby reducing the cost of such testing. Errors generated during the automated installation process can be analyzed and utilized to identify and correct errors in a computing system firmware. A device selector for facilitating the automated installation process is also provided.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: January 10, 2017
    Assignee: American Megatrends, Inc.
    Inventors: Charles Patrick Hanes, Clas Gerhard Sivertsen, James Brian Richardson
  • Patent number: 9286784
    Abstract: A method and apparatus for ignoring a duplicated alarm in a communications network are described. In one embodiment, at least one alarm message associated with at least one event is received. A determination of whether the at least one event exists in a database is subsequently made. The at least one event is recorded in the database if the at least one event does not exist in the database. Conversely, the at least one alarm message is suppressed if the at least one event exists in the database.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: March 15, 2016
    Assignee: AT&T Intellectual Property II, L.P.
    Inventors: Daniel Sheleheda, Michael Singer
  • Patent number: 9166844
    Abstract: An integrated circuit is disclosed that includes a receiver circuit to receive duobinary data symbols from a first signaling lane. The receiver circuit includes sampling circuitry to determine symbol state, and a duobinary decoder. The duobinary decoder is coupled to the sampling circuitry and converts the detected states to a PAM2 coded symbol stream. A decision-feedback equalizer (DFE) is provided that has inputs coupled to the sampling circuitry in parallel with the duobinary decoder. The DFE cooperates with the sampling circuitry to form a feedback path, such that the duobinary decoder is external to the feedback path.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: October 20, 2015
    Assignee: Rambus Inc.
    Inventor: E-Hung Chen
  • Patent number: 9047269
    Abstract: In certain embodiments, a method for modeling interactions with a computer system includes collecting interaction information for each of a number of interaction sessions with a computer system, each interaction session being associated with a corresponding agent system and including one or more states and one or more state transitions. The interaction information for an interaction session includes data for the one or more states and the one or more state transitions of the interaction session. The method further includes, for each of the interaction sessions, identifying the one or more states encountered during the interaction session based on the collected interaction information and generating, based on the one or more states encountered during the interaction session, a trace of the interaction session. The method further includes generating, based on the traces of the interaction sessions, a model of the interaction sessions, the model including the traces for each of the interaction sessions.
    Type: Grant
    Filed: October 27, 2006
    Date of Patent: June 2, 2015
    Assignee: Openconnect Systems Incorporated
    Inventors: Eric P. Armstrong, Stuart H. Burris, Jr., Christopher Raymond Houck
  • Patent number: 9026240
    Abstract: A coating and developing treatment apparatus includes a substrate transfer mechanism; and a defect inspection section. A transfer control part controls transfer of a substrate. A defect classification part classifies a defect based on the state of the defect. A storage part stores a transfer route of the substrate by the substrate transfer mechanism when the substrate has been treated by treatment sections. A defective treatment specification part specifies, based on a kind of the defect classified by the defect classification part and the transfer route of the substrate stored in the storage part, a treatment section which is a cause of occurrence of the classified defect, and judges presence or absence of an abnormality of the specified treatment section. The transfer control part controls the substrate transfer mechanism to transfer a substrate bypassing the treatment section which has been judged to be abnormal by the defective treatment specification part.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: May 5, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Makoto Hayakawa, Hiroshi Tomita, Tatsuhei Yoshida
  • Publication number: 20150100865
    Abstract: Plural control-units each perform a verification process for verifying validity of data. A first storage stores, for each control-unit, an index value indicating a load on the each control-unit activating the verification process, in association with each combination of a rate of a data-amount processed in the verification process executed by the each control-unit and a utilization rate of the each control-unit. A second storage stores, in association with each control-unit, information on a data-amount currently being processed in the verification process activated by the each control-unit and the utilization rate of the each control-unit. A first control-unit determines an index value, for each control-unit, by referring to information in the first storage based on information on a data-amount to be processed in a target verification process and information in the second storage, and determines a second control-unit to activate the target verification process, based on the determined index values.
    Type: Application
    Filed: September 8, 2014
    Publication date: April 9, 2015
    Applicant: FUJITSU LIMITED
    Inventor: Yuji Noda
  • Patent number: 9003271
    Abstract: An error detecting device of a dual controller system is provided. The first controller receives a sensing data from a sensor to calculate and generate a first data and outputs a final data if an error is not detected by comparing the first data with a second data transmitted from a second controller. The CAN transceiver receives the final data from the first controller and transmits the final data through a CAN bus. The second controller receives the sensing data from the sensor to calculate and generate a second data and transmits to the first controller an interrupt signal which prevents an output of the final data if an error is detected by comparing the second data with the final data fed back from the CAN transceiver. Accordingly, output transmission to the vehicle is controlled and the stability and reliability of the output data is increased.
    Type: Grant
    Filed: July 6, 2011
    Date of Patent: April 7, 2015
    Assignee: Daesung Electric Co., Ltd.
    Inventor: Ji-Hun Jung
  • Publication number: 20150095740
    Abstract: A binary content addressable memory (BCAM) is disclosed. The BCAM includes a memory array, data signature circuitry, and a data match module and compare circuitry. The memory array is configured to store a data entry for a data word and a corresponding data signature for the data entry. The data signature circuitry is configured to calculate the data signature for the data entry and to calculate the data signature for an input word. The data match module compares the data entry to the input word to produce a content match output, and compares the data signature for the data entry to the data signature of the input word to produce a signature match output. The compare circuitry compares the content match output and the data signature match output.
    Type: Application
    Filed: September 30, 2014
    Publication date: April 2, 2015
    Inventors: Michael Anthony Zampaglione, Thomas Robert Wik
  • Publication number: 20150095738
    Abstract: A ternary content addressable memory (TCAM) is disclosed. The TCAM includes a memory array, a data match module, and compare circuitry. The memory array stores a data entry for a data word and a corresponding duplicate data entry for the data word. The data match module compares the data entry to an input word to produce a first match output, and compares the duplicate data entry to the input word to produce a second match output. The compare circuitry compares the first match output and the second match output.
    Type: Application
    Filed: September 30, 2014
    Publication date: April 2, 2015
    Inventors: Michael Anthony Zampaglione, Thomas Robert Wik
  • Publication number: 20150095748
    Abstract: A method of operation in a memory controller is disclosed. The method includes generating first error information for a selectively dynamic-bus-inversion (DBI)-encoded data word. The selectively DBI-encoded data word is for transfer to a memory device. Second error information associated with the selectively DBI-encoded data word is received from the memory device. Errors in the data word are detected by comparing the first error information to the second error information. The detecting includes evaluating the DBI-encoding of the selectively DBI-encoded data word.
    Type: Application
    Filed: December 11, 2014
    Publication date: April 2, 2015
    Inventor: Aliazam Abbasfar
  • Patent number: 8996973
    Abstract: A method of determining frame loss between two management points (C, D) in an Ethernet network, in which the management points each transmit frames to each other and each of the two management points transmits to the other, in regular intervals, measurement messages which contain current counts of frames transmitted and received by the respective transmitting management point. At least one of the two management points responds to a received management message to compute from counts of actual packets transmitted and/or received by a given one of the management points the frame loss at the given management point. At least one of the management points computes the frame loss only once in a measurement interval which consists of a multiplicity of the regular intervals and employs in the computation the counts indicated by the measurement message most recently received by the one of the management points.
    Type: Grant
    Filed: June 12, 2010
    Date of Patent: March 31, 2015
    Assignee: Mingoa Limited
    Inventors: Anne G. O'Connell, Con D. Cremin
  • Patent number: 8982366
    Abstract: A method automatically performs regression testing of output of an altered variable information print job (program). In one embodiment, the method begins by supplying test data to a variable information (VI) print job to produce first sample data. Next, the method applies a numeric generation application to the sample data to produce numerical representations. Then, the VI print job is altered and the same test data is supplied to the altered VI print job to produce second sample data. Again, the numeric generation application is applied to the second sample data to produce more of the numerical representations. The numerical representations are then compared to identify altered data records caused by the altering of the VI print job.
    Type: Grant
    Filed: December 6, 2006
    Date of Patent: March 17, 2015
    Assignee: Xerox Corporation
    Inventor: Philip C. Rose
  • Patent number: 8977945
    Abstract: Examples are disclosed for transmitting video content. In some examples, cyclic redundancy check (CRC) values may be added to video content for video frames to be presented or displayed in a given region of a display. Results of CRC functions for consecutive video frames that use the added CRC values may be compared to determine whether the video content for the consecutive video frames is static video content. Video content for at least one of the consecutive video frames may be withheld from being transmitted if the video content for the consecutive video frames is characterized as static video content. Multiple CRC values or different CRC values may be added to further determine whether video content for the consecutive video frames or for subsequent consecutive video frames is also characterized as static video content. Other examples are described and claimed.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: March 10, 2015
    Assignee: Intel Corporation
    Inventors: Guoqing Li, Jeffrey R. Foerster, Yaniv Frishman
  • Patent number: 8977937
    Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for variable rate encoding and/or decoding in a data processing system. In some cases, embodiments include a variable length data decoder circuit that is operable to apply a decode algorithm to the encoded input based upon a first selected H-Matrix to yield a first decoded output and apply the decode algorithm to the encoded input based upon a second selected H-Matrix to yield a second decoded output.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: March 10, 2015
    Assignee: LSI Corporation
    Inventors: Fan Zhang, Shaohua Yang, Yang Han, Chung-Li Wang, Weijun Tan
  • Patent number: 8972790
    Abstract: A controller section outputs a first signal and a second signal holding a phase relationship with the first signal. The second signal is received by a memory I/F section via a FIFO memory of an error detecting section. The memory I/F section performs timing adjustment for the first and second signals, outputs the first and second signals after the timing adjustment to a memory, and loops back the second signal. A data comparator compares the looped-back second signal with the original second signal outputted from the FIFO memory and corresponding to the looped-back signal.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: March 3, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Hisataka Nakabayashi, Miho Takeda, Masanori Ito
  • Patent number: 8966355
    Abstract: An apparatus for comparing pairs of binary words includes an intermediate value determiner and an error detector. The intermediate value determiner determines an intermediate binary word so that the intermediate binary word is equal to a reference binary word for a first pair of equal or inverted binary words, so that the intermediate binary word is equal to the inverted reference binary word for a second pair of equal or inverted binary words and so that the intermediate binary word is unequal to the reference binary word and the inverted reference binary word for a pair of unequal and uninverted binary words, if the intermediate value determiner works faultlessly. Further, the error detector provides an error signal based on the intermediate binary word so that the error signal indicates whether or not the binary words of a pair of binary words are equal or inverted.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: February 24, 2015
    Assignee: Infineon Technologies AG
    Inventors: Thomas Kern, Ulrich Backhausen, Michael Goessel, Thomas Rabenalt
  • Patent number: 8954833
    Abstract: An approach for determining a value representing the number of leading zero count value in a binary input data word, is described. The binary input data word contains random data. The binary input data word is logically divided into odd and even bit positions. The approach includes a first comparator circuit for comparing data in the odd bit positions to data in the even bit positions. The approach further includes a second comparator circuit for comparing the data in the odd bit positions to a result of a logical operation performed on the data in the odd and even bit positions. The approach further includes a half-width leading zero counting circuit that provides a value representing the number of leading zero bits in the binary input data word.
    Type: Grant
    Filed: June 6, 2012
    Date of Patent: February 10, 2015
    Assignee: International Business Machines Corporation
    Inventor: Deepak K. Singh
  • Publication number: 20150040226
    Abstract: There is disclosed a method for detecting an error in the reading of a data item, this method includes a)storing a first copy of the data item in a first area of an electronic memory and storing of a second copy of the data item in a second area of an electronic memory. In Step b there is also included a Reading of the values of the first and second copies of the data item in the first and second areas respectively, In step c)here is a comparison of the read values of the first and second copies of the data item if the read values of the first and second copies are different, then the preceding steps b) and c) are repeated (78, 80), then f) if the values read in the step e) are identical, then an error in the reading of this data item is detected (82) and, otherwise, no error in the reading of this data item is detected.
    Type: Application
    Filed: November 29, 2012
    Publication date: February 5, 2015
    Applicant: VIACCESS
    Inventors: Emmanuel Barau, Patrick Soquet
  • Publication number: 20150039978
    Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for priority based data processing.
    Type: Application
    Filed: July 30, 2013
    Publication date: February 5, 2015
    Applicant: LSI Corporation
    Inventors: Kaitlyn T. Nguyen, Fan Zhang, Jun Xiao
  • Publication number: 20150019939
    Abstract: A method and system are described herein that employ a lost frame concealment technique for processing data frames received during transmission over a communications channel. The lost frame concealment technique involves determining whether a current data frame is a bad frame, performing source decoding on the current data frame with one or more parameters that are limited by a first set of one or more values if the current data frame is a bad frame, and performing source decoding on the current data frame with one or more parameters that are not limited if the current data frame is a good frame.
    Type: Application
    Filed: September 29, 2014
    Publication date: January 15, 2015
    Inventors: Yi Wen Liu, Sean Bartholomew Simmons
  • Patent number: 8930638
    Abstract: A cache coherency controller, a system comprising such, and a method of its operation are disclosed. The coherency controller ensures that target-side security checking rules are not violated by the performance-improving processes commonly used in coherency controllers such as dropping, merging, invalidating, forwarding, and snooping. This is done by ensuring that requests marked for target-side security checking and any other requests to overlapping addresses are forwarded directly to the target-side security filter without modification or side effects.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: January 6, 2015
    Assignee: QUALCOMM Technologies, Inc.
    Inventors: Laurent Moll, Jean-Jacques Lecler, Philippe Boucard
  • Publication number: 20150007002
    Abstract: A frequency signal generator includes a controllable oscillator unit, a frequency control unit and an error detection unit. The controllable oscillator unit generates and provides a frequency signal. The frequency control unit generates a frequency control signal and the controllable oscillator unit varies a frequency of the frequency signal based on the frequency control signal. Further, the error detection unit receives the frequency control signal, detects an error within the frequency control signal and provides an error signal. The error signal comprises information on a detected error.
    Type: Application
    Filed: June 28, 2013
    Publication date: January 1, 2015
    Inventors: Bernhard Gstöttenbauer, Klemens Kordik
  • Patent number: 8898394
    Abstract: A storage apparatus for controlling a storage unit includes a cache memory for temporarily storing data to be stored in the storage unit, and a processor for executing a process including receiving unit data which is divided from data to be migrated, calculating first checksum data from the received unit data, storing the unit data and the first checksum data to the cache memory, reading out the stored unit data and the first checksum data from the cache memory, calculating second checksum data from the read out unit data, storing the unit data to the storage unit, and determining whether data migration has been performed properly by comparing the first checksum data to the second checksum data.
    Type: Grant
    Filed: August 6, 2010
    Date of Patent: November 25, 2014
    Assignee: Fujitsu Limited
    Inventors: Norio Kondo, Satoshi Konno, Ken-ichiroh Tango
  • Patent number: 8887034
    Abstract: Various embodiments of the present invention provide systems and methods for media defect detection. As an example, a data processing circuit is disclosed that includes a defect detector circuit and a comparator circuit. The defect detector circuit is operable to calculate a correlation value combining at least three of a data input derived from a medium, a detector extrinsic output, a detector intrinsic output and a decoder output. The comparator circuit is operable to compare the correlation value to a threshold value and to assert a media defect indicator when the correlation value is less than the threshold value.
    Type: Grant
    Filed: April 15, 2011
    Date of Patent: November 11, 2014
    Assignee: LSI Corporation
    Inventors: Fan Zhang, Shaohua Yang
  • Patent number: 8887022
    Abstract: A data transmission system includes at least one transmission line. A sender is configured to send data frames to the at least one transmission line and a recipient is configured to receive the data frames from the at least one transmission line. The sender and the recipient are both configured to determine a check sum based on a plurality of corresponding data frames that are sent to and, respectively, received from the at least one transmission line. A check sum comparing unit is configured to receive and to compare the check sum determined by the sender and the corresponding check sum determined by the recipient. The check sum comparing unit is also configured to signal a transmission error or initiate a safety function when the check sums compared are not equal.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: November 11, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Dirk Hammerschmidt, Timo Dittfeld, Simon Brewerton
  • Publication number: 20140331112
    Abstract: Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns, and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device operation to maintain adequate margins despite fluctuations in the system noise environment due to e.g. temperature and supply-voltage changes. Also described are methods of plotting and interpreting filtered and unfiltered error data generated by the disclosed methods and circuits. Some embodiments filter error data to facilitate pattern-specific margin testing.
    Type: Application
    Filed: July 17, 2014
    Publication date: November 6, 2014
    Inventors: Andrew Ho, Vladimir Stojanovic, Bruno W. Garlepp, Fred F. Chen
  • Publication number: 20140325322
    Abstract: A semiconductor integrated circuit includes a first transmission circuit generating and outputting a first transmission signal reflecting a first data signal supplied from outside, a first reception circuit reproducing the first data signal based on a first reception signal, a first isolation element isolating the first transmission circuit from the first reception circuit and transmitting the first transmission signal as the first reception signal, a second transmission circuit generating and outputting a second transmission signal reflecting a second data signal supplied from outside, a second reception circuit reproducing the second data signal based on a second reception signal, a second isolation element isolating the second transmission circuit from the second reception circuit and transmitting the second transmission signal as the second reception signal, and a third transmission circuit generating and outputting a third transmission signal reflecting the second data signal.
    Type: Application
    Filed: July 14, 2014
    Publication date: October 30, 2014
    Inventor: Shunichi KAERIYAMA
  • Patent number: 8867287
    Abstract: A semiconductor memory apparatus including a test circuit configured for generating compressed data by comparing and compressing data stored in a plurality of memory cells inside a memory bank during a first test mode, and configured for outputting the compressed data as test data to an input/output pad through one selected global line during the first test mode, and the test circuit is configured for transmitting the compressed data to a plurality of global lines during a second test mode, combining the compressed data loaded in the respective global lines during the second test mode, and outputting the combination result as the test data to the input/output pad during the second test mode.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: October 21, 2014
    Assignee: SK Hynix Inc.
    Inventors: Jin Youp Cha, Jae Il Kim
  • Publication number: 20140304575
    Abstract: An apparatus and a method for digital-analog conversion are provided. The apparatus includes a first cell matrix for outputting a current of a signal corresponding to a number of Most Significant Bits (MSBs) of an input digital signal, a second cell matrix for outputting a current of a signal corresponding to a number of Least Significant Bits (LSBs) of the input digital signal, an amplifier for amplifying the output current of the second cell matrix at a preset amplification, and an adder for adding the output current of the first cell matrix and the output current of the amplifier.
    Type: Application
    Filed: June 23, 2014
    Publication date: October 9, 2014
    Inventor: Jong-Woo LEE
  • Patent number: 8856603
    Abstract: To produce a memory which resists ion or photon attack, a memory structure is chosen whose memory point behaves asymmetrically with regard to these attacks. It is shown that in this case, it is sufficient to have a reference cell for an identical and periodic storage structure in order to be able to correct all the memory cells assailed by an attack. An error correction efficiency of ½ is thus obtained, with a simple redundancy, whereas the conventional methods make provision, for the same result, to triple the storage, to obtain a less beneficial efficiency of ?.
    Type: Grant
    Filed: June 18, 2009
    Date of Patent: October 7, 2014
    Assignees: European Aeronautic Defence And Space Company EADS France, Astrium SAS
    Inventors: Florent Miller, Thierry Carriere, Antonin Bougerol
  • Publication number: 20140281845
    Abstract: A receiver path including first, second, third, and fourth comparator modules. The first comparator module is configured to generate, based on a signal received via the receiver path, a first digital output signal indicative of a sum of first data in the received signal and a first error. The second comparator module is configured to generate, based on the signal received via the receiver path, a second digital output signal indicative of a sum of second data in the received signal and a second error. The third comparator module is configured to generate, based on the signal received via the receiver path, a third digital output signal indicative of the first data in the received signal. The fourth comparator module is configured to generate, based on the signal received via the receiver path, a fourth digital output signal indicative of the second data in the received signal.
    Type: Application
    Filed: March 10, 2014
    Publication date: September 18, 2014
    Applicant: Marvell World Trade Ltd.
    Inventor: Sasan CYRUSIAN
  • Patent number: 8832537
    Abstract: An information management apparatus for managing data includes a rewritable nonvolatile memory, and a memory controller configured to control inputting information into and outputting information from the nonvolatile memory. The memory controller overwrites a data, which includes a first validity check information, a first data body, a second validity check information, a second data body having the same data as the first data body and a third validity check information arranged in this order, in a designated address area in the nonvolatile memory when the memory controller performs a writing control in which the memory controller writes data in the nonvolatile memory.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: September 9, 2014
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Hiroshi Yamamoto
  • Patent number: 8817597
    Abstract: One embodiment comprises a network that includes a plurality of bi-directional links and a plurality of nodes. Each node is communicatively coupled to two neighbor nodes and to two skip nodes using the plurality of bi-directional links. Three neighboring nodes of the plurality of nodes form a triple modular redundant (TMR) set having a first end node, a second end node, and a center node, the first end node configured to transmit output data in a first direction and the second end node configured to transmit output data in a second direction.
    Type: Grant
    Filed: November 5, 2007
    Date of Patent: August 26, 2014
    Assignee: Honeywell International Inc.
    Inventors: Brendan Hall, Kevin R. Driscoll, Michael Paulitsch
  • Publication number: 20140237329
    Abstract: Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for detecting a sync mark with a ratio-adjustable detection system.
    Type: Application
    Filed: February 26, 2013
    Publication date: August 21, 2014
    Applicant: LSI Corporation
    Inventors: Rui Cao, Yu Kou, Shaohua Yang
  • Patent number: 8812943
    Abstract: In particular embodiments, a method includes receiving from a remote system a binary decision diagram (BDD) representing data streams from sensors, an input, and a first hash code, transforming the received BDD to a second arithmetic function by performing the arithmetic transformation on the received BDD, calculating a second hash code from the second arithmetic function and the input, and if the first hash code equals the second hash code, then indicating that the received BDD is uncorrupted data, else indicating that the received BDD is corrupted data.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: August 19, 2014
    Assignee: Fujitsu Limited
    Inventors: Stergios Stergiou, Jawahar Jain
  • Patent number: 8806318
    Abstract: A fault analyzing circuit has: a comparing circuit to compare fault data stored in a storage area with a fault being caused with data of an alternation register; and a position identifying circuit to identify an error bit position from data of a comparative result of the comparing circuit.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: August 12, 2014
    Assignee: Fujitsu Limited
    Inventor: Takahito Hirano
  • Publication number: 20140223269
    Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.
    Type: Application
    Filed: February 7, 2014
    Publication date: August 7, 2014
    Applicant: Rambus Inc.
    Inventors: Yuanlong Wang, Frederick A. Ware
  • Patent number: 8799740
    Abstract: The present invention provides for applying a cyclic redundancy check (CRC) to a data signal. The present invention includes attaching a first CRC to a first data signal block having a first length, segmenting the first data signal block attached with the first CRC into a plurality of second data signal blocks having a length shorter than the first length, respectively generating a second CRC for each second data signal block, and attaching the generated second CRC to the respective second data signal block. Moreover, the first CRC and second CRC may be generated from respectively different CRC generating polynomial equations.
    Type: Grant
    Filed: July 21, 2010
    Date of Patent: August 5, 2014
    Assignee: LG Electronics Inc.
    Inventors: Dongyoun Seo, Bong Hoe Kim, Young Woo Yun, Daewon Lee, Nam Yul Yu, Ki Jun Kim, Dongwook Roh
  • Patent number: 8799753
    Abstract: There is provided a trace/failure observation system which is capable of comprehensive collection of information that is needed for checking a desired operation in a system or the like where the amount of information to be observed is large, and which allows easy analysis of the desired operation. The system includes, in a system LSI to be subjected to trace/failure observation: an event detecting means for observing behavior of a portion to be observed; a first data reducing means for performing observation data reduction processing so that observation data from the event detecting means has an amount of information processable to a second data reducing means; and the second data reducing means for performing one or more steps of observation data reduction processing.
    Type: Grant
    Filed: February 3, 2009
    Date of Patent: August 5, 2014
    Assignee: NEC Corporation
    Inventors: Noriaki Suzuki, Junji Sakai
  • Publication number: 20140215294
    Abstract: A circuit includes a first one-time programmable (OTP) element and a second OTP element. The circuit also includes error detection circuitry coupled to receive a first representation of data from the first OTP element. The circuit further includes output circuitry responsive to an output of the error detection circuitry to output an OTP read result based on the first representation of the data or based on a second representation of the data from the second OTP element.
    Type: Application
    Filed: January 29, 2013
    Publication date: July 31, 2014
    Applicant: QUALCOMM INCORPORATED
    Inventors: Jung Pill Kim, Taehyun Kim, Sungryul Kim
  • Publication number: 20140201607
    Abstract: One-time programmable integrated circuit security is described. An example of a method of protecting memory assets in an integrated circuit includes sampling values of multiple OTP memory arrays and comparing the sampled value of each OTP memory array with the sampled value of each other OTP memory array and with an unprogrammed OTP memory array value. The method further includes determining if an integrated circuit performance fault has occurred based on the compared sampled values, booting the integrated circuit, and operating the integrated circuit with access to memory determined by the fault occurrence determination.
    Type: Application
    Filed: January 14, 2013
    Publication date: July 17, 2014
    Applicant: QUALCOMM Incorporated
    Inventor: Asaf ASHKENAZI