Sequential Repetition Patents (Class 714/822)
  • Patent number: 10659081
    Abstract: Techniques for recovering preprogrammed data from non-volatile memory are provided that include majority voting and/or use of one or more levels of ECC correction. Embodiments include storage of multiple copies of the data where ECC correction is performed before and after majority voting with respect to the multiple copies. Multiple levels of ECC correction can also be performed where one level of ECC is performed at the local level (e.g. on-chip), whereas another level of ECC correction is performed at a system level.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: May 19, 2020
    Assignee: Everspin Technologies, Inc.
    Inventors: Sumio Ikegawa, Jon Slaughter
  • Patent number: 9291475
    Abstract: A device, system and method for controlling speed of a vehicle are provided. The device includes a locational information module for determining location information and speed; a storage module for storing at least one geographic map including at least one route and a speed limit for the at least one route; a processing module configured to receive the location information, retrieve at least one geographic map based on the location information, determine a speed limit based on the location information, and compare the speed of the device to the determined speed limit; and a display module for alerting a user if the speed of the device exceeds the determined speed limit. The system and method can be for communicating a subject vehicle's speed to a central server where it can be utilized to analyze traffic congestion patterns or notify selected companies or individuals.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: March 22, 2016
    Assignee: Intellectual Ventures II LLC
    Inventor: Leigh M. Rothschild
  • Patent number: 9213598
    Abstract: A nonvolatile memory device includes a nonvolatile memory, a buffer memory configured to store a plurality of read data transmitted from the nonvolatile memory, an error detection and correction circuit configured to detect an error in partial data of each of the plurality of read data and judging whether the partial data is correctable or not on the basis of the detected error, and a controller configured to analyze the uncorrectable partial data with respect to the plurality of read data to determine a representative value, and to transmit the representative value to the error detection and correction circuit. The plurality of read data is read through a read operation with respect to a same page.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: December 15, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Youngil Seo, Jungho Yun, Wonchul Lee, Dawoon Jung
  • Patent number: 8589774
    Abstract: Systems and techniques to interpret signals on a noisy channel are described. A described technique includes storing a group of signals including a filtered digital signal and one or more previous signals, the filtered digital signal being based on an analog signal; interpreting the filtered digital signal as first discrete values; determining whether the first discrete values are adequately indicated based on a result of the interpreting; initiating a retry mode when the first discrete values are not adequately indicated; producing, in the retry mode, a new signal, the new signal being determined based on an average of at least a portion of the group of signals; interpreting, in the retry mode, the new signal as second discrete values; and determining whether the second discrete values are adequately indicated based on hard decisions indicated by the new signal and hard decisions indicated by the filtered digital signal.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: November 19, 2013
    Assignee: Marvell International Ltd.
    Inventors: Hongxin Song, Zining Wu
  • Patent number: 8359527
    Abstract: Systems and techniques to interpret signals on a noisy channel. A described system includes a filter, buffer, detector, controller, and averager. The buffer can store a group of signals, including a filtered digital signal and previous signal(s). The controller can determine whether first discrete values are adequately indicated and initiate a retry mode when the first discrete values are not adequately indicated. The averager can produce a new signal, in the retry mode, based on an average of at least a portion of the group of signals. The detector can interpret the new signal as second discrete values. The controller can determine whether the second discrete values are adequately indicated based on a measurement of differences between hard decisions indicated by the new signal and hard decisions indicated by the filtered digital signal. The controller can selectively exclude a signal of the group of signals from the average.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: January 22, 2013
    Assignee: Marvell International Ltd.
    Inventors: Hongxin Song, Zining Wu
  • Patent number: 8209597
    Abstract: This invention provides a system and method that can employ a low-instruction-per-second (lower-power), highly parallel processor architecture to perform the low-precision computations. These are aggregated at high-precision by an aggregator. Either a high-precision processor arrangement, or a low-precision processor arrangement, employing soft-ware-based high-precision program instructions performs the less-frequent, generally slower high-precision computations of the aggregated, more-frequent low-precision computations. One final aggregator totals all low-precision computations and another high-precision aggregator totals all high-precision computations. An equal number of low precision computations are used to generate the error value that is subtracted from the low-precision average. A plurality of lower-power processors can be arrayed to provide the low-precision computation function.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: June 26, 2012
    Assignee: Cognitive Electronics, Inc.
    Inventors: Andrew C. Felch, Richard H. Granger
  • Patent number: 8201021
    Abstract: A method of creating backup files having less redundancy. The method creates a backup file by creating an overhead segment for each file that is to be backed up and creating a data segment containing the data that is to be backed up for each file. After creating the overhead segment and the data segment, the overhead segment is placed into an overhead stream data segment is stored in memory. The overhead segment is also positioned in the overhead stream with a pointer that identifies the data segment within the memory. For backups of subsequent servers or the same server at a later time, the backup software will create a separate overhead stream. However, a plurality of overhead streams may contain pointers to the same data segments such that redundant data segments do not need to be stored in a backup server.
    Type: Grant
    Filed: January 31, 2005
    Date of Patent: June 12, 2012
    Assignee: Symantec Corporation
    Inventors: Sunil Shah, Kirk L. Searls, Ynn-Pyng “Anker” Tsaur
  • Patent number: 8171386
    Abstract: Sequential storage circuitry for a integrated circuit is provided, comprising a first storage element, a second storage element and an additional storage element. The first storage element stores, during a first phase of a clock signal, a first indication of an input data value received by the sequential storage circuitry. The second storage element is coupled to an output of the first storage element, and stores a second indication of the input data value during a second phase of the clock signal. The additional storage element is driven by a pulse signal derived from the clock signal, and is arranged on occurrence of that pulse signal to store a third indication of the input data value. Error detection circuitry is then provided for detecting a single event upset error in either the first storage element or the second storage element.
    Type: Grant
    Filed: March 27, 2008
    Date of Patent: May 1, 2012
    Assignee: ARM Limited
    Inventors: Vikas Chandra, Sachin Satish Idgunji
  • Patent number: 8161367
    Abstract: Sequential storage circuitry includes first and second storage elements storing first and second indications of input data values received by the circuitry during first and second phases of a clock signal. Error detection circuitry detects a single event upset error in any of the first and second storage elements. Two additional storage elements are provided for storing third and fourth indications of the input data value respectively in response to a pulse signal derived from the clock signal. Included is comparison circuitry for comparing the third and fourth indications of the input data value and further comparison circuitry for comparing, during a first phase of the clock signal, the first indication and at least one of the third and fourth indications, and for comparing, during a second phase of the clock signal, the second indication and at least one of the third and fourth indications.
    Type: Grant
    Filed: October 7, 2008
    Date of Patent: April 17, 2012
    Assignee: ARM Limited
    Inventor: Vikas Chandra
  • Patent number: 8161361
    Abstract: Systems and techniques to interpret signals on a noisy channel. In general, in one implementation, the technique includes: interpreting an input signal as discrete values, and in response to an inadequate signal, averaging multiple signals to improve interpretation of the input signal. The input signal can be a read signal from a storage medium, such as those found in disk drives. A read channel can include a buffer and an averaging circuit capable of different signal averaging approaches in a retry mode, including making signal averaging decisions based on a signal quality measure. Buffering read signals can be done in alternative locations in the read channel and can involve buffering of many prior read signals and/or buffering of an averaged read signal.
    Type: Grant
    Filed: June 20, 2003
    Date of Patent: April 17, 2012
    Assignee: Marvell International Ltd.
    Inventors: Hongxin Song, Zining Wu
  • Patent number: 7921331
    Abstract: A write filter cache system for protecting a microprocessor core from soft errors and method thereof are provided. In one aspect, data coming from a processor core to be written in primary cache memory, for instance, L1 cache memory system, is buffered in a write filter cache placed between the primary cache memory and the processor core. The data from the write filter is move to the main cache memory only if it is verified that main thread's data is soft error free, for instance, by comparing the main thread's data with that of its redundant thread. The main cache memory only keeps clean data associated with accepted checkpoints.
    Type: Grant
    Filed: June 12, 2008
    Date of Patent: April 5, 2011
    Assignee: International Business Machines Corporation
    Inventors: Pradip Bose, Zhigang Hu, Xiaodong Li, Jude A. Rivers
  • Patent number: 7827475
    Abstract: In a transmitting entity a message of a first time period L is divided into N self-decodable blocks and transmitted towards a communications network. At the communications network the N self-decodable blocks are detected by a receiving entity and decoded on a block basis.
    Type: Grant
    Filed: September 20, 2005
    Date of Patent: November 2, 2010
    Assignee: Nokia Corporation
    Inventors: Esa Tiirola, Kari Pajukoski
  • Patent number: 7712012
    Abstract: Method for configuring a transmission chain in a 3GPP2 system for supporting a flexible or variable data rate of an information bitstream in a process for mapping an information bitstream of a data rate on a physical layer, including the steps of (1) channel coding the information bitstreams with bit rates different from each other into turbo codes or convolution codes having a value inverse of 1/coding rate, and (2) repeating coded bitstream when the channel coded bitstream is smaller than a desired interleaving size, and puncturing the coded bitstream when the channel coded bitstream is greater than the desired interleaving size, for matching the channel coded bitstream to the interleaving size.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: May 4, 2010
    Assignee: LG Electronics Inc.
    Inventors: Young Woo Yoon, Young Jo Lee, Ki Jun Kim, Soon Yil Kwon
  • Patent number: 7636878
    Abstract: Method for configuring a transmission chain in a 3GPP2 system for supporting a flexible or variable data rate of an information bitstream in a process for mapping an information bitstream of a data rate on a physical layer, including the steps of (1) channel coding the information bitstreams with bit rates different from each other into turbo codes or convolution codes having a value inverse of 1/coding rate, and (2) repeating coded bitstream when the channel coded bitstream is smaller than a desired interleaving size, and puncturing the coded bitstream when the channel coded bitstream is greater than the desired interleaving size, for matching the channel coded bitstream to the interleaving size.
    Type: Grant
    Filed: September 22, 2005
    Date of Patent: December 22, 2009
    Assignee: LG Electronics Inc.
    Inventors: Young Woo Yoon, Young Jo Lee, Ki Jun Kim, Soon Yil Kwon
  • Publication number: 20090249175
    Abstract: Sequential storage circuitry for a integrated circuit is provided, comprising a first storage element, a second storage element and an additional storage element. The first storage element stores, during a first phase of a clock signal, a first indication of an input data value received by the sequential storage circuitry. The second storage element is coupled to an output of the first storage element, and stores a second indication of the input data value during a second phase of the clock signal. The additional storage element is driven by a pulse signal derived from the clock signal, and is arranged on occurrence of that pulse signal to store a third indication of the input data value. Error detection circuitry is then provided for detecting a single event upset error in either the first storage element or the second storage element.
    Type: Application
    Filed: March 27, 2008
    Publication date: October 1, 2009
    Applicant: ARM Limited
    Inventors: Vikas Chandra, Sachin Satish Idgunji
  • Patent number: 7587663
    Abstract: A technique to detect errors in a computer system. More particularly, at least one embodiment of the invention relates to using redundant virtual machines and comparison logic to detect errors occurring in input/output (I/O) operations in a computer system.
    Type: Grant
    Filed: May 22, 2006
    Date of Patent: September 8, 2009
    Assignee: Intel Corporation
    Inventors: Steven K. Reinhardt, Shubhendu S. Mukherjee
  • Patent number: 7409330
    Abstract: Systems and methods for debugging software and/or hardware are disclosed. A processor may execute a program for a certain amount of time. The context of the processor at the end of that time may then be made available to a simulator operable to simulate the processor. The program can then be executed from that point on the simulator using the context. Additionally, a context resulting from the execution of the program on the simulator may result and be restored to the processor for continued execution.
    Type: Grant
    Filed: June 16, 2005
    Date of Patent: August 5, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Danny N. Kumamoto
  • Patent number: 7403893
    Abstract: A communication system includes a destination that receives voice samples and a voice parameter generated by a source. The destination uses the voice samples and voice parameter to reconstruct voice information in response to a packet loss. The destination may reconstruct voice information from multiple sources.
    Type: Grant
    Filed: January 19, 2006
    Date of Patent: July 22, 2008
    Assignee: Cisco Technology, Inc.
    Inventors: Pascal H. Huart, Luke K. Surazski
  • Patent number: 7386781
    Abstract: A method is presented comprising identifying a weak component in a wireless communication link, instructing a transmitter of the weak component to invoke repetition coding, and selectively combining signals received via multiple antennae on multiple channels to recover information contained in the transmitted signal.
    Type: Grant
    Filed: March 26, 2001
    Date of Patent: June 10, 2008
    Assignee: ArrayComm, LLC
    Inventors: Lars Johan Persson, Athanasios A. Kasapi
  • Patent number: 7346646
    Abstract: A method and apparatus for transmitting data frames, and a method and apparatus for data rate matching wherein, via an interleaver, elements to be transmitted are distributed over a plurality of radio frames and repeated, the repetition being carried out in such a way that, when put into its relationship with the original arrangement of the elements before the interleaving, the pattern prevents the spacing between arbitrary consecutive repeated elements from being substantially greater than the mean repetition spacing.
    Type: Grant
    Filed: September 19, 2000
    Date of Patent: March 18, 2008
    Assignee: Siemens Aktiengesellschaft
    Inventor: Bernhard Raaf
  • Patent number: 7266752
    Abstract: Method for configuring a transmission chain in a 3GPP2 system for supporting a flexible or variable data rate of an information bitstream in a process for mapping an information bitstream of a data rate on a physical layer, including the steps of (1) channel coding the information bitstreams with bit rates different from each other into turbo codes or convolution codes having a value inverse of 1/coding rate, and (2) repeating coded bitstream when the channel coded bitstream is smaller than a desired interleaving size, and puncturing the coded bitstream when the channel coded bitstream is greater than the desired interleaving size, for matching the channel coded bitstream to the interleaving size.
    Type: Grant
    Filed: December 2, 2003
    Date of Patent: September 4, 2007
    Assignee: LG Electronics Inc.
    Inventors: Young Woo Yoon, Young Jo Lee, Ki Jun Kim, Soon Yil Kwon
  • Patent number: 7260742
    Abstract: A non-hardened processor is made fault tolerant to SEUs and SEFIs. A processor is provided utilizing time redundancy to detect and respond to SEUs. Comparison circuitry is provided in a radiation hardened module to provide special redundancy with the need to run additional processors. Additionally, a hardened SEFI circuit is provided to periodically send a signal to the process which, in the case of a processor not in the SEFI state, initiates production by the processor of a “correct” response. If the correct response is not received within a particular time window, the SEFI circuit initiates progressively severe actions until a reset is achieved.
    Type: Grant
    Filed: January 28, 2004
    Date of Patent: August 21, 2007
    Inventor: David R. Czajkowski
  • Patent number: 7249185
    Abstract: Methods, devices, and software are provided for generating and sending data packets that contain redundant voice data over VoIP connections made under an unreliable network protocol. The redundant data is packaged either in redundant data packets, or in expanded original packets, to repeat data that originally belongs in other packets. Generation of the redundant voice data is either from the transmitting device or from a retransmitting device, such as a router in the network. Generation is triggered either when errors are detected, or simply when the network resources permit it, or both. The received voice data is processed by the second party to the connection, which is typically a telephone call. The redundant voice data that is actually received is discarded. The invention thus ensures that less voice data is lost than in the prior art over VoIP connections made under an unreliable network protocol.
    Type: Grant
    Filed: October 30, 2000
    Date of Patent: July 24, 2007
    Assignee: Cisco Technology, Inc.
    Inventors: Shmuel Shaffer, Joseph F. Khouri, Michael E. Knappe, John F. Wakerly
  • Patent number: 7213193
    Abstract: There is provided an apparatus and method of generating two-dimensional QCTCs. The sub-code sets of QCTCs with given code rates are generated and the sub-codes are rearranged in a sub-code set with a different code rate, for use in the next transmission to a sub-code with a predetermined code rate.
    Type: Grant
    Filed: February 6, 2002
    Date of Patent: May 1, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-Goo Kim, Sang-Hyuck Ha, Jae-Sung Jang
  • Patent number: 7185261
    Abstract: A system and method to transmit and receive forward error corrected data in a diversity communications system is provided. Using diversity techniques, multiple copies of the transmitted data are received with varying degrees of corruption due to channel impairments. In addition to the multiple copies of forward error corrected data, an additional data set of implicit parity bits is used in the data decoding process, wherein the reliability of these parity bits is assumed to be very high. The implicit parity bits are not transmitted or received by the system, but are introduced in the receivers' decoding process. These implicit parity bits add an extra highly reliable dimension of forward error correction codes. Therefore the present system and methods provide an improved data decoding process with high coding gain and channel efficiency, while minimizing system resources.
    Type: Grant
    Filed: April 28, 2004
    Date of Patent: February 27, 2007
    Assignee: The Insitu Group, Inc.
    Inventor: Stephen Heppe
  • Patent number: 7137045
    Abstract: A decoding method and an apparatus operate by performing error correction on code words of an error correcting code block in one direction selected from a row direction and a column direction, indicating in error flags the remaining code words except at least some code words from code words having uncorrectable errors, and performing error correction on code words in the other direction based on the error flags. Accordingly, errors that have been conventionally considered as being uncorrectable may now be corrected.
    Type: Grant
    Filed: January 21, 2003
    Date of Patent: November 14, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-hee Hwang, Yoon-woo Lee, Sung-hyu Han, Sang-hyun Ryu, Young-im Ju
  • Patent number: 7103811
    Abstract: A method for detecting errors in streaming media devices is described. In one embodiment, when a command to write a block of data to a streaming media device is received, integrity metadata associated with the data block is attached to the data block and written to the streaming media device together with the data block. Subsequently, when a read command pertaining to this data block is received, new integrity metadata is determined and compared to the attached metadata. If the new integrity metadata does not match the attached metadata, an error message is generated.
    Type: Grant
    Filed: December 23, 2002
    Date of Patent: September 5, 2006
    Assignee: Sun Microsystems, Inc
    Inventors: Nisha D. Talagala, Brian Wong
  • Patent number: 7103019
    Abstract: A communications system includes a mobile unit that transmits redundant content to a plurality of destinations. A copy of the content that is transmitted to each destination is encoded using a code that is related to the codes used to encode copies of the content transmitted to the other destinations. The system further includes a number of base transceiver stations. Each base transceiver station receives a copy of the coded content from the mobile unit, generates a packet including the coded content, and communicates the packet. Furthermore, the system includes a decoder that receives a number of packets that each include a copy of the coded content and that are each generated at a different base transceiver station. The decoder decodes the content in the packets by concatenating the related codes used to encode each copy of the content and generates one or more redundant packets including the decoded content.
    Type: Grant
    Filed: March 21, 2001
    Date of Patent: September 5, 2006
    Assignee: Cisco Technology, Inc.
    Inventor: Billy G. Moon
  • Patent number: 7093185
    Abstract: A QCTC (Quasi-Complementary Turbo Code) generating apparatus having: a turbo encoder for generating an information symbol sequence and a plurality of parity symbol sequences by encoding the information symbol sequence; a channel interleaver for individually interleaving the symbol sequences, generating new parity symbol sequences by multiplexing the symbols of parity symbol sequences with the same priority levels, and serially concatenating the information symbol sequence and the new parity symbol sequences; and a QCTC generator for generating a sub-code with a given code rate by recursively selecting a predetermined number of symbols from the concatenated symbol sequence at a given starting position.
    Type: Grant
    Filed: February 12, 2002
    Date of Patent: August 15, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-Goo Kim, Jae-Sung Jang
  • Patent number: 7013267
    Abstract: A communication system includes a destination that receives voice samples and a voice parameter generated by a source. The destination uses the voice samples and voice parameter to reconstruct voice information in response to a packet loss. The destination may reconstruct voice information from multiple sources.
    Type: Grant
    Filed: July 30, 2001
    Date of Patent: March 14, 2006
    Assignee: Cisco Technology, Inc.
    Inventors: Pascal H. Huart, Luke K. Surazski
  • Patent number: 6977969
    Abstract: There is provided a digital data receiver for recovering at least one message word signal from a digital data frame.
    Type: Grant
    Filed: June 28, 2001
    Date of Patent: December 20, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-Ha Lee, Young-Jin Kim, Sung-Joo Kim
  • Patent number: 6931565
    Abstract: A semiconductor memory is configured such that it can be connected with a first and second timing generator. The semiconductor memory includes (a) a first register configured to communicate with a memory array and the first timing generator, to retrieve and to hold first data from the memory array at a first timing, (b) a logic gate configured to communicate with the memory array and the first register, to receive the first data from the first register and second data from the memory array after the first timing, so as to compare the first and second data with each other, so that it can provide a comparison result indicating whether or not the first and second data agree with each other, and (c) a second register configured to communicate with the logic gate and the second timing generator, to retrieve and to hold the comparison result at a second timing.
    Type: Grant
    Filed: February 20, 2002
    Date of Patent: August 16, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Osamu Hirabayashi
  • Patent number: 6850704
    Abstract: Fault tolerance is provided in a cross-connect system having only duplicated switch fabrics, instead of the triplicated switch fabrics of the prior art. In addition to the two information switch fabrics, the cross-connect system has a relatively small code switch fabric which switches check-code signals generated at each input interface for each input signal sent to an information switch fabric. Fault-detection and error-recovery components in each output interface (1) generate local check-code signals for each outgoing signals received from an information switch fabric and (2) compare those local check-code signals to the corresponding check-code signal received from the code switch fabric to detect a failure and to select a healthy signal as the output signal for that output interface. In one embodiment, input and output interfaces are clustered, and the corresponding input and output check-code signals are multiplexed, for even greater savings in overhead (e.g.
    Type: Grant
    Filed: July 12, 2000
    Date of Patent: February 1, 2005
    Assignee: Lucent Technologies Inc.
    Inventor: Bharat P. Dave
  • Patent number: 6708299
    Abstract: A first method for acquiring data from a recording on a disk medium, comprises the steps of, successively reading bits defining a data set from different parts of the disk, continuously error correcting the bits to validate at least a part of the data set read from the disk, and, terminating reading upon successful validation of the data set by the error correcting step. A second method for acquiring data from a recording on a disk medium, comprises the steps of reading a data set beginning from a first position on the data recording, reading the data set from a second position radially spaced in a first direction from the first position absent acquisition of an error free data set from the first position; and, reading the data set from a third position radially spaced in an opposite direction beyond the first position absent acquisition of an error free data set from the second position.
    Type: Grant
    Filed: November 22, 1999
    Date of Patent: March 16, 2004
    Assignee: Thomson Licensing S.A.
    Inventor: Jianlei Xie
  • Patent number: 6694481
    Abstract: The invention relates to a method for reading programmes into a device which processes data using a processor, according to a programme stored in a programme memory. A programming device sends programme data to the programme memory of the device to be programmed in the form of a data stream. The inventive method comprises the following steps: a) activating a light transmitter in accordance with the programme data, so that said light transmitter generates digital light signals in accordance with the programme data; b) receiving the light signals with a light receiver which is permanently installed on the device to be programmed and c) applying the signals of the light receiver of the device to be programmed to the programme memory of the same. The invention also relates to a device for carrying out this method.
    Type: Grant
    Filed: November 27, 2000
    Date of Patent: February 17, 2004
    Assignee: Bodenseewerk Geratetechnik GmbH
    Inventors: Jürgen Späh, Benno Petersen
  • Patent number: 6614847
    Abstract: A video compression method and system including object-oriented compression plus error correction using decoder feedback.
    Type: Grant
    Filed: April 6, 1999
    Date of Patent: September 2, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Arnab Das, Rajendra K. Talluri
  • Patent number: 6601217
    Abstract: A system and method are provided for performing error correction for all or part of an electronic communication, such as a routing header of a packet. At a transmitting entity the routing information contained in the header is divided into a plurality of segments. Multiple iterations of the routing segments are included in the packet, with the routing segments arranged in different sequences in different iterations. Thus, when transmitted across a communication link comprising multiple lines, each routing segment is carried across at least two different subsets of the lines, thus increasing the likelihood that at least one version of the segment will be received without error. Each segment of each iteration may be encoded with error detection information. For example, a parity bit may be added to each segment. At the receiving entity each iteration is received in turn, and each segment of the received iteration is checked for errors. When a segment is received without errors, it can be forwarded (e.g.
    Type: Grant
    Filed: April 13, 2000
    Date of Patent: July 29, 2003
    Assignee: Sun Microsystems, Inc.
    Inventor: Brian L. Smith
  • Patent number: 6594798
    Abstract: Correction of errors and losses in a receiver-driven layered multicast (RLM) of real-time media over a network is augmented using one or more layers of error correction information. Each receiver separately optimizes the quality of received information by subscribing to at least one error correction layer. Ideally, each source layer in a RLM has one or more associated multicasted error correction data streams. Each error correction layer contains information for replacing lost packets from the associated source layer. More than one error correction layer is proposed to correct for lost packets in other error correction layers. Error correction streams are preferably generated using a pseudo-Automatic Repeat Request (ARQ) wherein a broadcaster sends both the source packets in a primary stream and delayed versions thereof in one or more redundant streams. A hybrid technique combines the psuedo-ARQ method with an adaptation of Forward Error Correction (FEC) techniques.
    Type: Grant
    Filed: May 21, 1999
    Date of Patent: July 15, 2003
    Assignee: Microsoft Corporation
    Inventors: Philip A. Chou, Albert S. Wang, Sanjeev Mehrotra, Alexander E. Mohr
  • Publication number: 20030093747
    Abstract: The present invention relates to a method for transporting real-time data from a transmitter to a receiver on a radio packet communication network, the real time data entity being generated at the transmitter and comprising at least two bit portions having different relevance, each real time data entities being encapsulated in a radio block and submitted to a modulation and coding scheme before transmission.
    Type: Application
    Filed: October 29, 2002
    Publication date: May 15, 2003
    Applicant: Evolium S.A.S.
    Inventors: Jerome Brouet, Nicolas Paul, Carine Thirouard
  • Publication number: 20030066017
    Abstract: Positions in which errors have occurred are found more accurately and erasure correction is performed more effectively than in cases where TA flags or error flags issued by the R/W channel are utilized as information indicating the positions in which errors have occurred, [this being accomplished] by reading the same sector on the magnetic disk a plurality of times, storing the plurality of NRZ data thus obtained, comparing these NRZ data in byte units, judging that an error has occurred in byte positions where the NRZ data reproduced in each read operation differs, and utilizing these positions as erasure pointers for erasure correction.
    Type: Application
    Filed: February 7, 2002
    Publication date: April 3, 2003
    Inventor: Nobuhiro Kuwamura
  • Patent number: 6543027
    Abstract: An application specific integrated circuit includes a clock recovery circuit which recovers from an input signal a repetitive sequence of data values wherein no two consecutive values are the same and a recovered clock. An address generator responds to the recovered clock to cause storage of the data values in said memory in a set of locations having addresses generated by the address generator, so that the address generated by the generator increments in response to a repetitive transition in the recovered clock. The existence of a clock glitch is found by reading the data values from the set of locations to determine whether any two consecutive locations contain the same data value.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: April 1, 2003
    Assignee: 3Com Corporation
    Inventors: Mark A Hughes, Joseph N Butler, Neil O Fanning
  • Patent number: 6523148
    Abstract: A majority decision method for improved frame error rate in the digital enhanced cordless telecommunications (DECT) system. Specifically, one embodiment of the present invention includes a method for improving retransmission efficiency of a data frame within a communication system. The method includes the step of receiving and storing three corrupted versions of a data frame within a memory. Moreover, the method also includes the step of performing a byte-wise comparison of the three corrupted versions of the data frame to locate an inconsistent byte position. In response to locating the inconsistent byte position among the three corrupted versions of the data frame, the method includes the step of performing a byte-wise majority decision among the three corrupted versions of the data frame to select a correct byte value of the inconsistent byte position.
    Type: Grant
    Filed: August 19, 1999
    Date of Patent: February 18, 2003
    Assignee: Koninlijke Philips Electronics N.,V.
    Inventor: Andreas Junghans
  • Patent number: 6519740
    Abstract: The present invention relates generally to the detection of bits which are protected by repetition, and which, along with their repetitions, have associated soft values available which give a measurement of the reliability of their received values. In particular, the present invention may be used in speech encoding in the GSM mobile communications system, and more particularly to the detection of those class 2 bits called pulse5 bits which are not protected with channel coding. In enhanced full rate (EFS) transmission in GSM there are 4 bits called pulse5 bits. These pulse5 bits are duplicated twice, giving three bits for each original bit, for a total of twelve pulse5 bits. These bits have associated soft values, a probability measure of their reliability, that are produced by the equalizer.
    Type: Grant
    Filed: May 15, 1998
    Date of Patent: February 11, 2003
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Jan Mårtensson, Johan Backman
  • Publication number: 20020166097
    Abstract: A method is presented comprising identifying a weak component in a wireless communication link, instructing a transmitter of the weak component to invoke repetition coding, and selectively combining signals received via multiple antennae on multiple channels to recover information contained in the transmitted signal.
    Type: Application
    Filed: March 26, 2001
    Publication date: November 7, 2002
    Inventors: Lars Johan Persson, Athanasios A. Kasapi
  • Patent number: 6412094
    Abstract: A method for performing 3/5 major voting in the TACS/AMPS mobile phone system, in which a word of the message frame is transmitted repeated five times and every bit of the word is given a value at reception by major voting of the five repeats. The number of ones or zeros of a bit C is counted at least to three. This number is saved as a binary two-bit number B′A′ in two memories (2, 3) so that the first (2) contains the least significant bit A′ of the number B′A′ and the second (3) contains the most significant bit B′ of the number B′A′. After the fifth repeat of the bit C, the final number of ones or zeros of the bit C has been counted and saved in the memories (2, 3) and voting is performed on the bit C based on bits A′ and B′ indicating the number of ones or zeros.
    Type: Grant
    Filed: June 9, 1997
    Date of Patent: June 25, 2002
    Assignee: Nokia Mobile Phones Ltd.
    Inventors: Cornelis Arnold Van Holten, Kaija Maria Salonen, Seppo Eerik Salow
  • Patent number: 6119258
    Abstract: A video error/distortion checker generates a difference signal from an input repetitive digital signal and a reference data signal corresponding to the input repetitive digital signal. The difference signal is compared with maximum and minimum threshold values to generate an error signal when the difference signal exceeds either threshold value. The difference signal also is used to generate a running range value that is compared with a total range value to produce the error signal when during one iteration of the repetitive digital signal the difference signal exceeds a specified range defined by the total range value. The error signal is suitably displayed, either visually or alphanumerically or both, so that an operator may recognize the type, severity and location of errors in the repetitive digital signal.
    Type: Grant
    Filed: March 25, 1998
    Date of Patent: September 12, 2000
    Assignee: Tektronix, Inc.
    Inventor: Bob Elkind
  • Patent number: 6105087
    Abstract: A data-analyzing unit monitors and/or analyzes events on an information bus. The data-analyzing unit comprises an event recognition unit with one or more comparators coupled to the information bus and a sequencer state machine for determining sequential dependencies of events, whereby a state of the sequencer state machine depends on the history of information as provided thereto. The data-analyzing unit preferably comprises one or more counters coupled to the event recognition unit, thus allowing an analysis of data and/or events on the information bus. The data-analyzing unit may also comprise one or more memories coupled to the event recognition unit, thus providing a trace memory. In a preferred embodiment, the event recognition unit of the data-analyzing unit provides customized rules for monitoring defined event sequences of event behaviors thus allowing the monitoring of defined event sequences of event behaviors and possibly the drawing of conclusions therefrom e.g.
    Type: Grant
    Filed: June 10, 1998
    Date of Patent: August 15, 2000
    Assignee: Hewlett-Packard Company
    Inventor: Jochen Rivoir
  • Patent number: 6091711
    Abstract: In a multiplex communication method for implementing multiplex communication between a plurality of circuit units, a format of a transmitted data signal not only is formed of serial data consisting of first data, second data that has the same content as the first data, and a parity that indicates the number of logical 1s or logical 0s forming the first data and the second data is even or odd, but also selects as regular data in such a manner that when the transmitted data signal is received, if the first data and the second data are compared with each other and judged to be coincident with each other from the comparison, then the coincident data is selected as the regular data and that if the first data and the second data are judged to be different from each other from the comparison, then a logic of the parity is checked and either the first data or the second data corresponding to the logic of the parity is selected as the regular data.
    Type: Grant
    Filed: May 23, 1997
    Date of Patent: July 18, 2000
    Assignee: Kansei Corporation
    Inventor: Masahiro Fukuda
  • Patent number: 6061821
    Abstract: A system for encoding and decoding a binary encoded text message using coxt-based error detection and correction implements the stops of: a) defining a dictionary of m dictionary words, W.sub.i, where each dictionary word is assigned a unique binary code word, represented by a series of bits, and an identifier, IDFR.sub.i such that for any two words W.sub.p and W.sub.q from the dictionary, if IDFR.sub.p =IDFR.sub.q, then the binary code word for the word W.sub.p differs from the binary code word for the word W.sub.
    Type: Grant
    Filed: January 9, 1998
    Date of Patent: May 9, 2000
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: Thomas W. Schlosser
  • Patent number: 6018816
    Abstract: A system comprising devices connected via a 1394 serial bus solves a problem that if omission of data packet occurs in isochronous transfer capable of high-speed data transfer, only data without the omitted data packet is sent to a transfer destination. A recording/reproduction device 101 repeatedly sends image data stored in a storage medium by the isochronous transfer, and a printer 102 receives the image data repeatedly sent by the isochronous transfer. If a data packet has been omitted in the received data, the omitted data packet is obtained from the data repeatedly sent by the isochronous transfer, thus the printer 102 can print an image based on the complete image data.
    Type: Grant
    Filed: April 2, 1998
    Date of Patent: January 25, 2000
    Assignee: Canon Kabushiki Kaisha
    Inventor: Jiro Tateyama