Abstract: Techniques to transmit encoded data along a transmission medium and decode the transmitted data along the transmission medium are provided. Some techniques include logic to encode data transmitted along a transmission medium, such as a fiberoptic line or cable, where the encoding is pursuant to a conversion between a first and second colorspace. The logic may further be configured to decode the data once it is received at a node along the fiberoptic line, where the colorspace conversion provides the basis, key, or cipher for preforming the decoding operation. The logic may be further configured to alter the encryption and decryption basis, key, or cypher by altering the colorspace scheme defining the encoding (and by extension the decoding) during transmission, including a transmission that takes place after a previous transmission governed by the previously defined (and subsequently altered) colorspace conversion scheme. Other embodiments are described and claimed.

Abstract: Methods, systems, and devices for operating a memory device are described. An error correction bit flipping scheme may include methods, systems, and devices for performing error correction of one or more bits (e.g., a flip bit) and for efficiently communicating error correction information. The data bits and the flip bit (e.g., an error corrected flip bit) may be directly transmitted (e.g., to a flip decision component). The flip bit may be transmitted to the flip decision component over a dedicated and/or unidirectional line that is different from one or more other lines that carry data bits (e.g., to the flip decision component).

Abstract: In order to provide a crossbar switch type memory circuit designed to be usable in normal circumstances even when a resistance change element is in an adverse state, the present invention is provided with: a first unit including a first column wiring to which one end of a first resistance change element is connected, a first power supply-side transistor for controlling the connection of the first column wiring and a power supply node, a first ground-side transistor, of a reverse operation type to the first power supply-side transistor, for controlling the connection of the first column wiring and a ground node, and a first polarity control line for causing the first power supply-side transistor or the first ground-side transistor to turn on and the other to turn off by a polar signal from a polar signal terminal, the first polarity control line being connected to the control terminals of the first power supply-side transistor and first ground-side transistor; a second unit including a second column wiring to

Abstract: A method includes, in a data storage device including a resistive memory, receiving, from an external device, an erase command to erase a portion of the resistive memory. The method further includes storing shaped data at the portion of the resistive memory responsive to the erase command. Shaped data is configured to control an amount of leakage current during a read and/or write operation at one or more storage elements that are adjacent to at least one storage element of the portion of the resistive memory.

Abstract: Systems and methods for communicating messages over a three-phase power cable between surface equipment and downhole equipment in a well. A transmitter parses messages into data bit pairs and generates a parity bit for each pair (a triplet). The bits of each triplet are concurrently but separately transmitted over the power cable. Each triplet is received from the power cable by a receiver and is decoded to identify the data bits. The receiver may verify the received bits and/or recover a lost bit in each triplet. The data bits are then reconstructed into the original message. Since each triplet has two bits, the effective data rate is twice the data rate of transmitting a single bit at a time. The parity bit enables recovery of data with a bit error rate of up to 1 in 3.

Abstract: A receiver of a remote control device includes a receiver configured to receive by wireless communication, a packet including a count value of edges of pulse signals, which are output from an encoder, per a predetermined period and to obtain the count value from the received packet, a register configured to retain the count value based on a write signal input from the receiver, and a pulse regenerating circuit including a counter in which the count value of the register is set based on the write signal input from the receiver, and configured to regenerate the pulse signals at an edge period that corresponds to the count value set in the counter in the predetermined period that corresponds to the write signal.

Abstract: A logic block group 120 having at least one set including a logic block having at least one logic circuit and a sequential circuit that inputs the output of the logic block is arranged in an irradiation region 110 of a high-energy particle irradiation device, and subjected to irradiation with high-energy particles. A control section 101 calculates the error rate of the logic circuit from the value obtained by subtracting the number of errors of the sequential circuit when the logic block of the logic block group 120 is bypassed, from the number of errors of the sequential circuit and the logic block of the logic block group 120.

Abstract: A memory system according to the embodiment comprises a memory device including a plurality of memory cells operative to store storage data, the storage containing input data from external to which parity information is added; and a memory controller operative to convert between the input data and the storage data, the storage data containing information data corresponding to the input data, and a relationship between the information data and the input data being nonlinearly.

Abstract: Processors, microprocessors and logical block systems and methods, error detection systems and methods, and integrated circuits are disclosed. In an embodiment, a logic-based computing system includes a first processing core; a second processing core generated from the first processing core and including an inverted logical equivalent of the first processing core such that an output of the second processing core is a complement of an output of the first processing core; and comparator logic coupled to receive the outputs of the first and second processing cores as inputs and provide an error output if the output of the second processing core is not the complement of the output of the first processing core.

Abstract: The present application relates to a data bus system, its encoder/decoder and encoding/decoding method.

Abstract: The memory device electrically connectable to a host circuit includes a nonvolatile data memory section, a data reception section, a determination section, and a data transmission section. The data reception section receives, from the host circuit, data including first data to be written into a memory array, and second data generated from the first data. The determination section determines the consistency the first data and the second data. The data transmission section transmits the result of the determination to the host circuit.

Abstract: The present application relates to a data bus system, its encoder/decoder and encoding/decoding method.

Abstract: Sequential storage circuitry includes first and second storage elements storing first and second indications of input data values received by the circuitry during first and second phases of a clock signal. Error detection circuitry detects a single event upset error in any of the first and second storage elements. Two additional storage elements are provided for storing third and fourth indications of the input data value respectively in response to a pulse signal derived from the clock signal. Included is comparison circuitry for comparing the third and fourth indications of the input data value and further comparison circuitry for comparing, during a first phase of the clock signal, the first indication and at least one of the third and fourth indications, and for comparing, during a second phase of the clock signal, the second indication and at least one of the third and fourth indications.

Abstract: A data storage subsystem that includes three data storage units, three check storage units, and an array controller coupled to the three data and three check storage units can tolerate failure of any three data and check storage units failures can be occur before data stored on the data storage subsystem is lost. Information is stored on the data storage subsystem as a symmetric Maximum Distance Separation code, such as a Winograd code, a Reed Solomon code, an EVENODD code or a derivative of an EVENODD code. The array controller determines the contents of the check storage units so that any three erasures of the data storage units and the check storage units can be corrected by the array controller. The array controller updates a block of data contained in any one of the data storage units and the check storage units using only six IO operations.

Abstract: At least two Exclusive-OR (EOR) circuits for carry-out which output carry-out bits and the complementary signals thereof are provided in the 5-3 compressor circuits constituted by an Exclusive-OR (EOR) circuit group, and dual lanes are employed at least for carry-out. As a result, the number of inverters required can be reduced, increases in delay time can be suppressed, and fast addition operation can be achieved.

Abstract: A data inversion register technique for integrated circuit memory testing in which data input signals are selectively inverted in a predetermined pattern to maximize the probability of identifying failures during testing. In accordance with the technique of the present invention, on predetermined input/outputs (I/Os,) data inputs may be inverted to create a desired test pattern (such as data stripes) which are “worst case” for I/O circuitry or column stripes which are “worst case” for memory arrays. A circuit in accordance with the technique of the present invention then matches the pattern for the data out path, inverting the appropriate data outputs to obtain the expected tester data. In this way, the test mode is transparent to any memory tester.

Abstract: A system for configuring registers of microcontrollers includes first register and second registers. The system includes a data source for loading a datum into the first register and the logic complement of said datum in the second register. The system also includes a comparator which verifies the identity between the datum in the first register and the logic complement in the second register, and, where the identity is not verified, generates a signal indicating that the data have been corrupted by a disturbance. The system also includes a final-state machine which disables the comparator during writing of the registers.

Abstract: An error detection circuit for a latch precharges two dynamic nodes whose discharge paths are gated by true and complement storage nodes of the latch, such that one and only one of the dynamic nodes always discharges when the clock signal transitions from an active state to an inactive state. If a soft error flips the contents of the latch during storage mode the other dynamic node will discharge. A gate having inputs coupled to the dynamic nodes produces an error signal when both nodes have discharged. The error signal can then be used to select between true and complement outputs of the latch. The invention can be implemented in a more robust embodiment which examines the outputs of two error detection circuits to generate a combined error signal that ensures against false error detection when an upset occurs within one of the detection circuits.

Abstract: A system for verifying data integrity includes a central processing unit (CPU) (1), a non-volatile random access memory (NVRAM) (2), and a program memory (3). The NVRAM includes: a plurality of data blocks (23), each data block including a plurality of data bits (20) for storing bit data; a first recognition bit (21) for storing a first recognition code; and a second recognition bit (22) for storing a second recognition code. The program memory stores program modules. The CPU updates and deletes data in data blocks, reads a first recognition code and a second recognition code in a data block in which bit data are to be read, and identifies whether the bit data are complete according to a combination of the first recognition code and the second recognition code. A related method for verifying data integrity is also disclosed.

Abstract: Hard-open defects between logic gates of, for example, an address decoder and the voltage supply which result in logical and sequential delay behavior render a memory conditionally inoperative. A method and apparatus for testing integrated circuits for these types of faults is proposed, in which two cells of two logically adjacent rows or columns are written with complementary logic data. If a read operation reveals the data in the two cells to be identical, the presence and location of a hard-open defect is demonstrated.

Abstract: Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data compression test mode. In the data compression test mode, reading one word of an output page provides an indication of the data values of the remaining words of the output page. The time necessary to read and verify a repeating test pattern can be reduced as only one word of each output page need be read to determine the ability of the memory device to accurately write and store data values. The memory devices include data compression circuits to compare data values for each bit location of each word of the output page. Output is selectively disabled if a bit location for one word of the output page has a data value differing from any remaining word of the output page.

Abstract: Monitoring systems and protocols are disclosed that are flexible in mode operation and format depending on the environment in which they are used. Such monitoring systems and protocols are able to change their utilization automatically, or by received instruction to do so. A location detection system includes one or more low frequency transmitters, one or more radio frequency monitoring tags and one or more receiving devices. The low frequency transmitter transmits location identification information, such as the transmitter ID, to a tag in the vicinity of the transmission. The tag relays the transmitter ID using a higher frequency transmission sent from the tag to the receiver. Communication protocols are disclosed that enable deciphering of multiple tag transmissions starting simultaneously.

Abstract: Methods and corresponding apparatus to recover data from a signal comprising groups of pulses generated in response to analog waveforms are described. Data recovery in accordance with the invention is based on parameters characterizing the groups of pulses. These parameters are the basis for mapping the groups of pulses to information symbols which collectively constitute the data to be recovered.

Abstract: Integrated circuit devices include data inversion circuits therein that are configured to evaluate at least first and second ordered groups of input data in parallel with an ordered group of output data previously generated by the data inversion circuit. The data inversion circuit is further configured to generate inverted versions of the first and second ordered groups of input data as versions of the first and second ordered groups of data in parallel at outputs thereof whenever a number of bit differences between the first ordered group of input data and the ordered group of output data is greater than one-half a size of the first ordered group of input data and a number of bit differences between the second ordered group of input data and the version of the first ordered group of input data is greater than one-half a size of the second ordered group of input data, respectively.

Abstract: A method and system for detecting a failure in a dynamic random access memory (DRAM) array having a plurality of cells organized in a matrix fashion of rows and columns. The method includes reading the content of a first row of cells of the memory array during a first refresh cycle. After obtaining the content from the first row of cells, a first complement of the content is generated. The generated first complement is then written back to the first row of cells during the writeback operation of the first refresh cycle. During the subsequent refresh cycle, the first complement in the first row of cells is read and a second complement of the first complement is generated. Next, the original content in the first row of cells is compared with the second complement. In response to the original content not being equal to the second complement, a control signal is generated to indicate a failure in the memory array.

Abstract: In a method for data transmission in which the binary original data (D0, . . . , Dm) is transferred from a transmitter to a unit of a receiver (1), selected preferably by means of a binary base address (A0, . . . , An), preferably to a register (80, . . . , 87), where the original data (D0, . . . , Dm) and preferably also the base address (A0, . . . , An) are transmitted through one or several data lines, the inverted original data (inversion data) (D0′, . . . , Dm′) and preferably also the complementary base address (complementary address) (A0′, . . . , An′, Ak) are transmitted by the transmitter. The transmitted inversion data (D0′, . . . , Dm′) and preferably the transmitted complementary address (A0′, . . . , An′, Ak) are inverted in the receiver, the transmitted base address (A0, . . . , An) and the transmitted original data (D0, . . . , Dm) are compared with the inverted complementary address (A0′, . . .

Abstract: A highly reliable industrial control system is produced using a network running a standard serial protocol on two redundant messages. A safety protocol is embedded within the standard serial protocol by adding to special error detecting data redundant with the protocol of the standard serial network. In addition, only a single network protocol module (CAN) is necessary to transfer two logical messages of data between modules. In order to still provide redundancy, the data on one of the messages is encoded in a predetermined manner, such as by inverting each bit of data, prior to transmission over the network. The data is then decoded at the destination module and compared to the data on the other logical message to determine whether a transmission error has occurred. Safety protocol may be implemented in an additional level for integrated circuits or through firmware changes in programmable aspects of the industrial controller components.

Abstract: A system within a complementary logic circuit having a true tree and a complement tree, for correcting an illegal non-complementary output caused by a defect in either tree. A complementary logic circuit has a true tree for producing a true signal and a complement tree for producing a complement signal. The true signal is utilized to generate a true output signal from the complementary logic circuit and the complement signal is utilized to generate a complement output signal from the complementary logic circuit. Multiplexing means within the true and complement trees are utilized to selectively replace the true (complement) signal with the complement (true) signal within the true (complement) tree, such that the complement (true) tree is utilized to correct the occurrence of a proscribed non-complementary condition at the output of the complementary logic circuit to diagnose a defect during diagnostic testing or to override a defect during normal runtime operation.

Abstract: A system and method for detecting and rectifying a proscribed non-complementary output from a complementary logic circuit. A complementary logic circuit having a true tree and a complement tree is provided. The true tree produces a true signal utilized to generate a true output signal from the complementary logic circuit. The complement tree produces a complement signal utilized to generate a complement output signal from the complementary logic circuit. Logic means coupled to the output of the complementary logic circuit detect an occurrence of a non-complementary output from the complementary logic circuit. Multiplexing means within the true tree is utilized to selectively replace the true signal with the complement signal within the true tree in response to detection by the logic means of a non-complementary output, such that a non-complementary output is seamlessly detected and rectified.

Abstract: A method and system for detecting faults within dual-rail complementary logic circuits. A method and system are disclosed for detecting faults within dual-rail complementary logic circuits. A dual-rail complementary logic circuit is coupled to an associated complementary fault detection circuit within an integrated circuit. Thereafter, the presence of a non-complementary logic signal can be detected at an output of the complementary fault detection circuit, in response to providing an input signal at an input of the dual-rail complementary logic circuit, such that the presence of a non-complementary logic signal at an output of the complementary fault detection circuit indicates the presence of a fault within the associated complementary logic circuit.

Abstract: A data inversion register technique for integrated circuit memory testing in which data input signals are selectively inverted in a predetermined pattern to maximize the probability of identifying failures during testing. In accordance with the technique of the present invention, on predetermined input/outputs (I/Os,) data inputs may be inverted to create a desired test pattern (such as data stripes) which are “worst case” for I/O circuitry or column stripes which are “worst case” for memory arrays. A circuit in accordance with the technique of the present invention then matches the pattern for the data out path, inverting the appropriate data outputs to obtain the expected tester data. In this way, the test mode is transparent to any memory tester.