Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to generate a first mapping portion and a second mapping portion, where the first mapping portion and the second mapping portion correspond to a same data set, and where the first mapping portion and the second mapping portion includes one or more parity bits, receive an update for the same data set, update the first mapping portion and the second mapping portion based on the update, where the second mapping portion is updated non-concurrently to updating the first mapping portion, and where the updating includes flipping a parity bit of the one or more parity bits, and determine whether the one or more parity bits of the first mapping portion matches the one or more parity bits of the second mapping portion.

Abstract: A read-disturb-based read temperature determination system includes a storage device that is coupled to a read temperature adjustment subsystem. The storage device receives data from the read temperature adjustment subsystem, stores the data in a block in the storage device, identifies read disturb information for a row in the block at a plurality of different times, processes the read disturb information to generate a read temperature for the row, provides the read temperature in a local logical storage element read temperature map and, based on instructions from the read temperature adjustment subsystem, adjusts the read temperature provided in the local logical storage element read temperature map.

Abstract: An analog fault detection circuit is disclosed. The analog fault detection circuit comprises an input terminal, an input circuit path coupled to the input terminal at a first end and a first sampling switch coupled to the second end of the input circuit path. The first sampling switch is configured to sample an input path voltage at the second end of the input circuit path to provide a first analog to digital converter (ADC) input voltage. The analog fault detection circuit further comprises a first ADC conversion circuit configured to convert the first ADC input voltage to a first digital ADC output; and a first broken wire detection circuit coupled between the first sampling switch and the first ADC conversion circuit, and configured to adaptively pulldown or pullup the first ADC input voltage, in order to detect a fault associated with a first analog circuit path.

Abstract: A semiconductor device includes a memory array arranged in a matrix, a plurality of word lines provided corresponding to memory cell rows, a word driver for driving one of the plurality of word lines, a plurality of row select lines connected to the word driver, and a row decoder for outputting a row select signal to the plurality of row select lines based on input row address information. According to the embodiment, the semiconductor device can detect a failure of the address decoder in a simple method.

Abstract: A memory device, memory address decoder, a memory system and related method for memory attack detection are disclosed. An apparatus includes a memory decoder include multiple stages in a decoding path configured to generate a select signal from an input address signal, and fault detecting logic operably coupled with the memory decoder and configured to receive feedback signals distributed from the multiple stages indicative of a fault along the decoding path.

Abstract: A subsystem is configured to apply an offset voltage to a test, or canary, SRAM write driver circuit to create a condition that induces failure of the write operation. The offset voltage is incrementally increased until failure of the test write operation occurs in the canary SRAM circuit. The subsystem then calculates a probability of failure for the actual, non-test SRAM write operation, which is performed by an equivalent driver circuit with zero offset. The subsystem then compares the result to a benchmark acceptable probability figure. If the calculated probability of failure is greater than the benchmark acceptable probability figure, corrective action is initiated. In this manner, actual failures of SRAM write operations are anticipated, and corrective action reduces their occurrence and their impact on system performance.

Abstract: A partition unit that includes a cache for storing both data and error-correcting code (ECC) checkbits associated with the data is disclosed. When a read command corresponding to particular data stored in a memory unit results in a cache miss, the partition unit transmits a read request to the memory unit to fetch the data and store the data in the cache. The partition unit checks the cache to determine if ECC checkbits associated with the data are stored in the cache and, if the ECC checkbits are not in the cache, the partition unit transmits a read request to the memory unit to fetch the ECC checkbits and store the ECC checkbits in the cache. The ECC checkbits and the data may then be compared to determine the reliability of the data using an error-correcting scheme such as SEC-DED (i.e., single error-correcting, double error-detecting).

Abstract: A set of decisions is determined based at last in part on a set of samples. For a given sample in the set of samples, a low frequency noise estimate is estimated based at least in part on (1) at least some samples from the set of samples and (2) at least some decisions from the set of decisions. A reduced noise sample is generated by removing the low frequency noise estimate from the given sample.

Abstract: A test pattern is encoded using a run length limited line encoding to produce an encoded block of data. The encoded block of data is sent via a channel. A plurality of bits in the received block of data that are subsequent to a maximum length run in the sent data is compared to an expected plurality of bits. A type of bit error is classified based on a mismatch between the expected plurality of bits and the plurality of bits in the received block of data.

Abstract: One preferred embodiment of the present invention provides systems and methods for analyzing the delivery performance of newsgroup services. Briefly described, in architecture, one embodiment, among others, includes a newsgroup evaluation system configured to determine a delivery rate for a newsgroup server. In other embodiments, methods and systems are provided for analyzing completion and retention for newsgroup services.

Abstract: A method of testing an integrated circuit (IC) having a plurality of dies can include receiving, within a master die of the plurality of dies of the IC, a configuration data set specifying a circuit design, wherein the circuit design is instantiated within the master die. The method can include broadcasting the configuration data set to at least one slave die, wherein the circuit design is instantiated within each slave die and receiving, within the master die, a test vector set. The method also can include broadcasting the test vector set to the at least one slave die and responsive to each die executing the test vector set, storing test output data generated by each die.

Abstract: A device for the safe threshold-detection of state information from an analog signal including a decision component and at least two acquisition diversity channels including in series a safe adaptation circuit, an electronic analog-to-digital conversion circuit, and a unit for comparing the digital output signal of the analog-to-digital conversion circuit with a reference signal is provided. The device comprises a fault detection circuit for the mutual comparison of digital output signals from the conversion circuits and supplies a consistency result. The output of the decision component is a function of the consistency result supplied by the fault detection unit and of the comparison results from the comparison units associated with the respective acquisition channels.

Abstract: A video transmitting apparatus includes a providing unit configured to provide retransmission request information including information for retransmitting video information to be transmitted to a video receiving apparatus, a control unit configured to perform connection control for communication with the video receiving apparatus, a transmitting unit configured to transmit the retransmission request information provided by the providing unit and the video information to the video receiving apparatus, through communication for which connection control is performed by the control unit, a receiving unit configured to receive a retransmission request based on the retransmission request information, the retransmission request being transmitted from the video receiving apparatus, and a retransmitting unit configured to retransmit a specific part of the video information in accordance with the retransmission request received by the receiving unit.

Abstract: A semiconductor device including an electronic circuit, a memory, and an error detecting module. The electronic circuit is configured to receive an input signal having been generated by a test module, and generate an output signal based on the input signal. The memory is configured to store a predetermined output value that is expected to be output from the electronic circuit based on the electronic receiving the input signal, wherein the predetermined output value is stored in the memory prior to the input signal being generated by the test module. The error detecting module is configured to (i) generate a sample value of the output signal, (ii) compare the sample value of the output signal to the predetermined output value stored in the memory, and (iii) generate a result signal that indicates whether the sample value of the output signal matches the predetermined output value.

Abstract: A memory control apparatus includes a reading unit, an inserting unit, an identifying unit, a determining unit, and an outputting unit. The reading unit reads data from the memory. The inserting unit inserts a dummy error at an insertion position in the data thereby obtaining error data. The identifying unit identifies an error position at which an error has occurred in the error data. The determining unit determines whether the insertion position matches the error position. When the insertion position matches the error position, the outputting unit outputs corrected data obtained by correcting an error at the error position.

Abstract: At least two Exclusive-OR (EOR) circuits for carry-out which output carry-out bits and the complementary signals thereof are provided in the 5-3 compressor circuits constituted by an Exclusive-OR (EOR) circuit group, and dual lanes are employed at least for carry-out. As a result, the number of inverters required can be reduced, increases in delay time can be suppressed, and fast addition operation can be achieved.

Abstract: A system for hazards analysis includes: a memory device for storing a program; a processor in communication with the memory device, the processor operative with the program to: access the memory device to obtain information specifying a system to be analyzed; build functional block diagrams using the information specifying the system to be analyzed; receive user-input hazards analysis elements; and use the functional block diagrams, the user-input hazards analysis elements and tree fault analysis for hazards analysis.

Abstract: A method for generating parallel codes is provided that includes generating a plurality of pairs of outputs for each clock cycle using a single code generator and generating a code based on each pair of outputs using the single code generator.

Abstract: The disclosure details methods of measuring the quality of service of received media signals by analyzing digital watermarks embedded in such signals. The quality of a received video or audio signal can thereby be assessed without having the original version of the signal before transmission. Instead, the strength or quality of the embedded digital watermark is analyzed to determine the quality of the received signal. The degradation of a watermark signal is used to assess quality of service of signals, such as audio and video. Several other features and arrangements are also detailed.

Abstract: A method for determining that failures in semiconductor test are due to a defect potentially causing a hold time violation in a scan cell in a scan chain, counting the number of potential defects, and, if possible, localizing, and ameliorating hold time defects in a scan chain.

Abstract: A device and method for determining defect sectors on an optical disc receives writing commands and data by a processor, and saves the writing data in a memory. An error correction code (ECC) encodes the writing data into encoded digital signals, and the encoded digital signals form modulated digital signals by a modulation device which are saved back into the storage. The processor controls a pick-up head to write and read the modulated digital signals. A comparing unit generates a number of errors by comparing the modulated digital signals before and after writing. The defect sector is directly determined if the number of errors are low or high. The modulated digital signal is decoded to determine the defect sector based on the failure or success of decoding if the number of errors lie in the middle of the range.

Abstract: A semiconductor device that includes a module under test that is integrated with the semiconductor device, that receives an input signal from a test module, and that provides an output signal to at least one output terminal based on the input signal. An error detecting module is integrated with the semiconductor device, samples values of the output signal, and outputs the sampled values to the test module.

Abstract: Disclosed is a system and method for testing a dual mode interface. The dual mode interface includes a first strobe circuit and a second strobe circuit configured to be inoperable during a first operational mode of the interface and operable during a second operational mode of the interface. The dual mode interface also includes a first data circuit and a second data circuit configured to be operable during the first operational mode and the second operational mode. The dual mode interface also includes a signal line connecting an output of the second strobe circuit with an input of the first strobe circuit and a switch element configured to activate said signal line in response to receipt of a test signal.

Abstract: Methods and structures for performing field flawscan to reduce manufacturing costs of a dynamic mapped storage device. In a dynamic mapped storage device in which all user supplied logical blocks are dynamically mapped by the storage device controller to physical disk blocks, features and aspects hereof permit flawscan testing of a storage device to be completed substantially concurrently with processing write requests for its intended application. A fraction of the storage device may be certified by an initial flawscan performed during manufacturing testing. Statistical sampling sufficient to assure a high probability of achieving specified capacity may be performed to reduce manufacturing time and costs in testing. Final flawscan of the remainder of the storage locations may be performed substantially concurrently with processing of write requests after the device is installed for its intended application.

Abstract: This invention relates to fault detection in electrical circuits. The invention provides a method and apparatus for testing an input circuit by generating a periodic test signal having a predetermined phase and a predetermined amplitude; summing the test signal and an input signal to provide a summed signal; processing the summed signal to provide an output signal; generating an extracted test signal from the output signal; comparing the extracted test signal with a reference signal representing said periodic test signal; generating an error signal in dependence upon the result of said comparing step. The invention also provides a method and apparatus for testing a plurality of adjacent input circuits.

Abstract: A memory device capable of detecting its failure, the memory device includes a data input section for receiving data applied from an external part of the memory device; a latch section for receiving and storing therein the data which have passed through the data input section; memory cell arrays for storing therein the data which have passed through the data input section; and a data compressor for determining whether or not the data stored in the latch section and the data stored in the memory cell arrays are identical to each other.

Abstract: A device for the safe threshold-detection of state information from an analog signal including a decision component and at least two acquisition diversity channels including in series a safe adaptation circuit, an electronic analog-to-digital conversion circuit, and a unit for comparing the digital output signal of the analog-to-digital conversion circuit with a reference signal is provided. The device comprises a fault detection circuit for the mutual comparison of digital output signals from the conversion circuits and supplies a consistency result. The output of the decision component is a function of the consistency result supplied by the fault detection unit and of the comparison results from the comparison units associated with the respective acquisition channels.

Abstract: An input circuit of a semiconductor memory device includes a data input circuit and a data pattern setting circuit. The data input circuit receives first data, and generates second data by buffering the first data, sampling buffered first data responsive to a write data strobe (WDQS) signal, and parallelizing sampled data. The data pattern setting circuit sets a pattern of the second data responsive to a test mode signal and a data pattern select signal to generate third data. Accordingly, the semiconductor memory device including the input circuit may generate data of various patterns in a test mode, and may perform a high-speed test using a low-speed tester.

Abstract: A system for checking basic input output system read only memory (BIOS ROM) data includes a keyboard, a display, a computer host, and a checking device. The computer host has a BIOS ROM installed therein. The checking device includes: a data dividing module for dividing the BIOS ROM data into a plurality of sections; a data obtaining module for capturing BIOS ROM data from one or more sections, and for counting a check datum; a data checking module for comparing the check datum with a standard datum, and for determining whether the two data are equal; and a checking result outputting module for outputting the checking results.

Abstract: A test system for testing a backplane comprising an adapter assembly and a generic boundary-scan test unit. The adapter assembly includes an application-specific mating connector to communicatively couple the adapter assembly to an application-specific port of a backplane and an adapter generic connector. The generic boundary-scan test unit includes a test card generic connector to communicatively couple the generic boundary-scan test unit to the adapter generic connector of the adapter assembly and boundary-scan functionality to transmit at least one output test signal. The backplane is tested by communicating the output test signal from the generic boundary-scan test unit to the application-specific mating connector for testing the backplane and communicating at least one input test signal received from the backplane via the application-specific mating connector to the boundary-scan functionality of the generic boundary-scan test unit.

Abstract: Exemplary techniques for verifying a hardware design are described. In a described embodiment, a method comprises compiling an error verification object corresponding to an error verification command to verify a portion of a hardware design of a device under test. The error verification object is compiled in accordance with data provided by an error scripting module. The error scripting module has access to hardware-specific data corresponding to the hardware design of the device under test. The compiled object is sent to the device under test and a response to the compiled object is received from the device under test. The received response from the device under test is parsed in accordance with data provided by the error scripting module.

Abstract: A modulated voltage signal modulated at a predetermined frequency f0 is supplied to an integrated circuit under test to be tested set at an arbitrary stationary point, and an observation signal containing information on power supply current flowing through the integrated circuit under test at the stationary point. Then, a determination signal from which DC component is removed is extracted from the observation signal and supplied to a determination device. The determination device compares the size of spectral component of the determination signal at the predetermined frequency f0 between each measurement point and determines that an error exists in the integrated circuit under test if a difference is a predetermined value or greater.

Abstract: A method and apparatus to correctly compute a vector-gather, vector-operate (e.g., vector add), and vector-scatter sequence, particularly when elements of the vector may be redundantly presented, as with indirectly addressed vector operations. For an add operation, one vector register is loaded with the “add-in” values, and another vector register is loaded with address values of “add to” elements to be gathered from memory into a third vector register. If the vector of address values has a plurality of elements that point to the same memory address, the algorithm should add all the “add in” values from elements corresponding to the elements having the duplicated addresses. An indirectly addressed load performs the “gather” operation to load the “add to” values. A vector add operation then adds corresponding elements from the “add in” vector to the “add to” vector. An indirectly addressed store then performs the “scatter” operation to store the results.

Abstract: A memory device capable of detecting its failure, the memory device includes a data input section for receiving data applied from an external part of the memory device; a latch section for receiving and storing therein the data which have passed through the data input section; memory cell arrays for storing therein the data which have passed through the data input section; and a data compressor for determining whether or not the data stored in the latch section and the data stored in the memory cell arrays are identical to each other.

Abstract: A method and apparatus to correctly compute a vector-gather, vector-operate (e.g., vector add), and vector-scatter sequence, particularly when elements of the vector may be redundantly presented, as with indirectly addressed vector operations. For an add operation, one vector register is loaded with the “add-in” values, and another vector register is loaded with address values of “add to” elements to be gathered from memory into a third vector register. If the vector of address values has a plurality of elements that point to the same memory address, the algorithm should add all the “add in” values from elements corresponding to the elements having the duplicated addresses. An indirectly addressed load performs the “gather” operation to load the “add to” values. A vector add operation then adds corresponding elements from the “add in” vector to the “add to” vector. An indirectly addressed store then performs the “scatter” operation to store the results.

Abstract: A timer circuit for tracking an elapsed time of an electronic device is provided. The timer circuit compares differences in elapsed times written to memory addresses of a memory chip with a periodic interval to determine whether any elapsed times written to the memory chip is corrupt. If so, then the corrupt data is discarded and the device elapsed time is tracked once again based on a valid elapsed time.

Abstract: According to one embodiment a computer system is disclosed. The computer system includes a bus and a chipset coupled to the bus. The chipset detects the slew rate of a signal transmitted over the bus by the chipset. In addition the chipset adjusts the slew rate based upon the state of the signal.

Abstract: The present invention comprises the step of reading a check-receiving data included in a transmitted time code signal and using the read check-receiving data to generate a transmitting side checking data, and the step of attaching the transmitting side checking data to the transmitted time code signal, as a pre-processing step at the time of transmitting the time code signal. The present invention comprises the step of reading the check-receiving data from the received time code signal and using the read check-receiving data to generate a receiving side checking data, and the step of reading the transmitting side checking data from the received time code signal and comparing the read transmitting side checking data to the receiving side checking data, thereby verifying whether or not an error is generated in the received time code signal. In this way, an error can be detected in the time code signal, as a post-processing step after the time code signal is received.

Abstract: The present invention relates to a packet command driving type memory device, a method for compressing output data according to the present invention is characterized to write first data of a certain bit in a corresponding address of core cell regions, read the first data of a certain bit written in the address, compare the written data and the read data by dividing it to an upper certain bit and a lower certain bit, generate compressed data of 1 bit with an information about whether a fail is.

Abstract: An error detection system for detecting errors in data output from a FIFO memory includes a first CRC generator for receiving an inbound data stream and generating a first CRC value based on a data block in the inbound data stream. A device coupled to the first CRC generator selectively inputs the data block and the first CRC value into the FIFO. A second CRC generator generates a second CRC value based on the data block after being output from the FIFO in an outbound data stream. The second CRC value indicates whether the data block contains an error.

Abstract: The present invention pertains to radiation sources that mimic radiation environment(s) encountered by packaged semiconductor devices. The sources are suitable for use in test systems operative to test for soft error and/or failure rates in devices sensitive to such radiation. The radiation is highly active to exacerbate soft error rates and thereby accelerate testing and reduce test times. The sources are also relatively uniformly distributed within a medium to simulate the direction(s) and energy spectra of radiation that would actually be encountered by semiconductor devices in device operation.

Abstract: A bit-error rate is tested in a minimal necessary time period. A block of bits is measured and a cumulative number of bit errors is counted in parallel with calculation of a posterior cumulative distribution function. The posterior cumulative distribution function permits a determination to a desired probability whether or not the bit-error rate is less than a desired bit-error-rate limit. The measurement of blocks of bits and accumulation of bit errors relating thereto and calculation of the posterior cumulative distribution function and making of determinations based thereon continue in parallel until one of three events is detected. The three events are: 1) the bit-error rate is less than the desired bit-error rate limit to the desired probability; 2) the bit-error rate is greater than or equal to the desired bit-error rate limit to the desired probability; and 3) a maximal test time has been reached. Upon detection of any of these three conditions, the test is stopped.

Abstract: A video compression method and system including object-oriented compression plus error correction using decoder feedback.

Abstract: A circuit board, for use with a high speed backplane, includes transmitter and receiver with circuitry for correcting for multipath signal errors. A training sequence that is often a pseudo-random signal is transmitted by the transmitter on a first circuit board to a receiver located on a second circuit board. The receiver on the second circuit board includes an analog-to-digital signal converter, an equalizer, and a binary digital-to-analog reconverter for receiving the training sequence. The equalizer preferably comprises a series of connected registers having taps in between, a plurality of individual weighting means attached to each of the taps, and a summing means connected to the weighting means. A training sequence is transmitted from the first circuit board to the receiver on the second circuit board, enabling the receiver to adaptively determine a set of weighting means coefficients for correcting the multipath errors in subsequent signals.

Abstract: A method and device for measuring the response time of a circuit are described in which clocking pulses are applied to the circuit at input pads, the input pads being connected to the circuit by circuitry having substantially the same delays. By adjusting the timing of the later clock pulse relative to the earlier clock pulse until a valid output is just achieved, the response time of the circuit can be measured using a register circuit.

Abstract: A circuit connection integrity monitor detecting and isolating connection faults in data path cards is disclosed. A connection integrity monitoring method and corresponding apparatus are applicable to selector and cross-connect circuits and permit a user to monitor all points where signal traffic may be prone to misconnection.

Abstract: A physical layer device 21 includes a link layer interface 2, a physical layer logic circuit 3, and ports 4 to 6. In addition to these components, the physical layer device 21 includes therein a test link layer circuit 22, a test physical layer logic circuit 23, and switches 24 to 26 in order to test the operation of the physical layer logic circuit 3 and the ports 4 to 6. In testing, the ports 4 to 6 are externally connected by a cable 27, and contacts of the switches 24 to 26 are switched. Accordingly, the physical layer logic circuit 3 is connected to the test link layer circuit 22, and the ports 5 and 6 are connected to the test physical layer logic circuit 23. According to the present invention, testing can be performed by a physical layer device alone, thus reducing the test time and the test cost.

Abstract: A method and apparatus are disclosed for testing the functionality of a queue structure. An input circuit is provided for inputting data into an input portion of the queue structure, while an output circuit is provided for retrieving data from an output portion of the queue structure. A comparison logic circuit compares the retrieved data with the input data to determine the integrity of the data that was stored in the queue structure and verify that the data from the output portion is identical to the data input to the queue. Various embodiments are disclosed for testing queue structure both in real time and in a test mode.

Abstract: The field of the present invention is related to the transmission of data between a source device and a target device. More particularly, the present invention relates to the determination of a capacity limitation associated with the communication connection between a source device which is the source of a data transmission and a target device which is the target of a data transmission. Even more particularly, the present invention relates to determining the actual data transmission capacity of the communication connection between the source device and the target device.

Abstract: To realize high-speed error propagation path extraction in a combinational circuit, a logical contradiction judgment section detects the logical state of each signal line under the implication by a first implication section and judges whether the logical state of every signal line is estimated as “0,” “1,” or “X” unless a contradiction is detected. When it is judged that logical state estimation is not completed, a U(Unknown)-state retrieval section retrieves an Unknown-state signal line whose logical state is incomplete and retrieves a signal line connected to an error propagation path through a gate. A detected signal line is decided as “0,” a decision level showing a decision frequency is increased by 1, and implication is restarted by a first implication section.