Abstract: A data link layer switch includes a switching mechanism coupled to several port interface controllers. The port interface controllers include an address table, an address learner, and an address matcher. The address table stores multicast addresses for hosts attached to the port interface controller. The address learner compares a destination address in an incoming packet to a target address, and stores a multicast address from the incoming packet in the address table when the destination address matches the target address. The address matcher compares a destination address in an outgoing packet to the multicast addresses stored in the address table, and transmits the outgoing packet when the destination address matches one of the multicast addresses.

Abstract: A self-testing smart memory (28) is provided in which memory test circuitry (46) within the smart memory (28) writes a pattern to a data RAM (32) and a broadcast RAM (34) and then reads the data RAM (32) and the broadcast RAM (34) to determine if any failures exist within the memory locations. Furthermore, a data path tester (50) determines the functionality of a data path (30) within smart memory (28).

Abstract: A sampled amplitude read channel is disclosed for disk storage systems that employs an EPR4 remod/demod sequence detector. To reduce the complexity of timing recovery, gain control and adaptive equalization, the channel samples are initially equalized into a PR4 partial response so that a simple slicer circuit can generate estimated sample values. The PR4 equalized channel samples are then passed through a 1+D filter to generate EPR4 equalized channel samples which are processed by an EPR4 Viterbi sequence detector to generate a preliminary binary sequence. The preliminary binary sequence is remodulated into an estimated or ideal PR4 sample sequence which is subtracted from the PR4 equalized channel samples to generate an error sample sequence. An error pattern detector processes the error sample sequence to detect the dominant error events associated with the EPR4 Viterbi sequence detector.

Abstract: A data receiving channel has a signal converter that converts a received signal into a digital signal. The digital signal is then applied to a Viterbi detector that will provide, as an output, a stream of digital signals that have a maximum likelihood of being accurate. Error correction is performed at the bit level through calculation of the error between the received signal and the maximum likelihood estimate signal produced by the Viterbi detector.

Abstract: The present invention is directed to a detector circuit for detecting a binary data sequence from an input sequence of data. The detector circuit comprises a storage device for storing a plurality of values which correspond to the squared errors computed between all possible input values to the circuit and all possible noiseless responses. The storage device outputs certain of the stored values in response to the input sequence of data. The detector circuit also comprises a Viterbi circuit responsive to the storage device. The Viterbi circuit computes a binary decision output from the outputted stored values. The present invention is also directed to a method for detecting a binary data sequence from an input sequence of data.