Generation Of Test Inputs, E.g., Test Vectors, Patterns Or Sequences, Etc. (epo) Patents (Class 714/E11.177)
  • Patent number: 10983902
    Abstract: Arrangements described herein relate to generation of test plans. A list of test case selection criteria can be presented to each of a plurality of stakeholders. At least one user input is received from each of the plurality of stakeholders selecting at least one test case selection criterion from the list of test case selection criteria and, for each selected test case selection criterion, assigning a criterion priority. Test cases, which correspond to the selected test case selection criteria, can be automatically selected to include in a candidate test plan. A candidate priority can be automatically assigned to each test case selected to be included in the candidate test plan. The processor selects the test cases to include in the candidate test plan and assigns the candidate priorities to the selected test cases based on processing the criterion priorities assigned to the selected test case selection criteria by the stakeholders.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: April 20, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Muhtar B. Akbulut, Mario A. Maldari
  • Patent number: 10642717
    Abstract: A method, computer program product, and computing system device for monitoring a plurality of individual actions executed on at least a portion of a software application. It may be determined whether the plurality of individual actions executed on the at least a portion of the software application complete at least one test case of a plurality of test cases. The at least one test case may be marked as completed based upon, at least in part, determining that the plurality of individual actions executed on the at least a portion of the software application complete the at least one test case of the plurality of test cases.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: May 5, 2020
    Assignee: International Business Machines Corporation
    Inventors: John Girata, Jr., Bryan R. Florkiewicz, Martin Presler-Marshall
  • Publication number: 20150012785
    Abstract: A method for data storage includes receiving in a memory device data for storage in a group of analog memory cells. The data is stored in the group by performing a Program and Verify (P&V) process, which applies to the memory cells in the group a sequence of programming pulses and compares respective analog values of the memory cells in the group to respective verification thresholds. Immediately following successful completion of the P&V process, a mismatch between the stored data and the received data is detected in the memory device. An error in storage of the data is reported responsively to the mismatch.
    Type: Application
    Filed: January 24, 2012
    Publication date: January 8, 2015
    Applicant: ANOBIT TECHNOLOGIES
    Inventors: Eyal Gurgi, Yoav Kasorla, Barak Rotbard, Shai Ojalvo
  • Publication number: 20140143619
    Abstract: Systems and methods are provided for reusing existing test structures and techniques used to test memory data to also test error correction code logic surrounding the memories. A method includes testing a memory of a computing system with an error code correction (ECC) logic block bypassed and a first data pattern applied. The method further includes testing the memory with the ECC logic block enabled and a second data pattern applied. The method also includes testing the memory with the ECC logic block enabled and the first data pattern applied.
    Type: Application
    Filed: November 21, 2012
    Publication date: May 22, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin W. GORMAN, Michael R. OUELLETTE, Patrick E. PERRY
  • Publication number: 20140129884
    Abstract: Embodiments of a register file test circuit are disclosed that may allow for determining write performance at low power supply voltages. The register file test circuit may include a decoder, a multiplexer, a frequency divider, and a control circuit. The decoder may be operable to select a register cell within a register file, and the control circuit may be operable to controllably activate the read and write paths through the selected register cell, allowing data read to be inverted and re-written back into the selected register cell.
    Type: Application
    Filed: November 7, 2012
    Publication date: May 8, 2014
    Applicant: APPLE INC.
    Inventors: Greg M. Hess, James E. Burnette, II
  • Publication number: 20140129890
    Abstract: A method for producing a LDPC encoded test pattern for media in a LDPC based drive system includes adding error detection code data to a predominantly zero bit test pattern and adding additional zero bits to produce a test pattern of a desirable length. The test pattern may then be scrambled to produce a desirable flaw detection test pattern. The flaw detection test pattern may then be encoding with an LDPC code, or other error correction code with minimal disturbance to the run length constraints of the data pattern, and written to a storage medium.
    Type: Application
    Filed: November 8, 2012
    Publication date: May 8, 2014
    Applicant: LSI CORPORATION
    Inventors: Jefferson E. Singleton, Shaohua Yang, Bruce A. Wilson, Keenan T. O'Brien
  • Publication number: 20140115396
    Abstract: A method, apparatus and product to be used in verification. The method comprising: based on a test generation input that defines a plurality of requirements automatically determining a mutated test generation input, wherein the mutated test generation input defining a mutated requirement which is absent from the test generation input, wherein the mutated requirement is based on a requirement of the plurality of requirements and contradicts, at least in part, the plurality of requirements; and generating one or more test-cases based on the mutated test generation input, whereby the one or more test-cases violate at least one requirement of the test generation input.
    Type: Application
    Filed: October 24, 2012
    Publication date: April 24, 2014
    Inventors: Laurent Fournier, Anatoly Koyfman, Michal Rimon, Avi Ziv
  • Publication number: 20140095934
    Abstract: Accessing a problem report data store including customer problem reports. Each customer problem report includes configuration and platform data. Calculating a number of instances each platform is stored, and identifying platforms that satisfy a platform threshold. Calculating a number of instances each configuration is stored, and identifying configurations that satisfy a configuration threshold. Calculating a number of instances each platform is associated with each configuration, and generating a data structure with a plurality of nodes and edges. Each of the nodes identifies one of the platforms and configurations. The weight of the edge connecting a platform to a configuration indicates a number of instances that the platform is associated with the configuration in the data store. Identifying a weighted edge that satisfies a weight threshold, where the weighted edge connects a first platform to a first configuration and, in response, generating a test case for development of a software product.
    Type: Application
    Filed: October 2, 2012
    Publication date: April 3, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jerry A. Dancy, John Hind, Geoffrey D. Lubold, Brad B. Topol
  • Publication number: 20140089750
    Abstract: An apparatus and method is provided for switching input pins to scan channels to increase test coverage. In one embodiment, a scan system connects a small number of input pins to several scan channels so that the input pins may be selectively switched. The input pins may transmit independent test vectors to test a large number of test areas on a semiconductor chip. The scan system may include a switching device such as a multiplexer (MUX).
    Type: Application
    Filed: September 27, 2012
    Publication date: March 27, 2014
    Applicant: International Business Machines Corporation
    Inventor: International Business Machines Corporation
  • Publication number: 20140082421
    Abstract: A method is provided to test a modular integrated circuit (IC) comprising: testing a module-under-test (MUT) within the IC while causing a controlled toggle rate within a first neighbor module of the MUT; wherein the controlled toggle rate within the first neighbor module is selected so that toggling within the first neighbor module has substantially the same effect upon operation of the MUT that operation of the first neighbor module would have during actual normal functional operation of the first neighbor module.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 20, 2014
    Applicant: Cadence Design Systems, Inc.
    Inventors: Erik Jan Marinissen, Sergej Deutsch
  • Publication number: 20140068335
    Abstract: A system, apparatus, method, and computer program product for dynamically loading IT products and scaling those loads in a predictive manner are disclosed. Dynamic loading and scaling is performed by generating a load on a computing product with one or more first load generators, increasing the load over time until the first load generators reach their capacity for generating load, monitoring the capacity of the first load generators as the load is increased, provisioning one or more second load generators to generate additional load as any of the first load generators approaches its capacity, increasing the load generated by the second load generators over time until the one or more second load generators reach their capacity for generating load or the computing product reaches a performance goal, and continuing to provision second load generators until the computing product reaches the performance goal.
    Type: Application
    Filed: August 31, 2012
    Publication date: March 6, 2014
    Applicant: CA, INC.
    Inventors: Cameron David BROMLEY, John Joseph MICHELSEN, III, Ricardo Emilio Denis
  • Publication number: 20140068358
    Abstract: The present invention is related to systems and methods for harmonizing testing and using a storage media.
    Type: Application
    Filed: August 28, 2012
    Publication date: March 6, 2014
    Inventors: Shaohua Yang, Bruce A. Wilson
  • Publication number: 20140047272
    Abstract: The present disclosure relates to a method and system for configuring a computing system, such as a cloud computing system. A method includes selecting, based on a user selection received via a user interface, a workload for execution on a cluster of nodes of the computing system. The workload is selected from a plurality of available workloads including an actual workload and a synthetic test workload. The method further includes configuring the cluster of nodes of the computing system to execute the selected workload such that processing of the selected workload is distributed across the cluster of nodes. The synthetic test workload may be generated by a code synthesizer based on a set of user-defined workload parameters provided via a user interface that identify execution characteristics of the synthetic test workload.
    Type: Application
    Filed: August 7, 2012
    Publication date: February 13, 2014
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Mauricio Breternitz, Keith A. Lowery, Patryk Kaminski, Anton Chernoff
  • Publication number: 20140026004
    Abstract: The present invention is related to systems and methods for defect scanning.
    Type: Application
    Filed: July 17, 2012
    Publication date: January 23, 2014
    Inventors: Ming Jin, Fan Zhang, Lei Chen, AbdelHakim S. Alhussein
  • Patent number: 8606538
    Abstract: A method of preparing a test for an electronic system including a plurality of pieces of equipment interconnected by at least one communications link, in which method, in order to perform the test, use is made of a test bench appropriate for the electronic system under test, which test bench is connected to the system and controlled in application of a command sequence established from at least one informal functional specification; while preparing the test, the informal functional specification, the command sequence, and a link identifying the informal functional specification from which the command sequence was established are all recorded so that after execution of the command sequence and after the test results have been recorded, it is possible to read the link and identify unambiguously the informal functional specification that corresponds to the test results obtained.
    Type: Grant
    Filed: July 11, 2008
    Date of Patent: December 10, 2013
    Assignee: Eurocopter
    Inventors: Gilles Cahon, Christian Gaurel
  • Publication number: 20130326274
    Abstract: A method for testing a device under test (DUT) during a test sequence. In accordance with one embodiment, during a regular, pre-defined test sequence, data packets are transferred from a tester to a device under test (DUT) containing data related to at least one of an identification parameter of the DUT, an operational characteristic of the DUT and a request for data. Examples of such transferred data include address data for identifying the DUT (e.g., a unique media access control (MAC) address) and calibration data for controlling an operational characteristic of the DUT (e.g., signal power levels, signal frequencies or signal modulation characteristics). In accordance with another embodiment, the DUT retrieves and transmits data to the tester, either in response to the request for data or as a preprogrammed response to its synchronization with the tester.
    Type: Application
    Filed: June 1, 2012
    Publication date: December 5, 2013
    Applicant: LITEPOINT CORPORATION
    Inventors: Christian Volf OLGAARD, Sheguang YIN, John Christopher LUKEZ
  • Publication number: 20130318407
    Abstract: A test mode signal generation circuit includes a pre-decoder block configured to output first and second control signals and test address signals in response to first and second address signals, and a signal generation block configured to decode the test address signals in response to the first control signal and generate first and second test mode group signals each including a plurality of test mode signals.
    Type: Application
    Filed: September 5, 2012
    Publication date: November 28, 2013
    Applicant: SK HYNIX INC.
    Inventors: Yu Ri LIM, Min Su PARK
  • Publication number: 20130318398
    Abstract: An exemplary system may include debug capabilities. In one embodiment, the system obtains a debug address. For a process associated with the system, the system determines whether a memory page used by the process includes the debug address. Upon determining that the memory page used by the process includes the debug address, the system marks the memory page for debug and sends the memory page to a swap area.
    Type: Application
    Filed: May 23, 2012
    Publication date: November 28, 2013
    Applicant: RED HAT, INC.
    Inventors: Anton Arapov, Jiri Olsa
  • Publication number: 20130305090
    Abstract: A test configuration resource manager and a method of managing test configuration resources in a network test system. A computer readable storage medium may store instructions that, when executed, cause a computing device to receive a user input identifying a portion of a first test configuration, store the identified portion of the first test configuration as a test configuration resource in a library of test configuration resources, receive a user input identifying a stored test configuration resource, retrieve the identified stored test configuration resource, and incorporate the retrieved test configuration resource into a second test configuration. The library of test configuration resources may include one or more of port resources, protocol resources, and traffic resources.
    Type: Application
    Filed: May 9, 2012
    Publication date: November 14, 2013
    Applicant: Ixia
    Inventors: Jesper Kristiansen, Alok Srivastava, Razvan Stan
  • Publication number: 20130262942
    Abstract: A flash memory lifetime evaluation method is introduced for dynamically amending, detecting and evaluating an ideal lifetime (or standard lifetime) of a built-in or expanded flash memory of an electronic device, and the method comprises the steps of calculating the ideal lifetime according to the capacity of the flash memory, creating a spare area in at least one of the flash memory and the control center, generating a testing command by the control center and transmitting the testing command to the flash memory such that the flash memory executes a memory test according to the testing command, and the flash memory feeds back a test result to the spare area as an amend parameter according to the memory test, and the control center retrieves the amend parameter stored in the spare area to selectively amend the ideal lifetime by the amend parameter.
    Type: Application
    Filed: March 27, 2012
    Publication date: October 3, 2013
    Inventor: Yung-Chiang CHU
  • Publication number: 20130246867
    Abstract: This technology relates to smoothly performing a test on a memory circuit having a high memory capacity while reducing the size of a test circuit. A test circuit according to the present invention includes a test execution unit configured to perform a test on a target test memory circuit, an internal storage unit configured to store data for the test execution unit, and a conversion setting unit configured to set a part of or the entire storage space of the target test memory circuit as an external storage unit for storing the data for the test execution unit.
    Type: Application
    Filed: September 5, 2012
    Publication date: September 19, 2013
    Inventors: Hyung-Gyun YANG, Hyung-Dong LEE, Yong-Kee KWON, Young-Suk MOON, Hong-Sik KIM
  • Publication number: 20130219220
    Abstract: A method for generating a replayable testing script for iterative use by an automated testing utility may include recording a plurality of scripts, each script relating to a separate iteration of a transaction between a user and a tested application performed by an operator. The method may also include comparing the recorded scripts to identify a location of a data item by finding different values in a pair of corresponding locations in the recorded scripts, indicative of a dynamic data item. The method may further include generating the replayable testing script comprising one of the recorded scripts and having a variable parameter at the identified location of the dynamic data item.
    Type: Application
    Filed: February 17, 2012
    Publication date: August 22, 2013
    Inventors: Moshe Eran Kraus, Lior Manor, Amichai Nitsan, Meidan Zemer
  • Publication number: 20130198567
    Abstract: In an exemplary embodiment, a system includes a memory and a processor communicatively coupled to the memory. The processor is operable to receive a first indication that a first component is selected from a plurality of components and receive a second indication that a second component is selected from the plurality of components. The processor is further operable to determine a first instruction associated with the first component, wherein the first instruction corresponds to first computer logic for executing the first at least one test action, and determine a second instruction associated with the second component, wherein the second instruction corresponds to second computer logic for executing the second at least one test action. The processor is also operable to generate a test case file comprising the first instruction and the second instruction and associate the test case file with an application under test.
    Type: Application
    Filed: January 31, 2012
    Publication date: August 1, 2013
    Applicant: Bank of America Corporation
    Inventors: Istiak Ahmed, Shanmugaraja Senthilnayagam
  • Publication number: 20130173971
    Abstract: A boundary scan chain for stacked memory. An embodiment of a memory device includes a system element and a memory stack including one or more memory die layers, each memory die layer including input-output (I/O) cells and a boundary scan chain for the I/O cells. A boundary scan chain of a memory die layer includes a scan chain portion for each of the I/O cells, the scan chain portion for an I/O cell including a first scan logic multiplexer a scan logic latch, an input of the scan logic latch being coupled with an output of the first scan logic multiplexer, and a decoder to provide command signals to the boundary scan chain.
    Type: Application
    Filed: December 29, 2011
    Publication date: July 4, 2013
    Inventor: David J. Zimmerman
  • Publication number: 20130117617
    Abstract: The method of generating an address scramble includes receiving address information for each of a plurality of memory cells included in a semiconductor memory device and the address information that includes a logical address and a physical address corresponding to each of the memory cells; generating an address scramble logical expression, the address scramble logical expression relating logical addresses to physical addresses based on the address information; and reducing the address scramble logical expression using a given algorithm.
    Type: Application
    Filed: November 1, 2012
    Publication date: May 9, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Samsung Electronics Co., Ltd.
  • Publication number: 20130117609
    Abstract: System and method for generating an enhanced test case for a computer application is disclosed. The system provides a test preparation engine including an entity extracting module and an assembly extractor for collecting information about the computer application and corresponding database schema for generating a global report. The test case designing module designs one or more test cases by using the global report. The test case execution engine includes an input evaluation module and generates an actual result for each executed test case and an expected result for one or more database query. The report generating module includes a result storage device, a result comparator and a result analyses module and performs analyses of the actual test case result and the expected results.
    Type: Application
    Filed: December 14, 2011
    Publication date: May 9, 2013
    Applicant: TATA CONSULTANCY SERVICES LIMITED
    Inventors: Madhu Dande, RameshKumar Perumal
  • Publication number: 20130111281
    Abstract: An integrated circuit includes a storing unit; and a tester that executes a write and read test on the storing unit based on received test information including a pair of address and data, the tester including: a first retain unit that retains, when a write is made based on the test information, the first write address and the first write data used in the write; a first generator that generates, based on the first write address retained in the first retain unit, a first read address used for reading first read data from the first read address in the storing unit simultaneously with writing second write data to a second write address based on the test information; and a second generator that generates, based on the first write data retained in the first retain unit, an expected value of the first read data.
    Type: Application
    Filed: August 31, 2012
    Publication date: May 2, 2013
    Applicant: FUJITSU LIMITED
    Inventors: Masahiro Yanagida, Hiroyuki Fujimoto
  • Publication number: 20130111268
    Abstract: A testing device is capable of simulating plugging and unplugging operations in relation to an USB port of an electronic device. The testing device comprises a processing unit to detect an electrical connection between the testing device and the USB port, and to control an indicator to cycle between a state of recognizability and a state of unrecognizability even though a physical connection to the USB port of the electronic device exists at all times. The state of recognizability indicates the testing device is capable of being recognized by the electronic device, and the state of unrecognizability indicates the testing device is incapable of being recognized by the electronic device. Reading and writing tests are carried out by the testing device each time that recognizability is indicated, to repeatedly test the integrity of the USB port being tested.
    Type: Application
    Filed: December 27, 2011
    Publication date: May 2, 2013
    Applicants: HON HAI PRECISION INDUSTRY CO., LTD., HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD.
    Inventors: Yuan-Yuan GONG, Zheng-Quan PENG, Qiong CAI
  • Publication number: 20130103992
    Abstract: A burn-in method for an embedded Multi Media Card (eMMC), and a test board using the same, and an eMMC tested by the same. The disclosed burn-in method comprises the steps as below: writing a test pattern to a flash memory of the eMMC; electrically connecting a command line of the eMMC to ground to operate the eMMC in a boot state; performing a burn-in procedure on the flash memory when the eMMC is in the boot state and the test pattern is recognized as being contained in the flash memory; and collecting a test report during the burn-in procedure, wherein the test report is stored in the flash memory.
    Type: Application
    Filed: April 13, 2012
    Publication date: April 25, 2013
    Applicant: Silicon Motion, Inc
    Inventors: Chia-Fang Chang, Hsu-Ping Ou
  • Publication number: 20130091393
    Abstract: A transmission test device that performs a transmission test in a transmission path includes a determining unit and a killer pattern transfer unit. The determining unit acquires an abnormality incidence rate representing a rate of abnormality having occurred in test data in a transmission path, and determines whether or not the abnormality incidence rate is lower than a predetermined reference value. The killer pattern transfer unit changes the test data and transmits changed test data when the determining unit determines that the abnormality incidence rate is lower than the predetermined reference value.
    Type: Application
    Filed: August 14, 2012
    Publication date: April 11, 2013
    Applicant: FUJITSU LIMITED
    Inventor: Tatsuki KOBAYASHI
  • Publication number: 20130091396
    Abstract: A packet-based testing capability is provided. The packet-based testing capability is configured to provide a packet-based JTAG (PJTAG) protocol. The PJTAG protocol is an asynchronous protocol configured to support the synchronous JTAG protocol. The PJTAG protocol is configured to convert between JTAG signals and packets configured to transport information of the JTAG signals (e.g., to convert JTAG signals into PJTAG packets at an interface from a JTAG domain to a PJTAG domain and to convert PJTAG packets into JTAG signals at an interface from a PJTAG domain to JTAG domain).
    Type: Application
    Filed: October 7, 2011
    Publication date: April 11, 2013
    Inventor: Michele Portolan
  • Publication number: 20130086457
    Abstract: A method for detecting codewords in solid-state storage devices. The method includes the steps of: obtaining respective read signals by reading memory cells that stores a group of codewords, where each of the read signals includes N signal components corresponding to respective symbols of the codeword; producing an ordered read signal by ordering the components of each of the read signals according to a signal level; producing an average read signal by averaging corresponding components of the ordered read signals; determining a reference signal level that corresponds to each of q levels of the memory cells in relation to the average read signal with predefined probabilities of each symbol value occurring at each symbol position in the codeword, where the symbols of the codeword are ordered according to the symbol value; and detecting the codeword corresponding to each of the read signal in relation to the reference signal levels.
    Type: Application
    Filed: September 19, 2012
    Publication date: April 4, 2013
    Applicant: International Business Machines Corporation
    Inventor: International Business Machines Corporation
  • Publication number: 20130086423
    Abstract: Provided is a test apparatus including: an address generator that generates an address of a memory under test; a selector that selects whether to perform bit inversion on the address generated by the address generator before supplying the address to the memory under test; an inversion processing section that outputs the address generated by the address generator after performing bit inversion on the address if the selector has selected in the affirmative, and outputs the address generated by the address generator without performing any bit inversion on the address if the selector has selected in the negative; and a supply section that supplies, to the memory under test, the address having undergone inversion control outputted from the inversion processing section and an inversion cycle signal that indicates whether the address outputted from the inversion processing section is bit inverted or not.
    Type: Application
    Filed: July 4, 2012
    Publication date: April 4, 2013
    Applicant: ADVANTEST CORPORATION
    Inventor: Takeshi KAWAKAMI
  • Publication number: 20130073907
    Abstract: A method of testing a plurality of DUTs includes providing a plurality of shift registers to test a plurality of cores in each DUT, supplying test input data, a test mode input signal, a test clock signal, and a test reset signal to the shift registers and cores, receiving a master bit, a first control value, and a second control value, based on the test input data and the test mode input signal, according to the test clock signal and the test reset signal, selecting at least one core and a test method, according to the first control value, selecting a target DUT according to the master bit or the second control value, simultaneously testing and debugging the selected core according to the test method, and outputting the test data output of the target DUT to check a result of the testing when an output enable signal is received.
    Type: Application
    Filed: August 15, 2012
    Publication date: March 21, 2013
    Inventor: Dong Kwan Han
  • Patent number: 8400334
    Abstract: An asymmetric approach for compressing digital data, or digitized analog data, uses dictionary-based compression for a transmitter and receiver communicating over a lossy unidirectional communication channel. The transmitter is responsible for generating active dictionaries, selecting appropriate dictionaries for compressing data, retiring old dictionaries, and sending new dictionaries to the receiver. The receiver passively stores the dictionaries from the transmitter and uses the right stored dictionary to decompress data received from the transmitter, as indicated by instructions in the compressed data set.
    Type: Grant
    Filed: December 31, 2009
    Date of Patent: March 19, 2013
    Assignee: Thomson Reuters Global Resources (TRGR)
    Inventors: Chik Chung Lee, Wai Ho Wan
  • Publication number: 20130055026
    Abstract: Playback data is created for testing a server. Recorded data that includes transactions executed in a session established between a client and a server at a designated point in time is extracted. A reduction process that includes deleting data related to certain transactions from the extracted recorded data is performed. The certain transactions are part of a specific transaction group which includes transactions that were executed on or before the designated point in time and includes a transaction that was executed without requiring the execution of a predetermined prior transaction. The playback data is output.
    Type: Application
    Filed: August 22, 2012
    Publication date: February 28, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hisanori Hatano, Masahiko Kosuda, Mika Shimogawa, Masafumi Shimotsuji
  • Publication number: 20130055027
    Abstract: A low cost error-based program testing apparatus and method are provided. The testing apparatus according to an embodiment of the present invention generates error programs by adding errors to a test target program, selects a test target error program associated with test data among the error programs using error information obtained through the error addition, receives the test data to execute the test target error program, and tests for presence/absence of the errors. Accordingly, it is possible to reduce a text execution time and testing costs.
    Type: Application
    Filed: July 16, 2012
    Publication date: February 28, 2013
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Yu-Seung Ma, Seon-Tae Kim
  • Publication number: 20130031410
    Abstract: Diagnostic apparatus for computers, including a diagnoser that connects to a PC, including an SD connector for connecting the diagnoser to an SD port of a PC, a storage medium for storing diagnostic program code that automatically runs on the PC via the SD connector, in response to connecting the diagnoser to the SD port of the PC, wherein the diagnostic program code performs specific diagnostic tests on the PC in response to input instructions, and generates test results as output, a modem for receiving input instructions from a remote online help-desk facility, specifying which diagnostic tests the diagnostic program code should perform on the PC, and for transmitting the test results to the help-desk facility, and a processor for controlling the storage medium and the modem.
    Type: Application
    Filed: September 13, 2012
    Publication date: January 31, 2013
    Inventors: Hagay Katz, Eyal Bychkov, Itay Sherman
  • Publication number: 20130019130
    Abstract: Testing electronic memories based on fault and test algorithm periodicity. A processor unit for testing an electronic memory includes a built-in self-test (BIST) finite state machine, an address generator, a data generator, a test algorithm generation unit, a programmable test algorithm register, and a test algorithm register control unit. A memory wrapper unit for testing an electronic memory includes an operation decoder, a data comparator, and an electronic memory under test. The method includes constructing a fault periodic table having columns corresponding with test mechanisms, and rows corresponding with fault families. A first March test sequence and second March test sequence are selected according to respective fault families and test mechanisms, and applied to an electronic memory. The electronic memory under test is determined to be one of acceptable and unacceptable based on results of the first March test sequence and the second March test sequence.
    Type: Application
    Filed: July 15, 2011
    Publication date: January 17, 2013
    Applicant: SYNOPSYS INC.
    Inventors: Aram HAKHUMYAN, Gurgen Harutyunyan, Samvel Shoukourian, Valery Vardanian, Yervant Zorian
  • Publication number: 20130019132
    Abstract: A method and system for testing an electronic memory. The method includes subjecting the electronic memory to a first test condition of a predetermined set of test conditions. The method also includes testing functionality of the electronic memory, a first plurality of times, for the first test condition using a predetermined test algorithm. The method further includes checking availability of a second test condition from the predetermined set of test conditions if the functionality of the electronic memory is satisfactory. Further, the method includes testing the functionality of the electronic memory, a second plurality of times, for the second test condition using the predetermined test algorithm if the second test condition is available. Moreover, the method includes accepting the electronic memory for use in a product if the functionality of the electronic memory is satisfactory.
    Type: Application
    Filed: July 15, 2011
    Publication date: January 17, 2013
    Applicant: SYNOPSYS INC.
    Inventors: Karen AMIRKHANYAN, Hayk Grigoryan, Gurgen Harutyunyan, Tatevik Melkumyan, Samvel Shoukourian, Alex Shubat, Valery Vardanian, Yervant Zorian
  • Publication number: 20130007524
    Abstract: Network survivability is quantified in such a way that failure cases can be compared and ranked against each other in terms of the severity of their impact on the various performance measures associated with the network. The degradation in network performance caused by each failure is quantified based on user-defined sets of thresholds of degradation severity for each performance measure. Each failure is simulated using a model of the network, and a degradation vector is determined for each simulated failure. A comparison function is defined to map the degradation vectors into an ordered set, and this ordered set is used to create an ordered list of network failures, in order of the network degradation caused by each failure.
    Type: Application
    Filed: March 6, 2012
    Publication date: January 3, 2013
    Applicant: OPNET Technologies, Inc.
    Inventors: Vanko VANKOV, Vinod JEYACHANDRAN, Pradeep K. SINGH, Alain J. COHEN, Shobana NARAYANASWAMY
  • Publication number: 20120317454
    Abstract: Disclosed are representative examples of methods, apparatus, and systems for generating test patterns targeting multiple faults using Boolean Satisfiability (SAT)-based test pattern generation methods. A SAT instance is constructed based on the circuit design information and a set of faults being targeted. A SAT solving engine is applied to the SAT instance to search for a test pattern for detecting the set of faults. The SAT instance or the SAT solving engine may be modified so that the SAT solving engine will search for a test pattern for detecting a maximum number of faults in the set of faults.
    Type: Application
    Filed: June 9, 2011
    Publication date: December 13, 2012
    Inventors: RENE KRENZ-BAATH, Andreas Glowatz, Friedrich Hapke
  • Publication number: 20120317449
    Abstract: A device for testing a semiconductor memory device, the device including a code table that is configured to store at least a first received code and a second received code received via a host interface, a pattern generation engine that is configured to determine a third code based on at least one of the first and the second received codes stored in the code table and to output the third code, in response to a request to perform a test operation, received via the host interface, and a signal generation unit that is configured to generate control signals for testing the semiconductor memory device, based on the third code received from the pattern generation engine.
    Type: Application
    Filed: June 7, 2012
    Publication date: December 13, 2012
    Inventor: Jung Rae KIM
  • Publication number: 20120311392
    Abstract: An automated regression testing intermediary configured to accept a first set of automated test instructions from an application testing tool. A data structure comprising predefined fields is configured so when a test instruction is received from the application testing tool, a command will be used to identify at least one field of the data structure that will be populated with a parameter test instruction. A library of generic target automated test instructions is provided. Each generic test instruction has a form and format different from the received test instruction. The intermediary is configured to select generic target automated test instructions from the library and populate selected generic target automated test instructions with parameters obtained from the data structure such that the resulting created target-specific automated test instructions can be used to regression test the application under test.
    Type: Application
    Filed: June 1, 2011
    Publication date: December 6, 2012
    Applicant: MORGAN STANLEY
    Inventor: Amit Agrawal
  • Publication number: 20120297250
    Abstract: A mechanism for verifying order of entities being processed by a device under test (DUT) is provided. The mechanism includes arranging the entities into a temporal order, and encoding the entities to maintain the temporal order of the entities and produce encoded entities with each being a random value. The encoded entities each have a one-to-one mapping to their corresponding one of the entities in the temporal order. The encoded entities are input into the DUT to verify its output, and responsive to detecting an error in the output corresponding to one encoded entity, the one encoded entity is decoded into a current decoded error entity. It is determined which is lower in the temporal order between the current decoded error entity and a previous decoded error entity. Responsive to the current decoded error entity being lower than the previous decoded error entity, the current decoded error entity is stored.
    Type: Application
    Filed: May 16, 2011
    Publication date: November 22, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Clinton E. Bubb, Chaitanya Kancherla, Roopesh A. Matayambath, Ralf Winkelmann
  • Publication number: 20120290889
    Abstract: A loopback card includes a connector configured to connect to an IO interface and emulate a storage device interface. The connector includes a port configured to receive a set of signals from the IO interface and transmit them to a redriver. The connector is configured to receive the set of signals from the redriver and transmit them from the redriver to the IO interface. The connector includes control signal inputs configured to receive control signals from the IO interface. The connector further includes one or more logic gates configured to receive the control signals. The one or more logic gates apply a logic operation on the control signals to generate an output and route the output to the IO interface through the connector. The redriver is operably connected to the port and configured to receive the set of signals from the port and transmit them back to the port.
    Type: Application
    Filed: May 11, 2012
    Publication date: November 15, 2012
    Inventors: Craig Anthony Klein, Aleksander Jaworski, John Roy Gaudet, Steven Scott Burroughs
  • Publication number: 20120290888
    Abstract: One embodiment of a Test Signal generated by Test Signal Synthesis 10 being coupled, by a method of Coupling 12, to an Antenna 14, a Receiver 16 and a Method of Verification 18; for the transmission of a Test Signal to verify the operation of the Receiver Chain of equipment in Applications receiving Intermittent Signals.
    Type: Application
    Filed: May 9, 2012
    Publication date: November 15, 2012
    Inventor: James Francis Harvey
  • Publication number: 20120254662
    Abstract: The invention provides an automated test method for testing a server. In one embodiment, the server comprises a plurality of sensors, a preboot Dynamic System Analyzer (pDSA), and a Baseborad Management Controller (BMC). First, a connection is built with the server via a network. A remote control program is then used to display a user interface of the pDSA on a screen. A keyboard-mouse automation program is then used to control a keyboard to perform a series of keyboard control operations and control a mouse to perform a series of mouse control operations for simulating user instructions. The remote control program is then used to send the keyboard control operations and the mouse control operations to the server via the network, thereby controlling the pDSA to perform testing of the sensors of the server to generate a test log.
    Type: Application
    Filed: August 31, 2011
    Publication date: October 4, 2012
    Applicant: WISTRON CORP.
    Inventor: Fei-Teng CHEN
  • Publication number: 20120254663
    Abstract: A semiconductor memory device is disclosed that includes an ODT circuit configured to be connected to a bus which transmits a data signal or a data strobe signal between a memory block and an input-output terminal; a first switch configured to be inserted into the bus between the memory block and the ODT circuit; a mode controller configured to switch off the first switch during a test of the memory block; and an oscillator configured to be connected to the ODT circuit, wherein a test signal is supplied to the ODT circuit from the oscillator during the test of the memory block.
    Type: Application
    Filed: March 27, 2012
    Publication date: October 4, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Rikizo Nakano, Osamu Ishibashi, Sadao Miyazaki
  • Publication number: 20120226951
    Abstract: Provided is a test apparatus comprising a plurality of pattern output sections. In a high-speed mode, each pattern output section outputs, as pattern data corresponding to at least one of a plurality of partial periods, the pattern data corresponding to an input pattern input to the pattern output section and the pattern data corresponding to input patterns input to other pattern output sections.
    Type: Application
    Filed: February 24, 2012
    Publication date: September 6, 2012
    Applicant: ADVANTEST CORPORATION
    Inventor: Toshiyuki NEGISHI