Abstract: One or more embodiments of the invention enable a memory device to load its memory array with desired background data, such as to reduce total test time and costs associated with testing. A background data loading circuit according to one embodiment of the invention includes a buffer, a data loading circuit, and a pattern generating logic. The buffer is coupled to the array of memory cells. The data loading circuit is coupled to load data into the buffer to be transferred to a respective row of the memory cells. The pattern generating logic is coupled to the data loading circuit. The pattern generating logic applies a pattern generating algorithm corresponding to a test mode when the memory devices is in the test mode and generates patterns of data each for a respective row of the memory cells according to the pattern generating algorithm.

Abstract: Methods, apparatus, and systems for diagnosing failing scan cells from compressed test responses are disclosed herein. For example, in one nonlimiting exemplary embodiment, at least one error signature comprising multiple bits (including one or more error bits) is received. Plural potential-error-bit-explaining scan cell candidates are evaluated using a search tree. A determination is made as to whether one or more of the evaluated scan cell candidates explain the error bits in the error signature and thereby constitute one or more failing scan cells. An output is provided of any such one or more failing scan cells determined. Tangible computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods are also provided. Tangible computer-readable media comprising lists of failing scan cells identified by any of the disclosed methods are also provided.

Abstract: The present disclosure generally relates to the testing of a system that includes software or hardware components. In some embodiments, a testing framework generates a set of test cases for a system under test using a grammar. Each test case may perform an action, such as provide an input to the system under test, and result in an output from the system under test. The inputs and outputs are then compared to the expected results to determine whether the system under test is performing correctly. Prior to generating the set of test cases from the grammar, the testing framework processes the grammar to identify attributes of the test cases to be derived from the grammar and facilitates the modification of the grammar.

Abstract: A method comprising the steps of (A) generating a code, (B) applying one or more constraint constructs to the code, (C) generating a coverage code and a second code in response to applying the constraint constructs to the code, (D) generating a third code in response to the code, and (E) generating one or more assembly language tests in response to the second code.

Abstract: A method, apparatus and computer program product are provided for implementing AC scan diagnostic of delay and AC scan chain defects in an integrated circuit chip under test using Functional Architecture Verification Patterns (AVPs) for enabling rapidly localizing identified defects to a failing Shift Register Latch (SRL). An Architecture Verification Pattern (AVP) test pattern set is generated using a chip design input and simulation. AVP test vectors are applied for starting chip clocks and initiating testing, such as Logic Built-In-Self-Test (LBIST).

Abstract: The invention relates, inter alia, to a method for testing a programmable memory cell having a particular memory state, the method involving the following steps of: applying a first read signal to the memory cell, with the result that the memory cell provides a first memory signal which represents its memory state; comparing the first memory signal with a threshold value in order to obtain a first comparison result; applying a second read signal to the memory cell, with the result that the memory cell provides a second memory signal which represents its memory state; comparing the second memory signal with the threshold value in order to obtain a second comparison result; assessing the integrity of the memory state using the two comparison results.

Abstract: A testing system for a device under test (DUT) includes a test parameter-generating device and a platform module. The test parameter-generating device stores test information, and is operable so as to execute a test algorithm, so as to generate a transmission signal upon execution of the test algorithm, and so as to generate a test environment with reference to the transmission signal. The platform module is operable so as to conduct testing of the DUT using the test information stored in the test parameter-generating device under the test environment generated by the test parameter-generating device.

Abstract: A constrained random test bench methodology employing an instruction abstraction layer. The instruction abstraction layer includes an instruction streamer for generating random test instruction sequences that preserve instruction order dependencies and randomly selecting data values from a valid range of data values. Multiple instruction streamers may be employed to simulate interrupt handlers and other functional design units sharing a control command bus. A priority scheduler sequences the instruction sequences generated by multiple instruction streamers based on a specified priority scheme.

Abstract: A test system in an integrated circuit includes a boundary scan cell. The boundary scan cell includes a first storage element and a second storage element connected in series with the first storage element. The boundary scan cell also includes initialization logic connected between an output of the first storage element and an input of the second storage element. The initialization logic provides the output of the first storage element to the input of the second storage element unchanged during a first operating state, and provides an inverted version of the output of the first storage element to the input of the second storage element during a second operating state.

Abstract: A timing measurement circuit inside a memory chip delays balanced test signals for generating delayed test signals. Each of the delayed test signals is input a corresponding input pin of a memory subsystem of the memory chip. By adjusting delay amount of the delayed test signals, AC timing parameters of the memory subsystem are tested and measured. When the timing measurement circuit is in ring oscillation, a resolution thereof is measured.

Abstract: A scan chain group structure in which a group of scan chains formed for each clock tree system in an LSI is subjected to a reconnection process so that the scan chain group is not present across a plurality of clock distribution regions obtained by dividing the clock-supplied region of the clock tree of one system and that the connection distance thereof in the distribution region becomes short, a test clock input mechanism in which test clocks to be input to the distribution regions are independent sub-clock phases, and an on/off mechanism of the clocks to be input to the distribution regions are realized. Further, the scan-in/out and scan test performed at the same time are limited in one region or between single regions, and tests in all regions and between all regions are carried out by a plurality of times of test steps.

Abstract: A method of testing memory modules comprising jumping through all addressable memory blocks a first and second time is disclosed. Each jumped-to address is determined by first XORing the last two bits of the previous address, and then XORing the first result with a bit representation of the previous jump direction for a second result. The second result determines the direction of the next jump, either upwards or downwards. Each jumped-to address is XORed with its contents, and the result is written to the address. For initially empty and defect-free memory, this results in all 1 values written for the first time jumping, and all 0 values written for the second time jumping. Finally, after the second time jumping, all addressable memory values are checked, and any non-0 value addresses are identified as defective memory cells.

Abstract: Embodiments of a scannable IO circuit featuring reduced latch count for pipelined memory architectures and test methodology are described. For a pipelined memory system performing at speed tests, the timing sequence for processing a test command comprises a precharge-read-precharge-write sequence for each clock cycle starting with the rising clock edge. The memory circuit utilizing this test command timing sequence comprises a sense amplifier and a single latch. The sense amplifier itself is used as a latch to implements scan functionality for the memory circuit. The memory device is incorporated into an integrated test wrapper circuit that executes back-to-back commands through serial compare operations using integrated scan flip-flop circuits. The test wrapper includes a fanout block and padded address scheme for testing multiple and disparate size memory devices in parallel.

Abstract: A method, system, and computer program product for identifying failures in multi-core processors, utilizing logic built-in self test (LBIST) technology. Multi-core processors, having LBIST and pseudo-random pattern generator (PRPG) circuitry, are tested. Controlled by the LBIST control logic, PRPG inputs a test pattern into scan chains within the cores of each device. A new test pattern is generated and executed during the scan shift phase of each LBIST loop. Logic output generated by each scan chain in the core is compared to other core logic output. Failures within the multi-core processors are determined by whether the logic output generated from a core, within a latch sequence, does not match the logic output of the other cores. If logic output, from a core within a latch sequence, does not match, then the latch number, loop number, and latch values are recorded as failed.

Abstract: A memory diagnosis apparatus include an intra-word testing unit that tests for a coupling fault in each bit in each word in a memory, an inter-word testing unit that tests for a coupling fault between words in each sub-array each being plural words in the memory, and an inter-block testing unit that tests for a coupling fault between sub-arrays in the memory.

Abstract: The present invention provides a method and system for routing a group of scan chains to a group of processor resources in a semiconductor chip. The group of processor resources is arranged in rows or columns. The group of processor resources in each row or column is connected through a plurality of scan chains. The first processor resource in each row or column is connected to input scan-chain pins, and the last processor resource in each row or column is connected to output scan-chain pins. A test-pattern generator, generating test signals, sends the test signals to the group of processor resources by using the group of scan chains within the semiconductor chip. The responses of the processor resources corresponding to the test signals are analyzed to detect and locate any error in the manufacture of the semiconductor chip.

Abstract: To reduce a circuit area of a data line driving circuit. The data line driving circuit includes a plurality of circuit blocks. A circuit block has shift register unit circuits, logical operation unit circuits and a control unit circuit. The control unit circuit specifies the operation period of the corresponding circuit block on the basis of the input and output signals of the shift register unit circuits and supplies a clock signal and an inverted clock signal to the shift register unit circuit.

Abstract: Logic level crossings in an integrated circuit are detected. According to an example embodiment, a reset signal is provided to a flip-flop (314) as a function of a logic level of an integrated circuit. A logic level crossing condition of the integrated circuit is indicated as a function of the reset condition of the flip flop. In one implementation, the flip-flop is reset when the logic level is different than an expected logic level. In another implementation, a pair of flip-flops (414, 418) are implemented such that only one flip-flop is reset at a particular logic level; if the logic level crosses, both flip-flops are reset. The aforesaid condition of both flip-flops being reset is used to indicate the logic level crossing.

Abstract: A system and method for including independent instructions into a test case for intentionally provoking interrupts that may be used in conjunction with an instruction shuffling process is presented. A test case generator builds a test case that includes intentional interrupt instructions, which are constructed to intentionally provoke an interrupt, such as an instruction storage interrupt (ISI), a data storage interrupt (DSI), and alignment interrupt, and/or a program interrupt (PI). When a processor executes the test case and invokes an interrupt to an interrupt handler, the interrupt handler does not resolve the interrupt, but rather increments an instruction address register or a link register and resumes test case execution at an instruction subsequent to the instruction that caused the interrupt.

Abstract: A system and method for generating a test case and a bit mask that allows a test case executor the ability to re-execute the test case multiple times using different machine state register bit sets. A test case generator creates a bit mask based upon identified invariant bits and semi-invariant bits. The test case generator includes compensation values corresponding to the semi-invariant bits into a test case, and provides the test case, along with the bit mask, to a test case executor. In turn, the test case executor dispatches the test case multiple times, each time with a different machine state register bit set, to a processor. Each of the machine state register bit sets places the processor in different modes.

Abstract: To provide a semiconductor test apparatus which is capable of adjusting skew efficiently with sufficient operational convenience. The semiconductor test apparatus tests a semiconductor device based on a signal obtained by applying a test signal to the semiconductor device, and includes a driver pin block. The driver pin block is provided with: a plurality of drivers which generate the test signal; at least one adjustment comparator which is connected to output terminals of the drivers and which is used for adjusting timings of the drivers; and a reference signal input terminal to which a reference signal for adjusting a timing of the adjustment comparator is input.

Abstract: This semiconductor storage device comprises a test mode based on test data input from the outside. A test data register temporarily retains the test data, while a test code register temporarily retains a test code corresponding to the test data. A test-code-match detection circuit detects a match between a test code retained in the test code register and a desired test code to output a match signal. When the match signal is output, a control circuit outputs the test data retained in the test data register to the first one of a plurality of shift registers in a test data latch circuit. Further, the control circuit inputs the test data returned from the last one of the plurality of shift registers in the test data latch circuit.

Abstract: Apparatus for testing a random number generator includes a random number generating unit that generates and outputs random numbers, and a switching unit that receives the random numbers from the random number generating unit and selectively transmits the random numbers in response to a switching control signal. A test unit performs a basic test on the random numbers to determine whether the transmitted random numbers are within a statistical range, controls the generation of random numbers according to a result of the basic test, and outputs the switching control signal based on whether a test suite is finished.

Abstract: A system and method processor testing using test pattern re-execution is presented. A processor re-executes test patterns using different timing scenarios in order to reduce test pattern build time and increase system test coverage. The invention described herein varies initial states of a processor's memory (cache, TLB, SLB, etc.) that, in turn, varies the timing scenarios when re-executing test patterns. By re-executing the test patterns instead of rebuilding new test patterns, verification quality is improved since more time is available for execution, verification and validation. In addition, since the test patterns result in the same final state, the invention described herein also simplifies error checking.

Abstract: An integrated circuit (IC) arrangement (10) comprises an integrated circuit (100) having a digital circuit portion (120) with a plurality of digital outputs (122), each of the outputs being arranged to provide a test result in a test mode of the integrated circuit (100). The arrangement (10) further comprises space compaction logic (140) comprising a space compaction network (160) having a plurality of compaction domains (162), each domain being arranged to compact a plurality of test results into a further test result, and a spreading network (150) coupled between the plurality of digital outputs (122, 210) and the space compaction network (160), the spreading network being arranged to duplicate each test result from the digital outputs (122,210) to a number of compaction domains (162).

Abstract: In order to further develop a circuit arrangement (100), in particular an active shield, as well as a method for identifying at least one attack on the circuit arrangement (100), wherein test data are generated, the test data are transmitted via at least one group of data lines (50) being designed for carrying data signals in the form of regular data and/or in the form of the test data, the transmitted test data are received, the received test data are compared with expected test data, and any discrepancy between the received test data and the expected test data is ascertained or determined, in such way that less power is required for examining, in particular for identifying, if the circuit arrangement (100) has been attacked, it is proposed that part of the group of data lines (50) is selected to carry new or most recent test data having been generated.

Abstract: A method is provided that uses non-linear data compression in order to generate a set of test vectors for use in scan testing an integrated circuit. The method includes the steps of initially designing the set of test vectors, and selecting one of multiple available coding schemes for each test vector. The method further comprises operating a random pattern generator to generate data blocks, each corresponding to one of the test vectors, wherein the data block corresponding to a given test vector is encoded with a bit pattern representing the coding scheme of the given test vector. The corresponding data block also has a bit length that is less than the bit length of the given test vector. Each data block is routed to at least one of a plurality of decoders, wherein each decoder is adapted to recognize the coding scheme represented by one of the bit patterns.

Abstract: For a control apparatus to be boundary scan testable even when running, including processor cores in an operator to be capable of self-repairing a troubling part, an operator (2) has processor cores (2a, 2b) connected to a boundary scan bus (12), and adapted to mutually diagnose opponent processor cores for troubles, by boundary scan testing each other in a time-dividing manner.

Abstract: The present invention provide a debug circuit which has a structure in which a conversion block latches plural internal signals which are supposed to be effective in finding a cause of a malfunction and are outputted from a selection block, using a signal that is outputted from a timing generation block, converts these signals into serial data, and outputs the serial data to an output block, thereby observing plural signals in the LSI using fewer external pins, and performing analysis of the malfunction of the LSI speedy and reliably.

Abstract: A signal generator generates a WiMedia ultra wideband test signal with a user interface for setting test sequences and parameters of the test signal. Parameters are set for Presentation Protocol Data Units associated with Packet Groups of the test signal. A signal processing unit compiles the Groups containing the Presentation Protocol Data units to generate digital data representative of the test signal. A waveform generator receives the digital data and generating a test signal output having Packet Groups containing Presentation Protocol Data Units. A method is describes for setting test sequences and parameters of an ultra wideband test signal test signal with a user interface of the signal generator.

Abstract: Systems and methods for reducing network performance degradation by assigning caching priorities to one or more states of a state machine are disclosed herein. In one embodiment, the method comprises storing, in a memory, a state machine corresponding to one or more patterns to be detected in a data stream, wherein the state machine comprises a plurality of states, generating a test data stream based on the one or more patterns, traversing the state machine with the test data stream, determining a respective hit quantities associated with each of the plurality of states, the hit quantities each indicating a number of accesses to a corresponding state by the traversing, and associating a caching priority to at least some of the plurality of states based on the hit quantities of the respective states.

Abstract: A test apparatus for testing a memory under test is provided, including a pattern generator generating a read address from which data is read from the memory under test and an expected value of the data read from the read address, a logical comparator comparing the read data read from the read address of the memory under test to the expected value and outputting fail data indicating pass/fail of every bit of the read data, a first fail memory storing a grouping of the read address and the fail data in a case where the read data and the expected value are not the same, a second fail memory storing fail data concerning addresses corresponding to each address of the memory under test, and an updating section updating fail data stored in the second fail memory and corresponding to the read address based on the grouping of the address and the fail data read from the first fail memory.

Abstract: A method and apparatus for providing help upon a user's wrong button manipulation, the method including: obtaining information on a user's button manipulation; checking whether an error pattern is detected in the button manipulation, using the information on button manipulation; and if the error pattern is detected, providing help information corresponding to the detected error pattern. According to the present invention, information on a user's button manipulation in a device is obtained, an error or malfunction pattern due to the user's wrong button manipulation is detected, and help information is provided in order to allow the user to return to the right process or prevent the error next time.

Abstract: An apparatus for LSI test has a risk place extraction unit supplied with a design information of the LSI to specify a place by estimating an error in LSI operation based on the design information of the LSI to write the place on a risk place list, and a pattern generator unit coupled to the risk extraction unit to generate a test pattern responsive to the risk place list, wherein the pattern generator unit generates the test pattern with an operation of the LSI being controlled to be lower than a predetermined threshold to prevent the error in LSI operation from occurring.

Abstract: In a linear feedback shift register (LFSR), a four-bit shift register mainly using F/Fs is formed and an XOR circuit that feeds back an exclusive OR of a first bit and a last bit to the first bit is also provided, thereby outputting a test pattern having a maximum cycle of 15. A phase change circuit that can perform arbitrary phase change of a test pattern based on input of a control signal having a maximum clock number 4 and an average clock number log24 is also formed in the LFSR. As a result, a smaller clock count is required for the LFSR to output a test pattern that matches a test pattern automatically generated by an ATPG.

Abstract: A method, apparatus and computer program product are provided for implementing deterministic based broken scan chain diagnostics. A deterministic test pattern is generated and is loaded into each scan chain in the device under test using lateral insertion via system data ports applying system clocks. Then each scan chain is unloaded and a last switching latch is identified. The testing steps are repeated a selected number of times. Then checking for consistent results is performed. When consistent results are identified, then the identified last switching latch is sent to a Physical Failure Analysis system.

Abstract: Provided are a semiconductor integrated circuit (IC) including a pad for a wafer test and a method of testing a wafer including a semiconductor IC. The semiconductor IC includes a first address generator, a second address generator, and an address output unit. The first address generator generates a normal address having (M+N) bits or a first test address having M bits corresponding to voltages applied to a plurality of address pads. The second address generator generates a second test address having N bits corresponding to a voltage applied to an additional pad. Therefore, according to the semiconductor IC and the wafer test method, an additional pad is provided to generate an N-bit test address in wafer test mode such that the number of pads needed to test a device can be reduced. As a result, more semiconductor ICs can be tested simultaneously.

Abstract: A test pattern generation circuit has multiple pseudo random number generation circuits and a clock control circuit. The pseudo random number generation circuits are provided corresponding to the respective signal lines in a bus wiring, and have predetermined first initial values, which take the same value. In response to first clock signals, the pseudo random number generation circuits generate pseudo random numbers including the first initial values as starting values. According to the value of a control signal, the clock control circuit determines the output-start timings of the first clock signals to be respectively provided to the multiple pseudo random number generation circuits.

Abstract: A method and apparatus is provided for detecting random access memory (RAM) failure for data with a plurality of addresses. The method comprises generating a plurality of RAM test patterns in a predetermined order, implementing a RAM test pattern on each data address in an initial testing pass, based on the predetermined order of the RAM test patterns, rotating the RAM test patterns sequentially to prepare for a new testing pass, and implementing the RAM test patterns on different data addresses in the new testing pass. The apparatus comprises means for generating a plurality of RAM test patterns in a predetermined order, means for implementing a RAM test pattern on each data address in an initial testing pass, based on the predetermined order of the RAM test patterns, means for rotating the RAM test patterns sequentially to prepare for a new testing pass, and means for implementing the RAM test patterns on different data addresses in the new testing pass.

Abstract: A method for Built-In Speed Grading (BISG) comprises a Circuit Under Test (CUT) with Built-In Self-Test (BIST) circuitry, an All-Digital Phase-Locked Loop (ADPLL), and a BISG, to automatically decide the maximum operating frequency of the CUT. The search process for this maximum operating frequency is conducted by a binary search in which the next frequency to test CUT is determined automatically by the BISG controller based on whether the CUT passes or fails the BIST session at current frequency. The maximum operating frequency the CUT can operate is narrowed down to a fine-tuning range out of a number of clock frequencies that the ADPLL can offer. The frequencies an ADPLL can offer is divided into a plurality of coarse ranges, with each of them further having a plurality of fine-tuning frequencies.

Abstract: In a semiconductor integrated circuit 11, there is constructed a test expected value programming circuit 100 having an input/input-output pad 103 for retrieving a ground/power-source signal 104 from a ground terminal 30 or a power source terminal 31 connected to the semiconductor integrated circuit 11, a switch 105 for selectively switching the outputting of the ground/power-source signal 104 inputted via the input/input-output pad 103, and an expected value generation circuit 13 for generating a test expected value signal 21 based on a switch output signal 122 outputted from the switch 105.

Abstract: Methods, system, and computer programs for compensating for introducing data dependent jitter into a test signal using a testing instrument are disclosed. The method includes generating a test pattern that comprises a plurality of intervals. Each of the intervals includes a number of redundant samples that correspond to a sample in a test source pattern. The test pattern is digitally modified to generate a modified test pattern that includes data dependent jitter.

Abstract: A technique for estimating and improving the test coverage for large machines, while accumulating minimum information of past test cases (i.e., minimum feedback) is provided. The technique is scalable in the sense that the number of machine instructions needed to measure the test coverage can range from a few instructions to all the instructions. The technique is easily integrated into existing test generation systems and is applicable to both uni- and multi-processing systems.

Abstract: This test generator takes data flow block diagrams and uses requirements-based templates, selective signal propagation, and range comparison and intersection to generate test cases containing test vectors for those diagrams. The templates are based on the functionality and characteristics of a block type, and each block type has associated templates. These templates provide maps for the creation of test values that verify the functionality of particular instances of that block type. Signal propagation allows the generation of diagram-level test cases that verify particular characteristics of a single embedded block. The methods disclosed for signal propagation utilize range intersection, equivalence classes, and block type formulae to create efficient and complete test cases. This test generation method would preferably be repeated until all blocks in a data flow block diagram were verified in their respective contexts, and it creates test cases that cover multiple time steps.

Abstract: A method is for refreshing a dynamic random access memory coupled to an error correction system, which uses an error correcting code. The dynamic random access memory includes groups of memory cells storing bits, each group of memory cells being subdivided into packets of memory cells. Each packet of memory cells is supplemented with the error correcting code. The method includes performing a retention test on each group of memory cells, and increasing a memory refresh frequency if a number of test groups of memory cells having at least one erroneous packet is greater than a threshold.

Abstract: The invention relates to a method for verifying one or more exceptions in a logic circuit comprising the steps of: a first step of providing an initial representation of a logic circuit; a second step of indicating at least one exception for the logic circuit; a third step of introducing one or more potential malfunctions of the logic circuit related to the one or more exceptions into the representation of the logic circuit to produce a modified representation of the logic circuit; a fourth step of determining whether functional behaviour of the modified representation of the logic circuit differs from functional behaviour of the first representation of the logic circuit; and a fifth step of reporting a result relating to the difference in the functional behaviour of the modified representation of the logic circuit from the functional behaviour of the initial representation of the logic circuit.

Abstract: The present disclosure describes a novel method and apparatus for using a device's power and ground terminals as a test and/or debug interface for the device. According to the present disclosure, messages are modulated over DC voltages applied to the power terminals of a device to input test/debug messages to the device and output test/debug messages from the device. The present disclosure advantageously allows a device to be tested and/or debugged without the device having any shared or dedicated test or debug interface terminals.

Abstract: Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns for testing integrated circuits. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) environment). Certain embodiments of the disclosed technology can reduce the switching rates, and thus the power dissipation, in scan chains with no hardware modification. Other embodiments use specialized decompression hardware and compression techniques to achieve low power testing.

Abstract: There is provided a test apparatus for testing a semiconductor device. The test apparatus includes a pattern generating section that sequentially reads and outputs waveform information to be used for testing the semiconductor device, where the waveform information is made up by a plurality, of pieces of data, a waveform generating section that generates a waveform based on the waveform information which is sequentially output from the pattern generating section, a match detecting section that detects, in response to a signal indicating a match detection request cycle output from the pattern generating section, whether an output signal output from the semiconductor device matches an expected value pattern, and an interrupt section that, when the match detecting section detects that the output signal matches the expected value pattern, terminates the match detection request cycle and causes the pattern generating section to output next waveform information.

Abstract: Technologies disclosed herein can be used to diagnose defects on die having both scan chain and system logic defects, including in situations where the presence of one or more faults in the system logic potentially obscures the detectability of one or more faults in the scan chains (or channels) and vice versa. At least some embodiments employ an iterative approach where at least some scan chain faults are identified, these chain faults are used to identify system logic faults, and then additional chain faults are identified using the system logic faults and vice versa. Failing bits can be partitioned into at least two groups: failing bits determined as being caused by system logic failures, and failing bits determined as being possibly caused by chain defects, system logic defects, or the compound effects of both types of defects.