By Checking The Correct Order Of Processing (epo) Patents (Class 714/E11.178)
  • Publication number: 20090313505
    Abstract: Methods and system are provided for detecting combinations of performance indicators that are associated with a root cause. The method comprises storing a plurality of error codes, each representative of at least one performance indicator, storing descriptive data associated with each of the plurality of error codes, storing a plurality of root causes, each associated with descriptive data that corresponds to the descriptive data of the plurality of error codes, identifying the error codes from the plurality of error codes that correspond to at least one of the plurality of root causes, and analyzing the error codes that correspond to at least one root cause to determine combinations of performance indicators that are associated with the root cause.
    Type: Application
    Filed: June 12, 2008
    Publication date: December 17, 2009
    Applicant: Honeywell International Inc.
    Inventors: Robert C. McCroskey, Kyusung Kim
  • Publication number: 20090307528
    Abstract: The present invention extends to methods, systems, and computer program products for simulating operations through out-of-process execution. When a diagnostic operation is to be performed for a target execution context, a separate execution context is created based on the same executable code used to create the target execution context. An execution boundary separates the target execution context and the separate execution context such that execution in the separate execution context does not influence the behavior of the target execution context. State data from the target execution context is marshaled and transferred to the separate execution context. The separate execution context reconstitutes the state data and uses the state data to perform the diagnostic operation. Accordingly, performance of the diagnostic operation is simulated in the separate execution context without influencing the behavior of the target execution context.
    Type: Application
    Filed: June 6, 2008
    Publication date: December 10, 2009
    Applicant: Microsoft Corporation
    Inventors: Richard M. Byers, Jonathon Michael Stall, Gregg B. Miskelly
  • Publication number: 20090307522
    Abstract: A network failover apparatus and method for use in a client-server system. The method includes establishing at least a first and further path between a client and a server. The first path connects the server to the client through a first network and a first interface of the client and the further path connects the server to the client through a further network that is separate from the first network and a further interface of the client. The method also includes reaching the server through the first interface, detecting that the server is no longer reachable through the first interface, and identifying the first interface as failed. The method also includes reaching the server through the further interface after the first interface is identified as failed, testing the first interface to determine whether the server is reachable while the server is reachable through the further interface, and reestablishing a connection to the server through the first interface.
    Type: Application
    Filed: May 7, 2009
    Publication date: December 10, 2009
    Applicant: PADCOM HOLDINGS INC.
    Inventors: Erik OLSON, David THOMPSON
  • Publication number: 20090300422
    Abstract: A method for analyzing operations of a plurality of machines communicating with a server computer. The method may include establishing a plurality of virtual sensors corresponding to a plurality of engine systems of the respective plurality of machines. Each virtual sensor may be indicative of interrelationships between a plurality of input parameters and a plurality of output parameters of an engine system. The method may also include determining an operational accuracy of each virtual sensor, and calculating a score of each machine based on the operational accuracy of a virtual sensor of the machine. Further, the method may include ranking the plurality of machines based upon the score of each machine, scheduling maintenance for a certain number of machines based on the ranking of the plurality of machines, and providing automatic notification of the scheduled maintenance.
    Type: Application
    Filed: May 30, 2008
    Publication date: December 3, 2009
    Inventors: Anthony J. Grichnik, Michael Seskin, Wade S. Willden
  • Publication number: 20090300417
    Abstract: A method for advanced condition monitoring of an asset system includes using a plurality of auto-associative neural networks to determine estimates of actual values sensed by at least one sensor in at least one of the plurality of operating regimes; determining a residual between the estimated sensed values and the actual values sensed by the at least one sensor from each of the plurality of auto-associative neural networks; and combining the residuals by using a fuzzy supervisory model blender; performing a fault diagnostic on the combined residuals; and determining a change of the operation of the asset system by analysis of the combined residuals. An alert is provided if necessary. A smart sensor system includes an on-board processing unit for performing the method of the invention.
    Type: Application
    Filed: May 29, 2008
    Publication date: December 3, 2009
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: Piero Patrone Bonissone, John Erik Hershey, Robert James Mitchell, JR., Rajesh Venkat Subbu, JR., Avinash Vinayak Taware, Xiao Hu
  • Publication number: 20090292951
    Abstract: The invention relates to a method and a device for locating a fault in a system. The system includes a set of elements. The elements are connected in a network. Each element is associated with an operational status and a probability of failure. The method according to an embodiment of the invention includes, for each of the elements having a status indicating a malfunction, denoted as a defective element, the creation, from the system topology, of an expression comprising terms corresponding to functional elements connected to said defective element. If several expressions have been created in the preceding step, then merge expressions having at least one term in common. For each expression, delete terms in the expression corresponding to elements having a “healthy” status. Calculate a minimal expression from the preceding expression. Calculate failure probabilities for selected members of the minimal expression based on failure probabilities of the corresponding elements.
    Type: Application
    Filed: May 13, 2009
    Publication date: November 26, 2009
    Applicant: Thales
    Inventors: Francois Fournier, Christian Sannino, Carine Bailly
  • Publication number: 20090276664
    Abstract: A test set for evaluating network performance is described, and which may include an output device, a processor, a power supply, a memory unit, and a control terminal. The test set may be configured to receive a user-entered selection of one of a plurality of different bit-error rate profiles and generate a test signal exhibiting the selected bit-error rate profile. The test set may also supply the test signal exhibiting the selected bit-error rate profile to a network under test. In addition, the test set may receive as an input, an output from the network under test. The output may include the test signal exhibiting the selected bit-error rate. The test set may evaluate the received test signal and determine the performance of the network in response to the received test signal exhibiting the bit-error rate. The test set may then output the results of the evaluation.
    Type: Application
    Filed: June 18, 2009
    Publication date: November 5, 2009
    Applicants: Verizon Services Organization Inc., Verizon Services Corp.
    Inventors: James E. Sylvester, Alexander Laparidis, Stanley Y. Lee, Muzaffer Kanaan
  • Publication number: 20090265582
    Abstract: A data processing system is provided. The data processing system comprises at least one processor (P) for processing data according to a set of instructions. The processors are coupled by a bus means (BM). Furthermore, a debugging means (DM) is provided to detect the occurrence of events and the corresponding point of time of the occurrence on the bus means (BM). If predefined events occur at, within and/or after/before predefined points in time, the debugging mode is switched on.
    Type: Application
    Filed: January 23, 2006
    Publication date: October 22, 2009
    Applicant: NXP B.V.
    Inventors: Narendranath Udupa, Nagaraju Bussa
  • Publication number: 20090265581
    Abstract: A data processing system includes an execution unit operating in a clocked manner, a clock pulse generator for delivering a clock signal for the execution unit, and a monitoring unit for monitoring the regular operation of the execution unit. The clock pulse generator is configured for delivering the clock signal having a controllable frequency. The monitoring unit is functionally connected to the clock pulse generator in order to reduce the frequency of the clock signal when irregular operation of the execution unit is detected.
    Type: Application
    Filed: October 25, 2005
    Publication date: October 22, 2009
    Inventors: Yorck von Collani, Thomas Kottke
  • Publication number: 20090259713
    Abstract: A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node may be used individually or simultaneously to work on any combination of computation or communication as required by the particular algorithm being solved or executed at any point in time. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency.
    Type: Application
    Filed: June 26, 2009
    Publication date: October 15, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthias A. Blumrich, Dong Chen, George L. Chiu, Thomas M. Cipolla, Paul W. Coteus, Alan G. Gara, Mark E. Giampapa, Philip Heidelberger, Gerard V. Kopcsay, Lawrence S. Mok, Todd E. Takken
  • Publication number: 20090254777
    Abstract: The invention relates to an integrated circuit comprising at least one microprocessor [12] linked to at least one non-volatile memory [14] that can be accessed by sectors. The integrated circuit comprises a detector [20] for discovering when a threshold number of bad sectors has been exceeded in said non-volatile memory [14].
    Type: Application
    Filed: December 12, 2006
    Publication date: October 8, 2009
    Applicant: GEMPLUS
    Inventors: Nathalie Feyt, Christophe Arnoux
  • Publication number: 20090240986
    Abstract: Embodiments of the invention enable error simulation for system validation. Errors can be simulated by modifying data presented to the processor as well as generating interrupts consistent with the modified data in the ASIC hardware. Modify logic may be added to the ASIC so when the microprocessor attempts to read a specific address, the modify logic may mask one or more of the data bits returned by the requested address. Address, bit mask, and force value data may be stored in registers to determine which address may be modified, the bit location to be modified, and the value that bit location should be changed to. Selection logic may then determine whether data from the modify logic or the unmodified value from an attached device should be sent to the ASIC interface and on to the microprocessor. A timer may also be used to decouple the setup from the test.
    Type: Application
    Filed: March 24, 2008
    Publication date: September 24, 2009
    Applicant: Emulex Design & Manufacturing Corporation
    Inventors: Bruce Gregory Warren, Carl Joseph Mies, William Eugene Morgan, William Patrick Goodwin
  • Publication number: 20090228741
    Abstract: A method to detect potential problems within a heterogeneous and diverse application environment. Operations data is received from a plurality of application servers within the application environment. The operations data pertains to operations performed at the plurality of application servers over a predetermined time interval. The operations data is aggregated. The aggregated data is compared to reference data, and a potential problem within the application environment is detected if the aggregated data deviates from the reference data in a predetermined manner.
    Type: Application
    Filed: March 30, 2009
    Publication date: September 10, 2009
    Inventors: James Lloyd, Faye Dai Hall, Michael Eynon, Abhunav Kumar
  • Publication number: 20090222699
    Abstract: A method for displaying the quality of a digital communications link for field devices of automation technology on a field device serving as a monitoring unit. According to the method telegrams are transmitted via the communications link and are tapped in the monitoring unit and tested according to at least two criteria. The result of the testing is displayed as a bar chart on the monitoring unit, so that the user can observe quality of the communications link simply and easily.
    Type: Application
    Filed: April 13, 2007
    Publication date: September 3, 2009
    Applicant: Endress + Hauser GmbH + Co. KG
    Inventors: Chris Abbott, Frank Van Bekkum
  • Publication number: 20090222703
    Abstract: According to one embodiment, an information processing apparatus includes an information processing apparatus main body, and a nonvolatile semiconductor memory drive. The semiconductor memory drive includes a control module configured to control execution of data read and write on a nonvolatile semiconductor memory in units of a predetermined number of sectors. In a case where a data size of write data from the information processing apparatus main body is less than a data size of the predetermined number of sectors, the control module reads, from the nonvolatile semiconductor memory, data in a predetermined number of sectors including a sector in which the write data is to be written, and in a case where an error is detected in the read data, the control module stores, in a management table, defective sector information which is indicative of a sector storing the data in which the error is detected.
    Type: Application
    Filed: February 20, 2009
    Publication date: September 3, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Takehiko Kurashige
  • Publication number: 20090217098
    Abstract: Management of storage used by pageable guests of a computing environment is facilitated. An enhanced suppression-on-protection facility is provided that enables the determination of which level of protection (host or guest) caused a fault condition, in response to an attempted storage access.
    Type: Application
    Filed: March 20, 2008
    Publication date: August 27, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark S. Farrell, Charles W. Gainey, JR., Dan F. Greiner, Lisa Cranton Heller, Damian L. Osisek
  • Publication number: 20090217097
    Abstract: A web server includes software to support a remotely accessible web portal for installation and repair services in conjunction with a telecommunication service provided to a customer by a provider. The software includes instructions to provide a first I&R user interface, including a plurality of selectable I&R objects in response to a first input from a remote field device, receive a second input from the remote field device indicating a user's selection of one of the I&R objects, generate a request to invoke an I&R application in response to receiving the input, transmit the request to invoke the I&R application to an I&R system, receive I&R data generated by the I&R application from the I&R system, and convey information indicative of the I&R data to the remote field device.
    Type: Application
    Filed: February 25, 2008
    Publication date: August 27, 2009
    Applicant: AT&T KNOWLEDGE VENTURES, L.P.
    Inventors: Erian Laperi, Michael L. Cromer, Jeremy A. Dilks, Joel Palmer, Bennett C. Seyer
  • Publication number: 20090210748
    Abstract: Methods and systems to simulated a plurality of airline information systems (AISs) to test an AIS under test (AISUT), including to send and receive messages between the simulated AISs, and to send messages to and receive messages from the AISUT, in accordance with communication parameters associated with the corresponding AISs and AISUT. The AISUT and/or the simulated AISs may be stimulated to cause interaction with the AISUT, and resultant messages and information may be recorded. Stimulation may include controlling a web browser to interact with a web application of the AISUT. AISs may be represented as travel system objects, which may be associated with corresponding AIS-specific message handling and reporting parameters. Message processing logic may be configured to process messages, such as booking request messages, directed to a plurality of the simulated AISs, and the travel systems and the message processing logic may be modifiable independent of one another.
    Type: Application
    Filed: February 18, 2009
    Publication date: August 20, 2009
    Applicant: ITA Software, Inc.
    Inventors: Andreas Hohmann, James Carter
  • Publication number: 20090193297
    Abstract: A data processing system 1 has a processor core 2 which is programmable to act as one of a plurality of virtual machines each identified by a virtual machine identifier, each virtual machine acting in one of a plurality of contexts each identified by a context identifier, each context executing a sequence of program instructions, each program instruction having one or more associated memory addresses. The data processing system has diagnostic circuitry 10 for performing diagnostic operations on the processor core. Diagnostic control circuitry 12 is provided which is responsive to current values of the virtual machine identifier, the context identifier and at least one of the one or more associated memory addresses to trigger the diagnostic circuitry 10 to perform diagnostic operations.
    Type: Application
    Filed: December 30, 2008
    Publication date: July 30, 2009
    Applicant: ARM LIMITED
    Inventors: Michael John Williams, Richard Roy Grisenthwaite, Andrew Brookfield Swaine, John Michael Horley
  • Publication number: 20090193294
    Abstract: A system and method for verifying operation of a target system to be inspected. The system includes an abstract binary tree generation unit and a matching unit. The abstract binary tree generation unit obtains information about a functional specification of the target system and generates one or more binary trees that associate one or more states that can occur in the target system with respective nodes and that associate state transitions of objects constituting the target system and interactions between the objects with connection relationships between the nodes. The matching unit receives an event sequence in an application model of the target system obtained in response to the operation of the target system and matches the event sequence against the binary trees generated by the abstract binary tree generation unit. The method includes steps for accomplishing the functionality of the system.
    Type: Application
    Filed: January 26, 2009
    Publication date: July 30, 2009
    Inventors: Hiroaki Nakamura, Kohichi Ono
  • Publication number: 20090177927
    Abstract: A method and system for determining an impact of a failure of a component for one or more services that the component is supporting. A data feed received from a processing node includes data indicative of an identity and system status of a component running on the processing node. The system status of the component identifies whether the component has failed or is active. The one or more services is mapped into a calendar function. After determining that the component supports the one or more services, a lookup in the calendar function is performed to identify a temporal activity and a level of criticality of each service of the one or more services. An impact of the system status of the component on the one or more services is determined from analysis of the identified temporal activity and the identified level of criticality of the one or more services.
    Type: Application
    Filed: March 12, 2009
    Publication date: July 9, 2009
    Inventors: Daniel Bailey, Charlotte Newton, Gary Paul Noble, Maurice James Perks, Andrew Tinsley, Melissa Jane Bailey
  • Publication number: 20090158094
    Abstract: A method and system of an embodiment may include designing two or more test cases for a network, creating one or more test records comprising data and configuration data for the two or more test cases, provisioning a user record on the network, running a first test case using the user record provisioned on the network, the first test case comprising, transmitting at least a first portion of the data to a network element being tested, and receiving a response from the network element based at least in part on the configuration data for the first test case contained in the data transmitted, running a second test case using the user record provisioned on the network, the second test case comprising, transmitting at least a second portion of the data to a network element being tested, and receiving a response from a network element based at least in part on configuration data for the second test case contained in the data transmitted.
    Type: Application
    Filed: December 13, 2007
    Publication date: June 18, 2009
    Applicant: VERIZON SERVICES CORPORATION
    Inventor: Jeffrey R. EVANS
  • Publication number: 20090144585
    Abstract: A debugging method of the BIOS is disclosed. Firstly a debugging routine is written into a boot program. Then the BIOS executes the boot program. The BIOS judges whether a status value is equal to a default value of the debugging routine or not. When the status value is equal to the default value, the BIOS outputs a test value according to the debugging routine. When the status value is not equal to the default value, the debugging routine is quit, and the BIOS continues to execute the boot program.
    Type: Application
    Filed: December 4, 2007
    Publication date: June 4, 2009
    Inventor: Ting-Chun Lu
  • Publication number: 20090132859
    Abstract: A service management system and a method of performing service diagnostics. In one embodiment, the service management system includes: (1) a service description repository configured to contain service descriptions that define services in terms of end points that assume roles based on at least one of the capabilities and attributes thereof, (2) a diagnostic rule definition repository configured to contain diagnostic rules pertaining to problem areas regarding the services and (3) a diagnostic engine coupled to the service description repository and the diagnostic rule definition repository and configured to retrieve at least one diagnostic rule based on a subscriber, a service and a problem area, evaluate at least one diagnostic rule to produce at least one solution, retrieve data regarding end points associated with the service and return a possible solution.
    Type: Application
    Filed: November 21, 2008
    Publication date: May 21, 2009
    Applicant: Motive, Incorporated
    Inventors: Edward S. Pelley, Bryan P. Tacker
  • Publication number: 20090132853
    Abstract: Embodiments include a computing system, a device, and a method. A computing system includes a processor subsystem having an adjustable operating parameter. The computing system also includes an information store operable to save a sequence of instructions. The computing system further includes a controller module. The controller module includes a monitor circuit for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem. The controller further includes a control circuit for adjusting the adjustable operating parameter based upon an error-tolerant performance criterion.
    Type: Application
    Filed: January 8, 2009
    Publication date: May 21, 2009
    Inventors: Bran Ferren, W. Daniel Hillis, William Henry Mangione-Smith, Nathan P. Myhrvold, Clarence T. Tegreene, Lowell L. Wood, JR.
  • Publication number: 20090132871
    Abstract: A system and method for detecting errors in a document transfer scheme. A user submits an electronic document transfer scheme to the document processing device including document handling instructions. The electronic document transfer scheme is then received by the document processing device and parsed, via the controller, to extract data representative of the destination designated by the scheme. Preferably, the destination data contained in the scheme provides the document processing device with a location to which a copy of an electronic document is to be sent. The source/destination information is then input as an arc on a graph, so as to generate a representation of the workflow associated with the document transfer scheme. A determination is then made, from the graph, whether the submitted electronic document transfer scheme represents at least one cycle on the graph.
    Type: Application
    Filed: December 30, 2008
    Publication date: May 21, 2009
    Inventor: Andrey Savov
  • Publication number: 20090113240
    Abstract: In one embodiment, the present invention includes a method for determining a vulnerability level for an instruction executed in a processor, and re-executing the instruction if the vulnerability level is above a threshold. The vulnerability level may correspond to a soft error likelihood for the instruction while the instruction is in the processor. Other embodiments are described and claimed.
    Type: Application
    Filed: March 31, 2006
    Publication date: April 30, 2009
    Inventors: Xavier Vera, Oguz Ergin, Osman Unsal, Jaume Abella, Antonio Gonzalez
  • Publication number: 20090106591
    Abstract: A memory hub includes an on-board diagnostic engine through which diagnostic testing and evaluation of the memory system can be performed. The memory hub includes a link interface for receiving memory requests for access to memory devices of the memory system and a memory device interface coupled to the memory devices for coupling memory requests to the memory devices. A memory hub diagnostic engine is coupled through a switch to the link interface and the memory device interface to perform diagnostic testing of the memory system. The diagnostic engine includes a maintenance port that provides access to results of the diagnostic testing and through which diagnostic testing commands can be received.
    Type: Application
    Filed: December 30, 2008
    Publication date: April 23, 2009
    Applicant: Micron Technology, Inc.
    Inventor: Joseph M. Jeddeloh
  • Publication number: 20090100294
    Abstract: A system and method for path saturation in a storage area network so that the throughput of the storage area network may be determined. The system and method includes a software utility suite that uses either a system administration scripting language, e.g., Perl or Korn shell, or by compiled or machine language software. The software utility suite includes a set of software tools to be installed on one or more computer systems sharing access to a data storage system, such as a storage area network (SAN). The software tools running on these separate computer systems communicate and collaborate in a peer-to-peer fashion in order to coordinate loading, testing and measurement of storage throughput on the shared data storage system. The software tools further coordinate the collection, storage and presentation of results data obtained through such loading, testing and measurement of the storage throughput of the shared data storage system.
    Type: Application
    Filed: December 17, 2008
    Publication date: April 16, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Craig William Fellenstein, Carl Phillip Gusler, Rick Allen Hamilton, II, James Wesley Seaman
  • Publication number: 20090083578
    Abstract: There is disclosed a method and system of testing server side objects in a client-server environment. A proxy is created of a first object on a server side on a client side. The proxy invokes a method of the first object on the server side to conduct a test by a test case deployed on the client side. A proxy is created of a second object on the client side by the proxy of the first object by the process of invoking the method of the first object on the server side. The creation of the proxies and objects are performed recursively.
    Type: Application
    Filed: September 24, 2008
    Publication date: March 26, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jun Jie Nan, Meng Wang, Zi Yao Wang, Hui Li Zheng
  • Publication number: 20090070635
    Abstract: The present invention relates to a method of improving the integrity and safety of a system, this method making it possible, on the one hand, to detect and to locate an anomaly of a system, and on the other hand to estimate the impact of such an anomaly on the degradation of performance, with a view to attaining the safety level required and to making the data provided by this system safe, and this method is characterized in that it consists, in a system comprising sub-assemblies, in monitoring the proper operation of sub-assemblies by checking their respective transfer functions in the operational mode with the aid of stimuli dispatched to these sub-assemblies.
    Type: Application
    Filed: July 3, 2008
    Publication date: March 12, 2009
    Applicant: THALES
    Inventors: David DEPRAZ, Jacques Coatantiec, Alain Renard
  • Publication number: 20090049340
    Abstract: A system analysis device for analyzing a state of operation of a computer system includes an analysis processing section, an analysis program storage section, a diagnostic processing section and a condition definition information storage section. The analysis processing section analyzes analysis subject data outputted from the analysis subject computer system. The analysis program storage section stores plural analysis programs, which perform analysis processing on the analysis subject data. The diagnostic processing section diagnoses a state of operation of the computer system from analysis results. The condition definition information storage section stores condition definition information, which defines conditions to be determination standards of the diagnostic processing. The analysis programs and the condition definition information are updated respectively separately from one another.
    Type: Application
    Filed: June 6, 2008
    Publication date: February 19, 2009
    Applicant: OKI ELECTRIC INDUSTRY CO., LTD.
    Inventors: Yunichi Yada, Tomoya Hitokoto, Akiyoshi Shimmura, Kazutaka Oki
  • Publication number: 20090044060
    Abstract: The invention relates to a method for supervising a task-based data processing, wherein for a plurality of tasks the following steps are performed for each task: scheduling the task for processing, and logging the scheduling of the task by storing a task identifier in a log memory, said task identifier identifying the scheduled task and being assigned to the scheduled task. The task identifiers stored in the log memory form a task history pattern of scheduled tasks. By means of the task history a pattern may be detected for determining whether a failure appears in the task-based data processing. At least one safety measure is taken when a failure is detected.
    Type: Application
    Filed: October 2, 2008
    Publication date: February 12, 2009
    Inventors: Stefan Noll, Alexander Wassew
  • Publication number: 20080301256
    Abstract: A data processing system includes one or more nodes, each node including a memory sub-system. The sub-system includes a fine-grained, memory, and a less-fine-grained (e.g., page-based) memory. The fine-grained memory optionally serves as a cache and/or as a write buffer for the page-based memory. Software executing on the system uses n node address space which enables access to the page-based memories of all nodes. Each node optionally provides ACID memory properties for at least a portion of the space. In at least a portion of the space, memory elements are mapped to locations in the page-based memory. In various embodiments, some of the elements are compressed, the compressed elements are packed into pages, the pages are written into available locations in the page-based memory, and a map maintains an association between the some of the elements and the locations.
    Type: Application
    Filed: May 30, 2008
    Publication date: December 4, 2008
    Inventors: Thomas M. McWilliams, Earl T. Cohen, James M. Bodwin, Ulrich Bruening
  • Publication number: 20080301503
    Abstract: The present invention provides for a self-correcting state circuit. A first flip flop is configured to receive a clock input and a first data input, and to generate a first output in response to the clock input and the first data input. A second flip flop is coupled to the first flip flop and configured to receive the clock input and to receive the first output as a second data input, and to generate a second output in response to the clock input and the first output. A first correction circuit is coupled to the second flip flop and configured to generate a corrected output. A third flip flop is coupled to the first correction circuit and configured to receive the clock input and to receive the corrected output as a third data input, and to generate a third output in response to the clock input and the third data input.
    Type: Application
    Filed: August 7, 2008
    Publication date: December 4, 2008
    Inventors: David William Boerstler, Eric John Lukes, Hiroki Kihara, James David Strom
  • Publication number: 20080276127
    Abstract: A method of performing diagnostics on a first hierarchical device operable within a building automation system is disclosed. The method includes compiling application code configured to control the first hierarchical device such that the application code includes a plurality of internal variables, providing a diagnostic module configured to monitor the plurality of internal variables, collecting internal variable diagnostic data related to the monitored plurality of internal variables, uploading the collected internal variable diagnostic data to a second hierarchical device, performing, at the second first hierarchical device, a layered diagnostic analysis on the internal variable diagnostic data, and identifying a first hierarchical device problem based on the analyzed internal variable diagnostic data.
    Type: Application
    Filed: May 3, 2008
    Publication date: November 6, 2008
    Inventors: Norman R. McFarland, Geoffrey D. Nass, Pornsak Songkakul
  • Publication number: 20080263402
    Abstract: The invention relates to a method, testing arrangement, simulator and software program for evaluating quality of a transmission channel or a transmission device or a codec. The evaluation is made by using multimedia stream including voice and video frames. The multimedia frames used in the evaluation are generated by using fractal functions both in the transmitting device and the receiving device.
    Type: Application
    Filed: March 4, 2008
    Publication date: October 23, 2008
    Applicant: NETHAWK OYJ
    Inventor: Vinski Braysy
  • Publication number: 20080250272
    Abstract: A logging last resource (LLR) system can provide a transaction log and transaction data to a LLR resource after a number of two-phase-commit resources have been prepared. The LLR resource manager can operate on the transaction log and transaction data in an atomic fashion so that the local commit can be done. The local commit can be done by the LLR manager in an atomic manner.
    Type: Application
    Filed: April 24, 2008
    Publication date: October 9, 2008
    Applicant: BEA SYSTEMS, INC.
    Inventors: Thomas E. Barnes, Adam Messinger
  • Publication number: 20080244316
    Abstract: A plurality of data storage devices are arranged to form a multi-device array space, and a controller controls access to the array space. The controller is configured to index sets of operational performance data from the plurality of data storage devices into a unified data log. The controller further detects a failure trend of one or more data storage devices by analyzing at least one of a vertical block of data and a horizontal block of data in the unified data log. The vertical data block of data is associated with one of the data storage devices at a plurality of indices. The horizontal block of data is associated with a plurality of the data storage devices at an index.
    Type: Application
    Filed: October 4, 2007
    Publication date: October 2, 2008
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Robert Sherwood Gittins, Robert Michael Lester
  • Publication number: 20080244319
    Abstract: A system (200) comprises a plurality of data collectors (210), a correlator (220), a context analyser (230), a baseline analyser (250), a database (260), and a graphical user interface (GUI) (270). The data collectors (210) are deployed on the services or applications that they monitor, or on the network between these applications as a network appliance, and are designed to capture messages that are passed between the various services. The data collectors (210) are non-intrusive, i.e. they do not to impact the behavior of the monitored services. The data collectors (210) can capture messages transmitted using communication protocols including, but not limited to, SOAP, XML, HTTP, JMS, MSMQ, and the like.
    Type: Application
    Filed: March 29, 2005
    Publication date: October 2, 2008
    Inventors: Smadar Nehab, Gadi Entin, David Barzilai, Yoav Cohen, Ron Wolf, Yoav Chernabroda, Roni Floman
  • Publication number: 20080244317
    Abstract: A computer program automatically producing a system test specification adapted for real-life use of a computer system, such that the system's most important processing functions can be tested. An update record storage unit stores update records each including: a process identifier of a data updating process, the name of a dataset updated by that process, and an update timestamp. A function test data storage unit stores data of function tests for checking whether each module realizing operation steps of an operation flow satisfies specified requirements. An operation flow extractor creates a flow descriptor enumerating the names of datasets updated by a data updating process in chronological order. From the stored function test data, a system test generator compiles a system test description for each operation flow, which specifies a series of function tests in the same order as the operation steps constituting each operation flow.
    Type: Application
    Filed: February 5, 2008
    Publication date: October 2, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Keisuke Yano, Tsuyoshi Kanai
  • Publication number: 20080244318
    Abstract: Methods for preventing the failure of disk drives in storage systems are disclosed. A system and a computer program product for preventing the failure are also disclosed. Factors relating to the aging or early onset of errors in a disk drive are monitored. These factors are then compared to thresholds. In case the thresholds are exceeded, an indication for the replacement of the disk drive is given. Sudden rises in the factors are also used to indicate the impeding failure of disk drives.
    Type: Application
    Filed: April 8, 2008
    Publication date: October 2, 2008
    Applicant: COPAN SYSTEMS
    Inventor: Aloke Guha
  • Publication number: 20080235531
    Abstract: A method, apparatus, and computer program product are disclosed for testing a data processing system's ability to recover from cache directory errors. A directory entry is stored into a cache directory. The directory entry includes an address tag and directory parity that is associated with that address tag. A cache entry is stored into a cache that is accessed using the cache directory. The cache entry includes information and cache parity that is associated with that information. The directory parity is altered to imply bad parity. The bad parity implies that the address tag that is associated with this parity is invalid. The information included in the cache entry is altered to be incorrect information. However, although the information is now incorrect, the cache parity continues to imply good parity which implies that the data is good. This good parity implies that the information that is associated with the parity is valid, even though it is not.
    Type: Application
    Filed: June 6, 2008
    Publication date: September 25, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: David Stephen Levitan
  • Publication number: 20080229152
    Abstract: An on-chip debug emulator is capable of connecting to the target device and the host device for remotely debugging the program in the target device. The on-chip debug emulator contains a debug communication control unit. This debug communication control unit contains a plurality of serial communication circuits, the plurality of serial communication circuits are commonly provided with a clock signal. The debug communication control unit controls communications with the target device based on commands output from the host device. Each of The plurality of serial communication circuits contains a data buffer and serially transmits data stored in the data buffer to and from the target device while synchronized with the clock signal. Namely, the plurality of serial communication circuits communicate in parallel while operating synchronized with the same clock. The on-chip debug emulator can in this way be made utilizing a low-cost microcomputer not containing any parallel communication circuits.
    Type: Application
    Filed: March 13, 2008
    Publication date: September 18, 2008
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Takahiro Moroda
  • Publication number: 20080209255
    Abstract: The invention describes an end-user-initiated method and system for managing failure in a host computing system. The embodiments of the invention describe an embedded management/diagnostics system that operates independently from the failed computing system and includes the locating and connecting of an appropriate technical service provider for correcting the problem in the failed computing system.
    Type: Application
    Filed: February 28, 2008
    Publication date: August 28, 2008
    Inventors: Jean-Marc L. SEGUIN, Jay M. Litkey, Anthony Richard Phillip White
  • Publication number: 20080209274
    Abstract: A large population of mass-produced devices (80) such as a particular model of computer hard disk drive, are distributed around the world. Each device (80) includes an arrangement for collecting failure analysis data of the device (50). Each device (80) is arranged to transmit this data to the device manufacturers server (10) via the internet (20). The server (10) analyses the data in order to determine trends in failure performance of the population of devices in order to improve future designs and to provide updated software for distribution to the devices (80) via the internet (20).
    Type: Application
    Filed: March 20, 2008
    Publication date: August 28, 2008
    Inventors: Robert Bruce Nicholson, Barry Douglas Whyte
  • Publication number: 20080184074
    Abstract: Provided are a method, system, and article of manufacture wherein at least a first zone is maintained in a fibre channel arbitrated loop system, and wherein a plurality of storage devices is included in the first zone. A determination is made that diagnostic operations have to be performed on a storage device that is included in the plurality of storage devices. A second zone is generated, wherein the second zone includes the storage device on which the diagnostic operations have to be performed, and wherein the storage device is removed from the plurality of storage devices in the first zone leaving a remaining set of storage devices in the first zone. Diagnostic operations are performed on the storage device in the second zone while other operations are performed on the remaining set of storage devices in the first zone.
    Type: Application
    Filed: January 30, 2007
    Publication date: July 31, 2008
    Inventors: Donald Scott Smith, Brian James Cagno, Kenny Nian Gan Qiu
  • Publication number: 20080178043
    Abstract: To implement pipelining, data from a first test written in a DBMS procedural language (such as PL/SQL) is automatically passed to a second test which may or may not be in the same language. A user creates a container test to identify names of the two tests, and adds one or more procedure(s) with predetermined name(s), to identify dependencies between the tests. In the first test, to supply data for the second test, the user includes one or more additional procedure(s) of predetermined name(s), to support an interface to a runtime data store. The second test reads data from the runtime data store. In certain embodiments, an adapter extracts test names from the container test and uses each name to create an object for each test, and during execution of methods in each object a database call is issued.
    Type: Application
    Filed: January 22, 2007
    Publication date: July 24, 2008
    Applicant: Oracle International Corporation
    Inventor: Minyi Xu
  • Publication number: 20080172579
    Abstract: The invention relates to a test device (1) and associated method for verifying a batch processing in a data processing device (2) comprising a first scheduling device (3) for controlling a data processing which processes the script library (5) scripts by means of a first script interface (4), thereby carrying out or controlling the operation of a company subordinate devices. The aim of said invention is to verify a batch processing without degrading a verifiable system performance. For this purpose, a second scheduling device (7) for simulating the processing of the script library (5) scripts and for transmitting said scripts to the device (1) for testing data resulting from the simulation by a second script interface (8) dependent of the first scheduling device (3) is added.
    Type: Application
    Filed: March 10, 2006
    Publication date: July 17, 2008
    Inventors: Uwe Hahm, Roland Griessbach
  • Publication number: 20080155336
    Abstract: A method, system and program product for dynamically identifying one or more components or resources contributing to a service degradation is provided. The method includes providing a dynamic correlation logic tool having logic that is configured to dynamically build a model for an application experiencing a service degradation at a given point-in-time. Further, the method includes obtaining from a configuration management database configuration data for resources utilized by the application experiencing the service degradation at that point-in-time and dynamically building the model using the configuration data obtained and status data obtained from monitoring sources that monitor the resources. Further, the method includes evaluating and analyzing the model, using the logic provided, and identifying one or more resources utilized by the application contributing to the service degradation.
    Type: Application
    Filed: December 20, 2006
    Publication date: June 26, 2008
    Applicant: International Business Machines Corporation
    Inventors: Niraj P. Joshi, Kenneth J. Parzygnat, Wayne B. Riley