Abstract: A post-routing path delay prediction method for a digital integrated circuit is provided. First, physical design and static timing analysis are performed on a circuit by a commercial physical design tool and a static timing analysis tool, timing and physical information of a path is extracted before routing of the circuit to be used as input features of a prediction model, then the timing and physical correlation of all stages of cells in the path is captured by a transformer network, a predicted post-routing path delay is calibrated by a residual prediction structure, and finally, a final predicted post-routing path delay is output.

Abstract: Systems, computer-implemented methods, and computer program products to facilitate batched quantum circuits simulation on a graphics processing unit are provided. According to an embodiment, a system can comprise a first processor that executes computer executable components stored in memory. The computer executable components can comprise a generalization component that generates a first defined matrix representation of a qubit gate and that employs a control mask to generate a second defined matrix representation of a multi-qubit gate. The computer executable components can further comprise an execution component that executes a kernel overhead operation using the first defined matrix representation and the second defined matrix representation to generate a batched kernel.

Abstract: A memory with reduced power consumption during a write assist period is provided that includes a series of inverters configured to delay a write assist signal to form a delayed write assist signal at a first terminal of a boost capacitor. A cutoff switch transistor couples between ground and a ground node of a final inverter in the series of inverters. A clock circuit switches off the cutoff switch transistor to isolate the first terminal of the boost capacitor before an end of a write assist period.

Abstract: Selective frequency dissipation is implemented that enables cooling of energy gap protected qubits such that excited energy states resulting from heating or other undesired processes are returned to a lower excited energy state or a ground state manifold, thus reducing the probability of errors. Also, the selective frequency dissipation inhibits leakage from the energy gap protected qubits when in the ground state.

Abstract: A method in certain embodiments includes using a computer system that includes an EDA tool to generate a layout of an IC device; searching, using a statistical method such as Bayesian optimization process, for one or more input variable parameters, such as the dimensions of the IC device and the dimensions of the voltage areas in the IC device, that results in an optimal characteristic, such as power, performance or area (PPA) of the IC device, subject to a limiting condition, such as one determined using a cost function. A computer system including one or more EDAs configured to perform the method is also disclosed.

Abstract: New techniques for the partitioning of big element blocks in a circuit are disclosed. The techniques partition both pre-layout and post-layout circuits. If a post-layout circuit has different simulation results from a pre-layout circuit, the techniques determine where and how “cross-talk” of the RC networks due to RC extraction is changing the circuit physics behavior from the original design of the circuit. A flow of the local circuit simulation of the pre-layout netlist and the post-layout netlist of the same design is presented. A flow of reference or relative or differential circuit simulation of a known design and a new design of the same kind is described. This Abstract is not intended to limit the scope of the claims.

Abstract: A system includes a high-bandwidth inter-chip network (ICN) that allows communication between parallel processing units (PPUs) in the system. For example, the ICN allows a PPU to communicate with other PPUs on the same compute node or server and also with PPUs on other compute nodes or servers. In embodiments, communication may be at the command level (e.g., at the direct memory access level) and at the instruction level (e.g., the finer-grained load/store instruction level). The ICN allows PPUs in the system to communicate without using a PCIe bus, thereby avoiding its bandwidth limitations and relative lack of speed. The respective routing tables comprise information of multiple paths to any given other PPU.

Abstract: A memory check method, a memory check device and a memory check system are disclosed. The method includes the following. A debug file is generated according to a source code, where the debug file carries symbol information related to a description message in the source code. Memory data generated by a memory storage device in execution of a firmware is received. The debug file is loaded to automatically analyze the memory data. In addition, an analysis result is presented by an application program interface, where the analysis result reflects a status of the firmware with assistance of the symbol information.

Abstract: Embodiments include herein are directed towards a system and method for intelligent intent recognition based electronic design. Embodiments may include receiving, using a processor, a natural language input from a user at an intent recognition model. Embodiments may also include performing intent recognition on the natural language input at the intent recognition model and providing an output from the intent recognition model to a command generator. Embodiments may further include generating a command based upon, at least in part, the output and executing the command at a target tool environment.

Abstract: Described is technology for automatically generating a routing for an integrated circuit (IC) design. Information describing pin-pairs of an integrated circuit (IC) design is received. An initial routing of the IC design is determined by (i) defining connected wires between each pin-pair in the set of pin-pairs, and (ii) evaluating a target resistance for the pin-pair over the connected wires, wherein each connected wire is routed with other connected wires. A resistance adjustment is applied to adjust wire resistance of the connected wires of the initial routing. The resistance adjustment can be based on a square routing in response to a wire resistance being below the target resistance; or the resistance adjustment can be based on a multi-layer stacking in response to the wire resistance being above the target resistance. The routing is provided in patterns as generated by the initial routing and the resistance adjustment.

Abstract: The present disclosure provides a surface mount data conversion method, system, medium and apparatus based on a component three-dimensional database. The surface mount data conversion method based on a component three-dimensional database includes: creating a component 3D database required in a circuit board designing stage and creating a production process template library required in a circuit board production stage; and performing data conversion on the component 3D database and the production process template library to generate a component image library for use in the production stage. The present disclosure can avoid repeated work, achieve real-time update and match of production data, and reduce the error rate caused by the production data during circuit board production.

Abstract: Systems and methods are disclosed for to generation of dynamic design flows for integrated circuits. For example, a method may include accessing a design flow configuration data structure, wherein the design flow configuration data structure is encoded in a tool control language; based on the design flow configuration data structure, selecting multiple flowmodules from a set of flowmodules, wherein each flowmodule provides an application programming interface, in the tool control language, to a respective electronic design automation tool; based on the design flow configuration data structure, generating a design flow as a directed acyclic graph including the selected flowmodules as vertices; and generating an output integrated circuit design data structure, based on one or more input integrated circuit design data structures, using the design flow to control the respective electronic design automation tools of the selected flowmodules.

Abstract: An aggregate representation of a collection of source code examples is constructed. The collection includes positive examples that conform to a coding practice and negative examples do not conform to the coding practice. The aggregate representation includes nodes corresponding to source code elements, and edges representing relationships between code elements. Using an iterative analysis of the aggregate representation, a rule to automatically detect non-conformance is generated. The rule is used to provide an indication that a set of source code is non-conformant.

Abstract: A simulation model of a multilayer capacitor for three-dimensional electromagnetic simulation includes a pair of input/output ports, a plate-shaped first internal electrode model and a plate-shaped second internal electrode model between the pair of input/output ports. A capacitance, an equivalent series resistance, and an equivalent series inductance obtained from an actually measured value of an impedance characteristic of the multilayer capacitor are set for the first internal electrode model and the second internal electrode model. The first internal electrode model faces two side surfaces opposed in a width direction of the multilayer capacitor. The second internal electrode model faces two main surfaces opposed in a height direction intersecting the width direction of the multilayer capacitor.

Abstract: Systems and methods for low latency materialized information provision are disclosed. For example, a system may include at least one memory storing instructions and one or more processors configured to execute the instructions to perform operations. The operations may include receiving, via a materialization service, data from multiple sources related to an item associated with a webpage hosted by a server. The data may include first event data sourced from a real-time feed and second event data sourced from stored data. Operations may include generating synchronized data based on the first and second event data. Operations may include receiving a request from the web server for information related to the item, the request being associated with a user segment. Operations may include identifying data to aggregate to fulfill the request, generating a data structure gathering synchronized data using the data structure, and forwarding the gathered synchronized data to the server.

Abstract: A method for providing access to a development and execution (D&E) platform for development of industrial software, including providing while the D&E platform is being accessed a GUI with a development tool having process flow and code editors and an execution tool and arranging two or more programming blocks of a process flow responsive to input from an author when the process flow editor is accessed. The two or more programming blocks, when arranged, are configured to be executed. The method further includes editing source code of the two or more programming blocks responsive to input from the author when the code editor is accessed, compiling at least one of the two or more programming blocks responsive to input from the author when the execution tool is accessed, and executing the compiled at least one programming block responsive to input from the author when the execution tool is accessed.

Abstract: Detecting sequential access violations for high-level synthesis (HLS) includes performing a simulation, using computer hardware, of an application for HLS. During the simulation, accesses of the application to elements of an array of the application are detected. During the simulation, determinations of whether the accesses occur in a sequential order are made. An indication of whether the access occur in sequential order is generated.

Abstract: A network processing element and method for using it, are provided for use in a cluster comprising a plurality of network processing elements, wherein the network processing element is configured to enable provisioning of a plurality of different services, wherein the network processing element is configured to store state data associated with one or more functions required for carrying out each of the plurality of different services, and wherein the network processing element is further configured to provide a service or part thereof, based on the state data associated the network processing element's processing resources required for carrying out one or more functions in the provisioning of the requested service.

Abstract: A method and a device for planning a specific process system, wherein during the planning of a specific process system, which consists of primary technology formed as components of the system that are interconnected with respect to process and at least one secondary technology that depends on the primary technology and enables operation of the system together with the primary technology, the primary technology is planned as a flow diagram of the system via a system planning tool, where configuration data formed as requirements, guidelines for operation of the system, system-specific basic conditions and/or specifications are added to the flow diagram, and where a data-processing device evaluates the flow diagram to which the configuration data have been added and automatically creates, optionally by accessing an archive having standard planning solutions, a specific planning solution for a secondary technology that meets the various requirements together with the planned primary technology.

Abstract: In at least one cell region, a semiconductor device includes fin patterns and at least one overlying gate structure. The fin patterns (dummy and active) are substantially parallel to a first direction. Each gate structure is substantially parallel to a second direction (which is substantially perpendicular to the first direction). First and second active fin patterns have corresponding first and second conductivity types. Each cell region, relative to the second direction, includes: a first active region which includes a sequence of three or more consecutive first active fin patterns located in a central portion of the cell region; a second active region which includes one or more second active fin patterns located between the first active region and a first edge of the cell region; and a third active region which includes one or more second active fin patterns located between the first active region and a second edge of the cell region.

Abstract: In one aspect, a transistor-level description of a circuit is accessed, where the circuit includes a plurality of transistors. A transistor-level circuit simulation of the circuit's response to an input stimulus is performed, based on the transistor-level description of the circuit. Activity levels for the transistors in the circuit are determined from the transistor-level circuit simulation. A graphical representation of the circuit is rendered. The graphical representation contains graphical elements that represent components of the circuit, and the graphical elements are visually coded according to the activity levels of the transistors in the corresponding components.

Abstract: High level synthesis (HLS) begins with high-level specification of a problem, where behavior is generally decoupled from e.g., clock-level timing. Programming code can be run and debugged during functional simulation using debugging techniques. However, it is not possible to understand execution flow of register transfer level instructions (RTL) generated during RTL debug. Conventionally, it is challenging and not possible due to nature of debugging techniques which ignore printf statements in code for invocation. Systems and methods of present disclosure synthesize printf and/or scanf statements for generating debug messages in HLS code, wherein printf and/or scanf statements is/are included before/after function(s) in sections comprising instructions in code and synthesized as a block during run-time which communicate with host system and debug messages are generated for display on screen.

Abstract: Methods, apparatus and computer program product for protecting a confidential integrated circuit design process.

Abstract: A system to support a machine learning (ML) operation comprises a core configured to receive and interpret commands into a set of instructions for the ML operation and a memory unit configured to maintain data for the ML operation. The system further comprises an inference engine having a plurality of processing tiles, each comprising an on-chip memory (OCM) configured to maintain data for local access by components in the processing tile and one or more processing units configured to perform tasks of the ML operation on the data in the OCM. The system also comprises an instruction streaming engine configured to distribute the instructions to the processing tiles to control their operations and to synchronize data communication between the core and the inference engine so that data transmitted between them correctly reaches the corresponding processing tiles while ensuring coherence of data shared and distributed among the core and the OCMs.

Abstract: A computer implemented method for analyzing and verifying software for safety and security. A software program comprising a sequence of program statements to be executed is provided. A compact representation of the program is computed, and the subset of program statements that are relevant to a property of the software to be verified is identified. A homomorphism that maps non-relevant program statements to an identity is computed, and the property is verified using the homomorphism.

Abstract: Disclosed is a physical unclonable function generator circuit and method. In one embodiment, a physical unclonable function (PUF) generator comprising: a plurality of PUF cells, wherein each of the plurality of PUF cells comprises a first MOS transistor and a second MOS transistor, wherein terminal S of the first MOS transistor is connected to terminal D of the second MOS transistor at a dynamic node, terminal D of the first MOS transistor is coupled to a first bus and terminal G of the first NMOS transistor is coupled to a second bus, and terminals S and G of the second NMOS transistor are coupled to ground; a plurality of dynamic flip-flop (DFF) circuits wherein each of the plurality of DFF circuits is coupled to each of the plurality of PUF cells respectively; a population count circuit coupled to the plurality of DFF circuits; and an evaluation logic circuit having an input coupled to the population count circuit and an output coupled to the plurality of DFF circuits.

Abstract: Systems and methods are disclosed for to generation of dynamic design flows for integrated circuits. For example, a method may include accessing a design flow configuration data structure, wherein the design flow configuration data structure is encoded in a tool control language; based on the design flow configuration data structure, selecting multiple flowmodules from a set of flowmodules, wherein each flowmodule provides an application programming interface, in the tool control language, to a respective electronic design automation tool; based on the design flow configuration data structure, generating a design flow as a directed acyclic graph including the selected flowmodules as vertices; and generating an output integrated circuit design data structure, based on one or more input integrated circuit design data structures, using the design flow to control the respective electronic design automation tools of the selected flowmodules.

Abstract: The disclosure describes the implementation of automated techniques for optimizing quantum circuits of the size and type expected in quantum computations that outperform classical computers. The disclosure shows how to handle continuous gate parameters and report a collection of fast algorithms capable of optimizing large-scale-scale quantum circuits. For the suite of benchmarks considered, the techniques described obtain substantial reductions in gate counts. In particular, the techniques in this disclosure provide better optimization in significantly less time than previous approaches, while making minimal structural changes so as to preserve the basic layout of the underlying quantum algorithms.

Abstract: A method includes instantiating a simulation of an electronic design for a device under test (DUT) in hardware design language responsive to a user selection thereof. A subset of leaf nodes from a plurality of leaf nodes from the electronic design with input/output signaling of more than two values is identified. A hierarchical path for each leaf node of the plurality of leaf nodes of the electronic design for the DUT with respect to a testbench is calculated. A bypass module for the subset of leaf nodes is generated. The bypass module is generated in response to detecting presence of the subset of leaf nodes in the electronic design with input/output signaling of more than two values. The bypass module facilitates communication between the testbench and the subset of leaf nodes. Leaf nodes other than the subset of leaf nodes communicate with the testbench without communicating through the bypass module.

Abstract: An input output circuit and an electrostatic discharge (ESD) protection circuit are provided. The ESD protection circuit is adapted to a charged-device model (CDM). The ESD protection circuit includes a bipolar junction transistor (BJT). The BJT has a first end coupled to an input end of an input buffer and an output end of an output buffer. A second end of the BJT is coupled to a first ground rail. A control end of the BJT is coupled to one of a first power rail, a second power rail, the first ground rail and a second ground rail.

Abstract: A system displays a visual representation of the operation of an electronic circuit. The position of graphical elements representing values of signals in the circuit convey information about the operation of the circuit. The visual representation may further depict navigable levels of hierarchy of the electronic circuit.

Abstract: Implementations disclosed herein may include receiving from a user a selection of at least one die, a package type, and at least one test condition; generating, using a processor, a product die configuration and a product package configuration using a predictive modeling module and the at least one die and the package type; generating a graphic design system file; generating a package bonding diagram; generating a product spice model of the discrete device product using a technology computer aided design module; generating, using a processor, one or more datasheet characteristics of the discrete device product with the product SPICE model; generating a product datasheet for the discrete device product using the graphic design system file; and using a second interface generated by a computing device to provide access to the graphic design system file, the package bonding diagram, the product datasheet, and the product SPICE model.

Abstract: Implementations of a method of designing a module semiconductor product may include receiving a selection of a module type, one or more die, a placement of one or more wires, clips, or pins; and generating, using a processor, a module configuration file. The method may include generating a module bonding diagram using a build diagram system module; selecting one or more SPICE models corresponding with the die; and generating a product SPICE model and a three dimensional model for the module semiconductor product. The method may include generating one or more datasheet characteristics of the module semiconductor product with at least the product SPICE model and the product simulation module, generating a product datasheet for the module semiconductor product using the datasheet formation module, and providing access to at least the module bonding diagram, the product SPICE model, the three dimensional model, and the product datasheet to the user.

Abstract: Disclosed herein are system, computer-readable storage medium, and method embodiments of machine-learning (ML)-based static verification for derived hardware-design elements. A system including at least one processor may be configured to extract a feature set from a hardware description and evaluate a similarity index of a first hardware element with respect to a second hardware element, using an ML process based on the feature set, wherein the first hardware element is described in the hardware description. The at least one processor may be further configured to update one or more parameters corresponding to a static verification of the hardware description while the static verification is being performed, by providing at least one test attribute, corresponding to the second hardware element, applicable to the first hardware element, in response to determining that the similarity index is within a specified range, and additionally output a first result of the static verification.

Abstract: A method for managing HDD expanders in a cluster storage system is provided. The method according to one embodiment is implemented by each of the HDD expanders, and includes: indicating a device type of HDD expander to a parent node thereof when a device-type request originates from the parent node; and indicating a device type not of HDD expander to the parent node otherwise. The method according to another embodiment is implemented by each HDD expander connected indirectly to a root node, and includes: indicating a device type not of HDD expander to the root node when a device-type request originates from the root node; and indicating a device type of HDD expander to a node that initiates the device-type request otherwise.

Abstract: A random code generator includes a differential cell array, a power supply circuit, a first selecting circuit and a current judgment circuit. The power supply circuit receives an enrolling signal and a feedback signal. The first selecting circuit receives a first selecting signal. When the enrolling signal is activated and an enrollment is performed on the first differential cell, the power supply circuit provides an enrolling voltage, and the enrolling voltage is transmitted to a first storage element and a second storage element of the first differential cell through the first selecting circuit. Consequently, the cell current is generated. When a magnitude of the cell current is higher than a specified current value, the current judgment circuit activates the feedback signal, so that the power supply circuit stops providing the enrolling voltage.

Abstract: Implementing an asymmetric memory having random port ratios using memory primitives can include detecting, using computer hardware, a hardware description language (HDL) random access memory (RAM) within a circuit design. The HDL RAM is asymmetric. Using computer hardware, a number of a plurality of memory primitives needed to implement the HDL RAM as a RAM circuit are determined based on a maximum port width ratio of the memory primitives defined as 1:N and a port width ratio of the HDL RAM defined as 1:M, wherein each of M and N is an integer and a power of two and M exceeds N. The RAM circuit is asymmetric. Using the computer hardware, a write circuit and/or a read circuit can be generated for a first port of the RAM circuit. Further, using the computer hardware, a write circuit and/or a read circuit can be generated for a second port of the RAM circuit.

Abstract: A system for optimizing scan pipelining may include a processor and a memory. The processor may generate and insert, based on prior analysis of the physical layout of the circuit, an optimized number of pipeline stages between a first block and a second block in a hardware test design, a first scan chain including at least one pipeline stage of a head pipeline stage or a tail pipeline stage. The processor may insert a plurality of flip-flops into the first scan chain. The processor may determine at least one clock to be used for the at least one pipeline stage, using the plurality of flip-flops so as to eliminate the need of a lockup element between the at least one pipeline stage and the plurality of flip-flops. The processor may generate, based on the at least one clock, a second scan chain that connects the at least one pipeline stage and the plurality of flip-flops.

Abstract: This application is directed to a power monitoring system for virtual platform simulation. In one embodiment, a simulation system may comprise a virtual power monitor (VPMON) and a performance simulator. An example VPMON module may include at least a system agent (SA) module to receive virtual platform data from the performance simulator. The SA module may then be further to determine at least one component power model based on the virtual platform data, and may proceed to formulate a platform power model based on the at least one component power model. During simulation of the virtual platform, the SA module may be further to generate power data corresponding to the virtual platform based on the platform power model. For example, the SA module may obtain performance data from the performance simulator, and may provide the performance data to the platform power model to generate the power data.

Abstract: A method of programming a device comprising acquiring configuration data, loading the configuration data onto a programmable device, processing at least a portion of the configuration data through a one way function to form processed configuration data, and configuring at least one configurable module of the programmable device using the processed configuration data from the processing step.

Abstract: A heterogeneous multi-core integrated circuit comprising two or more processors, at least one of the processors being a general purpose CPU and at least one of the processors being a specialized hardware processing engine, the processors being connected by a processor local bus on the integrated circuit, wherein the general purpose CPU is configured to generate a first instruction for an atomic operation to be performed by a second processor, different from the general purpose CPU, the first instruction comprising an address of the second processor and a first command indicating a first action to be executed by the second processor, and transmit the first instruction to the second processor over the processor local bus. The first command may include the first action, or may be a descriptor of the first action or a pointer to where the first action may be found in a memory.

Abstract: One embodiment of the present disclosure describes a memory system that may include one or more memory devices that may store data. The memory devices may receive command signals to access the stored data as a loopback signal. The memory devices may operate in a normal operational mode, a loopback operational mode, a retrieval operational mode, a non-inverting pass-through operational sub-mode, and an inverting pass-through operational sub-mode. The operational modes facilitate the transmission of the loopback signal for the purpose of monitoring of memory device operations. A selective inversion technique, which uses the operational modes, may protect the loopback signal integrity during transmission.

Abstract: Methods and apparatus relating to techniques for a dual path sequential element to reduce toggles in data path are described. In an embodiment, switching logic causes signals for a single data path of a processor to be directed to at least two separate data paths. At least one of the two separate data paths is power gated to reduce signal toggles in the at least one data path. Other embodiments are also disclosed and claimed.

Abstract: Various systems and methods are provided that display schematics and data associated with the various physical components in the schematics in an interactive user interface. For example, a computing device links data stored in one or more databases with schematics displayed in one or more interactive user interfaces. The computing device parses a digital image that depicts a schematic and identifies text visible in the digital image. Based on the identified text, the computing device recognizes representations of one or more physical components in the schematic and links the representations to data regarding the physical component in one or more databases, such as specification data, historical sensor data of the component, etc. The computing device modifies the digital image such that it becomes interactive and visible in a user interface in a manner that allows the user to select a physical component and view data associated with the selection.

Abstract: Computing systems, database systems, and related methods are provided for supporting dynamic validation workflows. One exemplary method involves a server of a database system receiving a graphical representation of a validation process from a client device coupled to a network, converting the graphical representation of the validation process into validation code, and storing the validation code at the database system in association with a database object type. Thereafter, the validation process is performed with respect to an instance of the database object type using the validation code in response to an action with respect to the instance of the database object type in a database of the database system. The action triggering the validation process can be based on user-configurable triggering criteria, and the validation process may generate user-configurable notifications based on one or more field values of the database object instance.

Abstract: There is provided a method and system (200) for power management of an event-based processing system (100). The system (200) is configured to obtain information representing a history of arrival times of events, wherein the information comprises arrival timestamps of the events. The system (200) is configured to determine a measure for power management based on the timestamps of at least two events represented in the information. The system (200) is also configured to perform power management based on the determined measure.

Abstract: Aspects of the present disclosure address systems and methods for local cluster refinement for integrated circuit (IC) designs using a dynamic weighting scheme. Initial cluster definitions are accessed. The initial cluster definitions define a plurality of clusters where each cluster includes a plurality of pins. Each cluster is evaluated with respect to one or more design rule constraints. Based on the evaluation, clusters are identified from the plurality of clusters. A set of refinement candidates are generated based on the one or more clusters. A scoring function that employs a dynamic weighting scheme is used to determine a refinement quality score for each refinement candidate in the set of candidates and one or more refinement candidates are selected from among the set of refinement candidates based on respective refinement quality scores. A refined clustering solution is generated based on the selected refinement candidates.

Abstract: Systems and methods are disclosed for secret sharing for secure collaborative graphical design. Graphical secret shares are generated from a three-dimensional graphical design and distributed to one or more contributor devices. Contributor graphical designs modifying graphical secret shares may be received from contributor devices. Various corresponding and related systems, methods, and software are described.

Abstract: Means and a computerized method for recommending items such as books and audio compact disks. For each item, a user profile includes ratings provided by users of the system. Unlike present recommendation systems, the user profiles do not include pre-computed similarity factors measuring similarity between users. Rather, when an advisee requests a recommendation, similarity measures are computed comparing the advisee to other users, and the similarity measures are associated with the other users. A subset of the users is selected, where the subset includes the users most similar to the advisee. A recommendation is made based on the ratings by the members of the selected subset.

Abstract: A method and system for evaluating software tools that detect malicious hardware modifications is provided. In one embodiment, among others, a system comprises a computing device and an application. The application causes the computing device to at least receive hardware description language code that represents a circuit design and calculate a signal probability for one or more nodes in the circuit design. The application also causes the computing device to identify one or more rare nodes in the circuit design and generate a Trojan sample population. The application further causes the computing device to generate a feasible Trojan population and generate a Trojan test instance based at least in part on a random selection from the Trojan feasible population. Additionally, the application causes the computing device to generate modified hardware description code from the Trojan test instance.