Design Entry Patents (Class 716/102)
  • Patent number: 10417364
    Abstract: Embodiments are directed towards a method to create a reconfigurable interconnect framework in an integrated circuit. The method includes accessing a configuration template directed toward the reconfigurable interconnect framework, editing parameters of the configuration template, functionally combining the configuration template with a plurality of modules from an IP library to produce a register transfer level (RTL) circuit model, generating at least one automated test-bench function, and generating at least one logic synthesis script. Editing parameters of the configuration template includes confirming a first number of output ports of a reconfigurable stream switch and confirming a second number of input ports of the reconfigurable stream switch. Each output port and each input port has a respective architectural composition. The output port architectural composition is defined by a plurality of N data paths including A data outputs and B control outputs.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: September 17, 2019
    Assignees: STMICROELECTRONICS INTERNATIONAL N.V., STMICROELECTRONICS S.R.L.
    Inventors: Thomas Boesch, Giuseppe Desoli
  • Patent number: 10417374
    Abstract: A method for designing a system on a target device includes synthesizing the system. The system is placed on the target device. The system is routed on the target device. Register retiming is performed on the system by applying timing analysis constraints, retiming constraints, bound constraints, and ordering constraints when solving for retiming labels that represent a number and direction of register movement along a path between nodes in the system, and arrival times on all nodes in the system to reflect the maximum delay in the system, to improve timing and meet target delay constraints.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: September 17, 2019
    Assignee: Altera Corporation
    Inventor: Mahesh A. Iyer
  • Patent number: 10410736
    Abstract: An apparatus includes a memory and a controller. The memory may be configured to store data. The controller may be configured to process a plurality of input/output requests to a plurality of blocks of the memory that are not marked as bad on a block list, perform a code rate test that programs the plurality of blocks of the memory at three or more code rates of an error correction code scheme, and mark any of the plurality of blocks identified as bad during the code rate test on the block list.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: September 10, 2019
    Assignee: Seagate Technology LLC
    Inventors: Zhengang Chen, David Patmore, Yingji Ju, Erich F. Haratsch
  • Patent number: 10409611
    Abstract: An apparatus and method is described herein for providing robust speculative code section abort control mechanisms. Hardware is able to track speculative code region abort events, conditions, and/or scenarios, such as an explicit abort instruction, a data conflict, a speculative timer expiration, a disallowed instruction attribute or type, etc. And hardware, firmware, software, or a combination thereof makes an abort determination based on the tracked abort events. As an example, hardware may make an initial abort determination based on one or more predefined events or choose to pass the event information up to a firmware or software handler to make such an abort determination. Upon determining an abort of a speculative code region is to be performed, hardware, firmware, software, or a combination thereof performs the abort, which may include following a fallback path specified by hardware or software.
    Type: Grant
    Filed: December 26, 2015
    Date of Patent: September 10, 2019
    Assignee: Intel Corporation
    Inventors: Martin G. Dixon, Ravi Rajwar, Konrad K. Lai, Robert S. Chappell, Rajesh S. Parthasarathy, Alexandre J. Farcy, Ilhyun Kim, Prakash Math, Matthew Merten, Vijaykumar Kadgi
  • Patent number: 10393803
    Abstract: One embodiment of the present disclosure describes a memory system that may include one or more memory devices that may store data. The memory devices may receive command signals to access the stored data as a loopback signal. The memory devices may operate in a normal operational mode, a loopback operational mode, a retrieval operational mode, a non-inverting pass-through operational sub-mode, and an inverting pass-through operational sub-mode. The operational modes facilitate the transmission of the loopback signal for the purpose of monitoring of memory device operations. A selective inversion technique, which uses the operational modes, may protect the loopback signal integrity during transmission.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: August 27, 2019
    Assignee: Micron Technology, Inc.
    Inventor: David D. Wilmoth
  • Patent number: 10394704
    Abstract: The present disclosure relates to a method and a device for testing a software program. The method of the present disclosure simulates, in a simulation process, a predetermined scenario on a test platform in a test scenario. The test platform in this simulation process generates output values based on input stimuli, and a dynamic adaption of the test scenario takes place during the simulation process based on the current state of the simulation process.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: August 27, 2019
    Assignee: Ford Global Technologies, LLC
    Inventors: Norbert Wiechowski, Norman Hansen, Alexander Kugler, Stefan Kowalewski, Thomas Rambow, Rainer Busch
  • Patent number: 10387821
    Abstract: One or more implementations relate generally to a platform architecture planning process utilizing architecture type unit definitions. For example, an architecture for realizing a customer system on a cloud computing platform may be defined in terms of a plurality of architecture types, each type (AT) defined by plural architecture type units (ATUs), and each ATU comprising a set of ATU Details.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: August 20, 2019
    Assignee: SALESFORCE.COM, INC.
    Inventors: Gerhard Friedrich Mack, Stefan Pühl
  • Patent number: 10386824
    Abstract: During commissioning activities of a process plant, a device placeholder object that stores an I/O-abstracted configuration of a particular field device within the plant is created and stored in a device in the back-end environment of the plant and a further configuration file is stored in or for the particular field device in the field equipment environment of the plant. The device placeholder object, which will eventually be associated with the particular field device, and the field device configuration file are used to perform separate commissioning activities in each of these plant environments before the field devices are configured to communicate with a process controller via a particular I/O network within the plant. Thereafter, a binding application performs a discovery process to detect the I/O communication path through which each field device is connected to the back-end environment.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: August 20, 2019
    Assignee: FISHER-ROSEMOUNT SYSTEMS, INC.
    Inventors: Larry O. Jundt, Gary K. Law, Cristopher Ian S. Uy, Deborah R. Colclazier, Sergio Diaz, Julian K. Naidoo, Neil J. Peterson, Kent A. Burr, Daniel R. Strinden
  • Patent number: 10380295
    Abstract: Disclosed are techniques for verifying X-behavior in electronic designs. These techniques identify at least a portion of an electronic design, wherein the at least the portion that includes an input node, an output node, and an internal node located between the input node and the output node. Internal X-propagation proof results may be generated for the internal node based in part or in whole upon an internal precondition and an internal harmless condition for the internal node. X-propagation verification for the output node may then be performed based in part upon one or more assumed properties at the internal node, wherein the one or more assumed properties are assumed at the internal node based in part or in whole upon the internal X-propagation proof results.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: August 13, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Chung-Wah Norris Ip, Georgia Penido Safe
  • Patent number: 10380298
    Abstract: Systems and methods for validating a circuit design are described. The circuit validation includes determining a subset of checks to apply to a portion of the overall circuit based on the pin type composition of the circuit portion.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: August 13, 2019
    Assignee: Mentor Graphics Corporation
    Inventors: Michael Alam, Peter Campbell, Mark Cianfaglione
  • Patent number: 10380291
    Abstract: A system and method for web-based interface design tool is provided. The design tool enables system designers to quickly and independently design a custom serial-link interface. The system provides interface selection and signal integrity analysis. An interface selection may interact with system designers to prompt for a set of selection criteria such as data-rate, supply rail, standard protocol, and intended application. An intelligent search engine screens through a large interface products database based on the selection criteria and provides designers with a list of devices that potentially meet the design criteria. The performance of the custom system with the selected device can be evaluated by using a web-based IBIS-AMI standard-compliant signal integrity simulator. A designers can have options to manually fine tune selected devices' parameters to iterate through different settings to determine the robustness of the solution.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: August 13, 2019
    Assignee: Texas Instruments Incorporated
    Inventors: Kian Haur Chong, Makram Monzer Mansour, Ashwin Vishnu Kamath, Srikanth Pam, Yudhister Satija, Nithya Narayanaswamy, Khang Duy Nguyen, Pavani Jella, Jeff Perry, Pradeep Kumar Chawda
  • Patent number: 10338888
    Abstract: An electronic component footprint setup system in collaboration with a circuit layout system and a method thereof are provided in the present disclosure. The electronic component footprint setup system in collaboration with a circuit layout system provides a user operating the circuit layout system with an interface on which parameters of an electronic component footprint to be created are configured; the parameters of the electronic component footprint are transformed for conforming to electronic component footprint specifications used in the circuit layout system; characteristic values of the electronic component footprint are calculated according to electronic component footprint specifications and electronic component footprint setup regulations; the electronic component footprint is created in the circuit layout system according to the characteristic values.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: July 2, 2019
    Assignee: Footprintku Inc.
    Inventors: Cheng-Ta Lu, Yu-Cheng Hu, Guan-Yu Shih, Kun-You Lin, Mong-Fong Horng
  • Patent number: 10339243
    Abstract: A method for designing a system on a target device is disclosed. The system is synthesized. The system is partitioned into a plurality of logical sections utilizing information derived from synthesizing the system and prior to performing placement of the system on the target device. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: July 2, 2019
    Assignee: ALTERA CORPORATION
    Inventors: Scott James Brissenden, Paul McHardy
  • Patent number: 10339263
    Abstract: An electronic component footprint verification system and a method thereof are provided in the present disclosure. The system is available to an external user for selecting an electronic component footprint to be verified, reading a verification rule checklist in an external database, extracting characteristics of the electronic component footprint, accessing characteristic data from the electronic component footprint, verifying the characteristic data based on the verification rule checklist, and displaying a verification result.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: July 2, 2019
    Assignee: Footprintku Inc.
    Inventors: Yu-Siang Fan Jiang, Mong-Fong Fan Horng, Yan-Jhih Wang, Jun-Qiang Wei, Yi-Ting Chen
  • Patent number: 10339258
    Abstract: Some embodiments determine a merged timing graph for a multi-instance module (MIM), wherein each node in the merged timing graph corresponds to a pin in the MIM, and wherein each node in the merged timing graph stores timing information associated with the corresponding pins in multiple instances of the MIM in a circuit design. The embodiments can then determine an ECO for the MIM based on the merged timing graph.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: July 2, 2019
    Assignee: SYNOPSYS, INC.
    Inventors: Seungwhun Paik, Nahmsuk Oh, Subramanyam Sripada, Rupesh Nayak
  • Patent number: 10331847
    Abstract: An automated electronic component footprint setup system and a method thereof are provided in the present disclosure. The system is available to not only an external first user for configuring characteristic parameters of an electronic component for the database but also an external second user for configuring setup parameters of an electronic component footprint to be created. Then, the system is to create an electronic component footprint of a specific electronic layout system according to the characteristic parameters of the electronic component, component setup regulations and the setup parameters, all of which correspond to the electronic component footprint.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: June 25, 2019
    Assignee: FOOTPRINTKU INC.
    Inventors: Cheng-Ta Lu, Yu-Siang Fan Jiang, Jiun-Huei Ho, Chun-Chieh Tsai, Yi-Ting Chen
  • Patent number: 10318686
    Abstract: Configuration data for an integrated circuit may be generated using logic design equipment to implement an circuit design on the integrated circuit. Implementing the circuit design may include placing functional blocks at optimal locations that increase the maximum operating frequency of the integrated circuit implementing the optimal circuit design. Logic design equipment may perform timing analysis on an initially placed circuit design that includes initially placed functional blocks. The timing analysis may identify one or more critical paths that may be shortened by moving the critical functional blocks within the circuit design to candidate placement locations. A levelized graph representing possible candidate locations and paths between the possible candidate locations may be traversed in a breadth-first search to generate a shortest updated critical path. The critical functional blocks may be moved to candidate locations corresponding to the updated critical path.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: June 11, 2019
    Assignee: Intel Corporation
    Inventors: Shounak Dhar, Mahesh A. Iyer, Love Singhal, Nikolay Rubanov, Saurabh Adya
  • Patent number: 10318689
    Abstract: A computer-implemented method for modifying an original design of an integrated circuit in accordance with an engineering change order (ECO) design includes cloning complex logic gate having multiple logic functions with cloned logic gates in parallel with the corresponding complex logic gates in the original design and the ECO design and expanding each cloned logic gate to corresponding base functionality logic gates to provide an expanded original design and an expanded ECO design using the processor. The method also includes modifying at least a portion of the expanded original design to have a circuit topology that is the same as the expanded ECO design in order to have an input from the expanded original design to an output structure be the same as the input from the expanded ECO design to the output structure in response to an expanded original design input and an expanded ECO design input being non-equivalent.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: June 11, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: George Antony, Ankit N. Kagliwal, Sridhar H. Rangarajan, Vinay K. Singh
  • Patent number: 10311188
    Abstract: A binding data acquiring unit acquires binding data describing a plurality of memory modules as functional modules of a design target circuit. A memory module selecting unit selects an external memory module to be implemented as an external memory outside of the design target circuit from the memory modules described in the binding data on the basis of a constraint condition on the design target circuit.
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: June 4, 2019
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Naoya Okada, Ryo Yamamoto
  • Patent number: 10296680
    Abstract: An apparatus may include a processor caused to: receive indications of selection of experiment designs to compare; receive indications of selection of a set of terms to include in the comparison; for each experiment design, generate a corresponding term correlation graph of a set of term correlation graphs, wherein: the correlation graph comprises horizontal and vertical axes along both of which the set of terms are arranged, at each intersection within the graph, a degree of correlation between terms is indicated with a visual indicator selected from a set of visual indicators, the set of visual indicators is assigned an order that corresponds to a range of degree of correlation, and the range is divided into a set of contiguous sub-ranges, and each visual indicator corresponds to one of the sub-ranges; and present at least two correlation graphs of the set of correlation graphs at adjacent locations on a display.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: May 21, 2019
    Assignee: SAS INSTITUTE INC.
    Inventors: Joseph Albert Morgan, Bradley Allen Jones, Ryan Adam Lekivetz
  • Patent number: 10296701
    Abstract: A computer-implemented method includes performing retiming using a circuit design to determine a retimed variation to the circuit design. The circuit design includes a first set of registers with defined power-up states and the variations each comprise a second set of registers that correspond to the first set of registers. The method includes maintaining fixed power-up states for the second set of registers in the variations. The fixed power-up states for the second set of registers are equivalent to the defined power-up states of the first set of registers. The method includes identifying registers of the second set of registers involved in an initial state conflict, and performing a mitigating action to resolve the initial state conflict to enable retiming to continue while maintaining functionally equivalent behavior as the circuit design. Various choices of initial states are also explored during retiming to increase the effect of retiming.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: May 21, 2019
    Assignee: Altera Corporation
    Inventors: Mahesh A. Iyer, Vasudeva M. Kamath, Robert Lawrence Walker
  • Patent number: 10282508
    Abstract: In one embodiment, a computer-implemented method includes performing retiming using a first circuit design to determine one or more variations to the first circuit design, identifying one or more source registers that are involved in one or more unsuccessful retiming moves due to initial conditions conflicts, and recommending, via a graphical user interface, one or more corrective actions to the one or more source registers to avoid the initial conditions conflicts and improve performance of the one or more variations.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: May 7, 2019
    Assignee: Altera Corporation
    Inventors: Dai Le, Scott James Brissenden
  • Patent number: 10254343
    Abstract: Methods and apparatuses to generate test patterns for detecting faults in an integrated circuit (IC) are described. During operation, the system receives a netlist and a layout for the IC. The system then generates a set of faults associated with the netlist to model a set of defects associated with the IC. Next, the system determines a set of likelihoods of occurrence for the set of faults based at least on a portion of the layout associated with each fault in the set of faults. The system subsequently generates a set of test patterns to target the set of faults, wherein the set of test patterns are generated based at least on the set of likelihoods of occurrence associated with the set of faults.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: April 9, 2019
    Assignee: SYNOPSYS, INC.
    Inventors: Alodeep Sanyal, Girish A. Patankar, Rohit Kapur, Salvatore Talluto
  • Patent number: 10255404
    Abstract: A computer-implemented includes performing retiming using a circuit design to determine variation to the circuit design. The circuit design includes a first set of registers with defined power-up states and the variations each comprise a second set of registers that correspond to the first set of registers. The method includes computing and maintaining programmable power-up states for the second set of registers in the variations. The programmable power-up states computed for the second set of registers are equivalent to the defined power-up states of the first set of registers. The method includes identifying registers of the second set of registers involved in an initial state conflict, and performing a mitigating action to resolve the initial state conflict to enable retiming to continue while maintaining functionally equivalent behavior as the circuit design. Various choices of initial states are also explored during retiming to maximize the effect of retiming.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: April 9, 2019
    Assignee: Altera Corporation
    Inventors: Mahesh A. Iyer, Vasudeva M. Kamath, Robert Lawrence Walker
  • Patent number: 10248550
    Abstract: Techniques for selecting test configurations associated with a particular coverage strength using a constraint solver are disclosed. A set of parameters are configurable for conducting a test on a particular target application. A data model generator identifies one or more candidate test configurations based on the set of parameters. The data model generator determines a set of interactions based on a desired coverage strength. The data model generator specifies a selection variable indicating the candidate test configurations that are selected for testing the particular target application. The data model generator specifies constraint(s) minimizing the number of selected test configurations. The data model generator specifies constraint(s) requiring that each interaction be covered by at least one selected test configuration.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: April 2, 2019
    Assignee: Oracle International Corporation
    Inventors: Serdar Kadioglu, Samir Sebbah
  • Patent number: 10248747
    Abstract: A method for simulating an integrated circuit (IC) is provided. The method includes parsing an IC and loading the IC into memory and forming a table model including parameter values for at least one circuit component in the IC, the parameter values selected from a portion of a parameter space, storing a data value associated with the parsing of the IC and the table model in a database accessible through a cloud computing environment, the data value comprising a metadata associated with the data value, loading, to a processor, at least one of the data value or the metadata from the database, modifying the data value or the metadata that is loaded in the processor, according to the portion of the parameter space, and performing an analysis on at least one block of the IC according to the data value or the metadata that is loaded in the processor.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: April 2, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Jaideep Mukherjee, Saibal Saha, Jianyu Li, Yishan Wang, Walter J. Ghijsen
  • Patent number: 10248146
    Abstract: A system and approach for monitoring and controlling energy consumption. The system may incorporate one or more devices configured on a floor map, a monitor that detects energy consumption by each of the one or more devices, a heat map shown on the floor map, a processor, and a user interface having a display connected to the processor. The heat map may indicate energy consumption in various areas of the floor plan. The floor map with the heat map may be a screen showable on the display. The energy consumption by each of the one or more devices from the monitor may be calculated by the processor in terms of time that each device is active and in terms of a power rating of the respective device. The energy consumption by each of the one or more devices may be converted by the processor into cost. From a screen, a user may define a virtual and dynamic zone to optimize and control the energy consumption with duration to apply the changes.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: April 2, 2019
    Assignee: Honeywell International Inc.
    Inventors: Deepak Sundar Meganathan, Soumen Ghosh
  • Patent number: 10242135
    Abstract: A selection of a source testbench is received from a user. The source testbench includes a description of one or more source parameters, a description of one or more source measurements, and a plurality of source entries, each of the source entries including a value for each of the one or more source parameters and each of the one or more source measurements. Furthermore, a selection of a destination testbench is received. The destination testbench includes a description of one or more destination parameters and a plurality of destination entries including a value for each of the one or more destination parameters. One or more source entries are matched with a destination entry. One or more source measurements of the matched one or more source entries are aggregated based on an aggregation function, and the aggregated source measurements are mapped to the matched source entry.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: March 26, 2019
    Assignee: Synopsys, Inc.
    Inventors: Gajanan Madhukarrao Joshi, Jonathan Lee Sanders, Donald John Oriordan, Ruben Grigoryan, Hui Xu
  • Patent number: 10235489
    Abstract: Methods and systems for fabricating micro-fluidic devices include determining a target cost function value based device design parameters. The performance of one or more chosen design candidates is simulated in a selected simulation model. A design candidate is identified with a cost function value closest to the target cost function value as a best initial design candidate. Design parameters of the best initial design candidate are iteratively modified to provide a modified design candidate having design parameters differing from the design parameters of the best initial design candidate, a cost function value is iteratively calculated for the modified initial design candidate, and optimized device design parameters are iteratively derived from a modified design candidate, until a computed cost function value for the modified design candidate meets the determined target cost function value.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: March 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jaione Tirapu Azpiroz, Peter W. Bryant, Rodrigo N. B. Ferreira, Bruno D. C. Flach, Ronaldo Giro, Ricardo L. Ohta
  • Patent number: 10216174
    Abstract: A system and method for providing an integrated circuit that integrates with and controls a device wherein the integrated circuit design is developed based on a selection of characteristics of the device. The system and method also provide software for establishing interoperability between the integrated circuit and a controller.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: February 26, 2019
    Inventor: Daniel Jakob Seidner
  • Patent number: 10210452
    Abstract: Apparatus and methods for high-level neuromorphic network description (HLND) framework that may be configured to enable users to define neuromorphic network architectures using a unified and unambiguous representation that is both human-readable and machine-interpretable. The framework may be used to define nodes types, node-to-node connection types, instantiate node instances for different node types, and to generate instances of connection types between these nodes. To facilitate framework usage, the HLND format may provide the flexibility required by computational neuroscientists and, at the same time, provides a user-friendly interface for users with limited experience in modeling neurons. The HLND kernel may comprise an interface to Elementary Network Description (END) that is optimized for efficient representation of neuronal systems in hardware-independent manner and enables seamless translation of HLND model description into hardware instructions for execution by various processing modules.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: February 19, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Botond Szatmary, Eugene M. Izhikevich, Csaba Petre, Jayram Moorkanikara Nageswaran, Filip Piekniewski
  • Patent number: 10210298
    Abstract: An integrated circuit for configuring memory block portions is provided. The integrated circuit may include a memory block that is partitioned into first and second memory block portions. The first memory block portion has a first memory type and the second memory block portion has a second memory type that is different than the first memory type. The integrated circuit further includes a control circuit configured to receive configuration data. The configuration data may include memory partition information for repartitioning the first and second memory block portions into first and second repartitioned memory block portions when a portion of the first memory block portion is unused. The memory partition information may also include a memory partitioning constraint, which includes a start point address for the second repartitioned memory block portion and a number of at least one memory segments to be partitioned in the second repartitioned memory block portion.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: February 19, 2019
    Assignee: Altera Corporation
    Inventors: Kar Liang Oung, Woi Jie Hooi
  • Patent number: 10204028
    Abstract: Errors in software may be detected via the use of design rule spaces and architecture root detection. Design rule spaces may reveal multiple overlapping modular structures of a software system, and reveal structural relations among error-prone files and structural problems contributing to error-proneness. Root detection may extract a few groups of architecturally connected files, which may be connected through problematic architecture relations that propagate errors among these files, and thus influence system error-proneness. The root detector may locate the core architecturally connected file groups that contribute to the error-proneness of a system. The root detection process may, beginning with a set of error-prone files, search and link other files that are architecturally related. The output of the root detection process may be a set of design rule spaces ordered by the number of error-prone contained therein.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: February 12, 2019
    Assignee: Drexel University
    Inventors: Yuanfang Cai, Lu Xiao
  • Patent number: 10198544
    Abstract: A method for improving OpenCL hardware execution efficiency described in this invention comprises the following steps: compiling a kernel implemented in OpenCL, generating Verilog code with a high-level synthesis tool; analyzing the interfaces of auto-generated Verilog code, recording signals, timing sequence, and function of the interfaces; manually modifying and optimizing the Verilog code; inserting a file replacement command in the script responsible for flow control, replacing the auto-generated code with the optimized Verilog code; rerunning OpenCL compiler and generating an ultimate FPGA configuration file. The invention makes manual optimization of the auto-generated Verilog code becomes possible, by parsing the compilation flow of OpenCL environment and analyzing the structure and interfaces of the auto-generated Verilog code.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: February 5, 2019
    Assignee: HANGZHOU FLYSLICE TECHNOLOGIES CO., LTD.
    Inventors: Ailian Cheng, Wenhua Wang
  • Patent number: 10181003
    Abstract: Devices, systems, and methods are disclosed that are configured to execute functions using synthesized parallel stateless asynchronous flowcharts. The flowcharts include one or more test objects, action objects, and/or task objects. Each of the objects in the flowcharts to be executed sets out an atomic path, which is a sequence of functions with one or more elements. The disclosed processing circuits are configured to execute the functions/instructions set forth in the flowcharts by following each atomic path. In some embodiments, the processing circuits execute the one or more flowcharts in an order determined during processing (i.e., “on the fly”). In these and other embodiments, the disclosed processing circuits transform or restore elements of the one or more flowcharts with or without human intervention.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: January 15, 2019
    Assignee: YOU KNOW SOLUTIONS, LLC
    Inventors: Ronald J. Lavallee, Thomas C. Peacock
  • Patent number: 10176160
    Abstract: Converting data transformations entered in a spreadsheet program into a circuit representation of those transformations. The circuit representation can run independently of the spreadsheet program to transform input data into output data. In some cases the circuit representation is in the form of hardware, accepts and/or produces data streams, and/or the circuit and/or output data or data streams can be shared among multiple users and/or subscribers. Where data streams are processed, the transformations may include well-specified timing semantics, supporting operations that involve rate-based rate manipulation, value-based rate manipulation, and/or access to past cell values.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: January 8, 2019
    Assignee: International Business Machines Corporation
    Inventors: Martin J. Hirzel, Rodric Rabbah, Philippe Suter, Olivier L. J. Tardieu, Mandana Vaziri
  • Patent number: 10169513
    Abstract: According to one embodiment, a source code is parsed to identify a first routine to perform a first function and a second routine to perform a second function. A control signaling topology is determined between the first routine and the second routine based on one or more statements associated with the first routine and the second routine defined in the source code. A first logic block is allocated describing a first hardware configuration representing the first function of the first routine. A second logic block is allocated describing a second hardware configuration representing the second function of the second routine. A register-transfer level (RTL) netlist is generated based on the first logic block and the second logic block. The second logic block is to perform the second function dependent upon the first function performed by the first logic block based on the control signaling topology.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: January 1, 2019
    Assignee: BAIDU USA LLC
    Inventors: Davy Huang, Jia Feng, Hassan Kianinejad, Yanyan Zhang, Manjiang Zhang
  • Patent number: 10164596
    Abstract: Switchable and/or tunable filters, methods of manufacture and design structures are disclosed herein. The method of forming the filters includes forming at least one piezoelectric filter structure comprising a plurality of electrodes formed to be in contact with at least one piezoelectric substrate. The method further includes forming a micro-electro-mechanical structure (MEMS) comprising a MEMS beam in which, upon actuation, the MEMS beam will turn on the at least one piezoelectric filter structure by interleaving electrodes in contact with the piezoelectric substrate or sandwiching the at least one piezoelectric substrate between the electrodes.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: December 25, 2018
    Assignee: SMARTSENS TECHNOLOGY (CAYMAN) CO., LTD.
    Inventors: James W. Adkisson, Panglijen Candra, Thomas J. Dunbar, Mark D. Jaffe, Anthony K. Stamper, Randy L. Wolf
  • Patent number: 10164597
    Abstract: Switchable and/or tunable filters, methods of manufacture and design structures are disclosed herein. The method of forming the filters includes forming at least one piezoelectric filter structure comprising a plurality of electrodes formed to be in contact with at least one piezoelectric substrate. The method further includes forming a micro-electro-mechanical structure (MEMS) comprising a MEMS beam in which, upon actuation, the MEMS beam will turn on the at least one piezoelectric filter structure by interleaving electrodes in contact with the piezoelectric substrate or sandwiching the at least one piezoelectric substrate between the electrodes.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: December 25, 2018
    Assignee: SMARTSENS TECHNOLOGY (CAYMAN) CO., LTD.
    Inventors: James W. Adkisson, Panglijen Candra, Thomas J. Dunbar, Mark D. Jaffe, Anthony K. Stamper, Randy L. Wolf
  • Patent number: 10157250
    Abstract: In one embodiment, a tangible, non-transitory, computer-readable medium, includes instructions to receive a first circuit design, determine one or more variations of the first circuit design using register retiming with speculative circuit design changes, determine one or more performance improvements of the variations when fed clock signals over the first circuit design, determine one or more tradeoffs of the one or more variations of the first circuit design in comparison to the first circuit design, display a summary of the one or more variations of the first circuit design, the one or more performance improvements, and the one or more tradeoffs, and provide a user-selectable user interface element to enable selection of the first circuit design, at least one of the one or more variations of the first circuit design, or a combination thereof.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: December 18, 2018
    Assignee: ALTERA CORPORATION
    Inventors: Benjamin Michael Joshua Gamsa, Gordon Raymond Chiu
  • Patent number: 10152565
    Abstract: Circuit design computing equipment may perform register retiming operations to improve the performance of a circuit design after having performed placement and routing operations. For example, the circuit design computing equipment may perform register retiming operations that move registers from a first portion of a circuit design that operates in a first clock domain into a synchronization region that separates the first portion of the circuit design from a second portion of the circuit design that operates in a second clock domain that is different than the first clock domain. Performing register retiming operations that move registers into a synchronization region between clock domains may solve the so-called short path—long path problem in which a long path that would benefit from a register retiming operation is coupled in parallel to a short path that has no location to receive a register during the register retiming operation.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: December 11, 2018
    Assignee: Altera Corporation
    Inventors: Benjamin Gamsa, Gordon Raymond Chiu
  • Patent number: 10120968
    Abstract: The present disclosure relates to defining and processing hardware description language (HDL) groups. Embodiments may include mapping, using a processor, a set of tool-specific objects into a group graph with one or more groups. Embodiments may also include generating a search order associated with each group. The search order associated with each group may be based upon the hierarchical design configuration of the group graph. Embodiments may further include identifying undefined references from within a first group within the group graph and binding defined references from within the first group to electronic circuit design components. Embodiments may include identifying the undefined references from within a second group within the group graph. The second group may be selected based upon the undefined references and the search order associated with the first group.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: November 6, 2018
    Assignee: Cadence Design Systems, Inc.
    Inventors: Dan Richard Kaiser, Jonathan Lee DeKock, Steven Guy Esposito
  • Patent number: 10120969
    Abstract: Systems and methods for generating and deploying integrated circuit (IC) applications are provided. Global variable implementation logic may be used to optimize implementation, on an integrated circuit, of functionality represented by high-level code including global variables. A compiler's intermediate representation is analyzed for one or more characteristics that may be used to determine one or more initialization parameters, one or more scope parameters, one or more implementation parameters, or any combination thereof of the functionality. An HDL is generated based upon the one or more initialization parameters, the one or more scope parameters, the one or more implementation parameters, or the any combination thereof.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: November 6, 2018
    Assignee: Altera Corporation
    Inventors: Byron Sinclair, Andrew Chaang Ling, John Stuart Freeman
  • Patent number: 10114917
    Abstract: Systems and methods automatically generate code from an executable model. The code may be generated from one or more in-memory representations constructed for the model. The in-memory representations may be analyzed, and portions that can be mapped to DSP slices of a programmable logic device may be identified. The portions may be modified based on information for a particular programmable logic device, such as the structure of the device's DSP slices. The modifications may ensure that elements of the generated code get mapped to DSP slices, when the generated code is used to synthesize the programmable logic device.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: October 30, 2018
    Assignee: The MathWorks, Inc.
    Inventors: Girish Venkataramani, Purshottam Vishwakarma, Rama Kokku
  • Patent number: 10095822
    Abstract: In one aspect, electronic design automation systems, methods, and non-transitory computer readable media are presented for adding a memory built-in self-test (MBIST) logic at register transfer level (RTL) or at netlist level into an integrated circuit (IC) design. In some embodiments, the MBIST logic is coupled to a physical memory module via a logical boundary of an intermediate level module that contains the physical memory module. The MBIST logic helps to keep intact integrity of the intermediate level module, making it more likely to meet any specified performance of the intermediate level module and reduce area overhead.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: October 9, 2018
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Navneet Kaushik, Puneet Arora, Steven Lee Gregor, Norman Card
  • Patent number: 10073795
    Abstract: In a system and method for emulating a circuit design, an emulation system receives input instructions from a host device executing the emulation and returns test results and trace data. Channels of multiple buffers and associated processors implement the test operations. Compression units on each channel may compress the test and trace data to facilitate returning the results to the host device. Multiple channels may be used to compress data in parallel, thereby improving throughput.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: September 11, 2018
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventor: Mitchell Grant Poplack
  • Patent number: 10073701
    Abstract: Systems and methods for implementing a scalable very-large-scale integration (VLSI) architecture to perform compressive sensing (CS) hardware reconstruction for data signals in accordance with embodiments of the invention are disclosed. The VLSI architecture is optimized for CS signal reconstruction by implementing a reformulation of the orthogonal matching pursuit (OMP) process and utilizing architecture resource sharing techniques. Typically, the VLSI architecture is a CS reconstruction engine that includes a vector and scalar computation cores where the cores can be time-multiplexed (via dynamic configuration) to perform each task associated with OMP. The vector core includes configurable processing elements (PEs) connected in parallel. Further, the cores can be linked by data-path memories, where complex data flow of OMP can be customized utilizing local memory controllers synchronized by a top-level finite-state machine.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: September 11, 2018
    Assignee: The Regents of the University of California
    Inventors: Dejan Markovic, Fengbo Ren
  • Patent number: 10055528
    Abstract: Disclosed are methods, systems, and articles of manufacture for implementing engineering change orders (ECOs) with figure groups and virtual hierarchies. These techniques identify a schematic design and a layout having at least one virtual hierarchy of an electronic design. These techniques then implement an ECO to modify at least one layout circuit component design in a figure group, without considering a physical hierarchical structure of the layout. These techniques further check the figure group based in part or in whole upon one or more criteria and update one or more data structures for the at least one virtual hierarchy and the figure group based in part or in whole upon the ECO.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: August 21, 2018
    Assignee: Cadence Design Systems, Inc.
    Inventor: Arnold Ginetti
  • Patent number: 10049337
    Abstract: An architecture for realizing a customer system on a cloud computing platform is defined in terms of a plurality of architecture types, each type (AT) defined by plural architecture type units (ATUs), each ATU comprising a set of ATU Details. The ATU Details are ordered into a series of discrete stages. Maturity of the architecture is determined as a single architecture pulse (AP) numeric value for each architecture type. The pulse reflects the extent to which the ATUs of the architecture type have reached a requisite level of quality, and an extent to which the ATUs are created in a sequence consistent with the series of discrete stages. The AP pulse values may be combined to form a single success platform pulse (SPP) for tracking overall condition of the platform architecture with a single numerical value.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: August 14, 2018
    Assignee: SALESFORCE.COM, INC.
    Inventors: Gerhard Friedrich Mack, Stefan Pühl
  • Patent number: 10041992
    Abstract: The testing and operating of remote devices are discussed. More particularly, signals are generated and/or received by remote devices, analyzed, logged, and displayed. Signals to remote devices are provided. Enhancements to the operability, capabilities, and functionality of such previously available testing equipment, are provided, via the operation of a remote, portable, and lightweight test bed. The test bed is operated and controlled remotely via a user-computing device. The test bed senses, probes, and/or controls a remote device and test data is automatically generated and/or acquired. The test data is provided to the user-computing device for automated analysis, visualization, and test report generation.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: August 7, 2018
    Assignee: AZ, LLC
    Inventor: Sana Rezgui