Design Entry Patents (Class 716/102)
  • Patent number: 10929160
    Abstract: Systems and methods for just-in-time compilation are disclosed. The systems and methods can be used to generate composite blocks, reducing program execution time. The systems and methods can include generating single-trace blocks during program execution. Upon satisfaction of a trigger criterion, single-trace blocks can be selected for compilation into a composite block. The trigger criterion can be a number of executions of a trigger block. Selecting the single-trace blocks can include identifying blocks reachable from the trigger block, selecting a subset of the reachable blocks, and selecting an entry point for the composite block. The composite block can be generated from the single-trace blocks and incorporated into the program control flow, such that the composite block is executed in place of the selected single-trace blocks.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: February 23, 2021
    Assignee: The MathWorks, Inc.
    Inventors: Nikolay Mateev, Ayon Basumallik, Aaditya Kalsi, Prabhakar Kumar
  • Patent number: 10922457
    Abstract: The disclosure describes the implementation of automated techniques for optimizing quantum circuits of the size and type expected in quantum computations that outperform classical computers. The disclosure shows how to handle continuous gate parameters and report a collection of fast algorithms capable of optimizing large-scale-scale quantum circuits. For the suite of benchmarks considered, the techniques described obtain substantial reductions in gate counts. In particular, the techniques in this disclosure provide better optimization in significantly less time than previous approaches, while making minimal structural changes so as to preserve the basic layout of the underlying quantum algorithms.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: February 16, 2021
    Assignees: University of Maryland, IonQ Inc.
    Inventors: Yunseong Nam, Dmitri Maslov, Andrew Childs, Neil Julien Ross, Yuan Su
  • Patent number: 10922469
    Abstract: Embodiments described herein provide a new layout editor tool allowing designers to concurrently edit various aspects of an electronic circuit layout, even at disparate hierarchical levels of the design. The new layout editor tool enables multiple electronic circuit designers to concurrently edit a layout a different hierarchical levels, by logically establishing editable child sub cell-level partitions within a parent layout-level partition, each of which representing various components of the same electronic circuit layout.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: February 16, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Yuan-Kai Pei, Gautam Kumar, Gerard Tarroux
  • Patent number: 10915693
    Abstract: An embodiment herein provides a method for implementing verification IP for pre-silicon functional verification of a layered protocol. The method includes generating serially connected layer blocks. A layer block includes modular components that may be enabled or disabled to change a functionality of the layer block. The modular components include a layer core, a stimulus handler, one or more transmit routers and one or more receive routers. The layer core implements the complete functionality of the layer block. The stimulus handler drives input stimulus transactions into the layer core of the layer block. The one or more transmit routers routes one or more transmit core transactions from the layer core to the connected succeeding layer block. The one or more receive routers routes one or more receive core transactions from the succeeding layer block to the layer core.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: February 9, 2021
    Assignee: SILICONCH SYSTEMS PVT LTD
    Inventors: Kaustubh Kumar, Pavitra Balasubramanian
  • Patent number: 10896272
    Abstract: A high-level synthesis device executes high-level synthesis on a behavioral description including a plurality of loop descriptions and a logical description. An extraction unit extracts loop descriptions that can be merged with the logical description without changing a function, as loop description candidates, from the plurality of loop descriptions. The extraction unit also calculates characteristics of a circuit of a case where the logical description is merged with each of the loop description candidates, as circuit characteristics. A determination unit determines a loop description to be merged with the logical description, from the loop description candidates based on the circuit characteristics. A merge unit merges the logical description with the loop description determined by the determination unit.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: January 19, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Ryo Yamamoto
  • Patent number: 10895871
    Abstract: A method and system for automatically generating interactive wiring diagram in an industrial automation environment are disclosed. The method includes acquiring real-time data associated with devices commissioned in a plant from one or more sensing units disposed at the respective devices. The method also includes determining connections between the devices in the plant based on the acquired real-time data using a lookup table. The method includes generating a wiring diagram of the plant based on the determined connections between the devices. The wiring diagram represents the devices located in the plant and physical connections between the devices. The method includes dynamically generating interactive wiring diagrams by superimposing the wiring diagram with the device connectivity status information associated with respective connections between the devices.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: January 19, 2021
    Assignee: SIEMENS AKTIENGESELLSCHAFT
    Inventor: Mahantesh Ganachari
  • Patent number: 10885249
    Abstract: A system to develop an integrated circuit includes a child placement module that places in a parent macro a child macro that contains therein a child logic circuit component. The parent macro has a first hierarchical level assigned thereto and the child macro has a lower second hierarchical level assigned thereto. The system further includes a timing analysis module and a component targeting module. The timing analysis module detects a timing fault in response to performing a first parent-level optimization process on the parent macro. The component targeting module extracts from the child macro a targeted logic circuit component and places the targeted logic circuit component in the parent macro. The timing analysis module performs a second parent-level optimization process on the parent macro that resolves the timing fault based on the placement of the targeted logic circuit component in the parent macro.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: January 5, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nany Kollesar, Shawn Kollesar
  • Patent number: 10872186
    Abstract: Embodiments are directed towards a method to create a reconfigurable interconnect framework in an integrated circuit. The method includes accessing a configuration template directed toward the reconfigurable interconnect framework, editing parameters of the configuration template, functionally combining the configuration template with a plurality of modules from an IP library to produce a register transfer level (RTL) circuit model, generating at least one automated test-bench function, and generating at least one logic synthesis script. Editing parameters of the configuration template includes confirming a first number of output ports of a reconfigurable stream switch and confirming a second number of input ports of the reconfigurable stream switch. Each output port and each input port has a respective architectural composition. The output port architectural composition is defined by a plurality of N data paths including A data outputs and B control outputs.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: December 22, 2020
    Assignees: STMICROELECTRONICS S.R.L., STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Thomas Boesch, Giuseppe Desoli
  • Patent number: 10867091
    Abstract: A method of optimizing a power consumption of an integrated circuit design, includes dividing the integrated circuit design into N circuit partitions, supplying each circuit partition to a different one of N computer systems each associated with a different one of the N circuit partitions, training each of the N computer systems to reduce the power consumption of its associated circuit partition thereby to generate N training data, storing the N training data in a database, and applying the N training data to the integrated circuit design thereby to reduce the consumption of the integrated circuit design.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: December 15, 2020
    Assignee: Synopsys, Inc.
    Inventors: Nahmsuk Oh, Antun Domic
  • Patent number: 10846456
    Abstract: A method of generating a netlist of an IC device includes extracting dimensions of a gate region of the IC device, the dimensions including a width of the gate region, the width extending at least from a first edge of an active region to a second edge of the active region, and a distance from a first end of the width to a gate via positioned along the width. A first gate resistance value corresponding to the gate region is received, a second gate resistance value is determined based on the distance and the width, and the netlist is updated based on the first and second gate resistance values.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: November 24, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ke-Ying Su, Jon-Hsu Ho, Ke-Wei Su, Liang-Yi Chen, Wen-Hsing Hsieh, Wen-Koi Lai, Keng-Hua Kuo, KuoPei Lu, Lester Chang, Ze-Ming Wu
  • Patent number: 10846450
    Abstract: Described herein are a processor and a method of operating the processor to simulate a many-core target machine. The processor includes a plurality of processing cores arranged in a predetermined manner and a global target clock counter (GTCC) configured to count a number of simulated clock cycles in the target machine. A global stall controller (GSC) configured to halt execution of all the processing cores based on a determination of at least one processing core being in a fault condition; and wherein the processor acquires a base clock per instruction (CPI) of a target machine, the CPI corresponding to an average number of clock cycles required by the target machine to execute a single instruction, translates an application of the target machine to a compact executable trace to be executed by the processor, and adjusts a speed of simulation by adjusting an update rate of the global target clock counter.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: November 24, 2020
    Assignee: KING FAHD UNIVERSITY OF PETROLEUM AND MINERALS
    Inventors: Muhammad Elnasir Elrabaa, Ayman Ali Hroub
  • Patent number: 10839132
    Abstract: Cover points are automatically generated based on analysis of the hardware design represented in register transfer level (RTL) of a hardware description language. A cover point generator uses uncertainty of event occurrence, critical point analysis and redundancy elimination to determine consequential cover points for function verification. A user may provide input parameters to the cover point generator to define depth and width of cover events for generating cover points.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: November 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kousik Dan, Sandeep Korrapati
  • Patent number: 10831970
    Abstract: Techniques for generating a layout of a multi-port memory cell are provided. A specification describing at least on port within a memory cell is defined. A base memory cell including at least one extension point is modeled. A port that interfaces with the base memory cell is identified from the specification. An electrical interface between the identified port and an extension point of the base memory cell is modeled. In some embodiments, a design bucket is selected from among a predefined set of design buckets based on a count of ports within the memory cell, as described by the specification. Each design bucket corresponding to a respective layout template including the base memory cell and a respective maximum count of ports. Each electrical interface including a port described in the specification of the memory cell is modeled based on the selected design bucket and the respective layout template.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Rolf Sautter, Amira Rozenfeld, Shankar Kalyanasundaram, Ananth Nag Raja Darla, Rajesh Veerabhadraiah
  • Patent number: 10831959
    Abstract: An advanced timing mode has a path that originates from a host application-specific integrated circuit (ASIC) and terminates at a register inside an embedded field programmable gate array (FPGA), bypassing interface cluster registers. The terminating register may be present at a boundary between the host ASIC and the embedded FPGA or deep inside the embedded FPGA. In a clock trunk input with internal divergence timing scenario, a clock output from a phase-locked loop (PLL) in the host ASIC is driven through a clock trunk into the embedded FPGA and, from there, diverges into interface cluster registers and the boundary adjacent to the host ASIC. A clock trunk input with external divergence timing scenario is similar to the internal divergence scenario except that a clock divergence occurs before the clock enters a clock trunk of the embedded FPGA. In a boundary clock input scenario, a PLL drives both the host ASIC and the embedded FPGA interface clusters.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: November 10, 2020
    Assignee: Achronix Semiconductor Corporation
    Inventors: Namit Varma, Shirish Jawale
  • Patent number: 10816957
    Abstract: Disclosed is a method of integrating changes to a computer aided manufacturing software application file for a manufactured component comprising the steps of: obtaining a first computer aided design file for the manufactured component; displaying a first solid model of the manufactured component; obtaining a second computer aided design file for a revised version; displaying a second solid model of the revised version of the manufactured component; and matching at least one face on the second solid model to at least one face on the first solid model.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: October 27, 2020
    Inventor: Robert Kirkwood
  • Patent number: 10810342
    Abstract: Capturing and processing a digital image of a pictorial (e.g., hand-drawn) representation of a schematic or block diagram as a digital image to aid in creation and maintenance of electrical designs is disclosed. Processing of the digital image includes processing to determine design parameters to create an informational format useful as input to other design software. Design parameters may include schematic layout and attributes such as maximum output voltage, minimum input voltage, ambient temperature, etc. The method and system also include storage of information accessible to refine designs and perform simulations of designs as part of an overall electrical design process. Associated devices and methods are disclosed as well.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: October 20, 2020
    Assignee: Texas Instruments Incorporated
    Inventor: Malcolm James Humphrey
  • Patent number: 10810336
    Abstract: Described is a method comprising a processing, an establishing, and/or a determining. In the processing, an inputted capabilities list including one or more hardware design capabilities may be processed. In the establishing, one or more candidate components for the one or more hardware design capabilities may be established. In the determining, a set of unique candidate netlists capable of satisfying the one or more hardware design capabilities may be determined, the set of unique candidate netlists being based upon the set of candidate components.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: October 20, 2020
    Assignee: zGlue, Inc.
    Inventors: Danielle Morton, Rick Yan
  • Patent number: 10803228
    Abstract: An embodiment herein provides a method for implementing verification IP for pre-silicon functional verification of a layered protocol. The method includes generating serially connected layer blocks. A layer block includes modular components that may be enabled or disabled to change a functionality of the layer block. The modular components include a layer core, a stimulus handler, one or more transmit routers and one or more receive routers. The layer core implements the complete functionality of the layer block. The stimulus handler drives input stimulus transactions into the layer core of the layer block. The one or more transmit routers routes one or more transmit core transactions from the layer core to the connected succeeding layer block. The one or more receive routers routes one or more receive core transactions from the succeeding layer block to the layer core.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: October 13, 2020
    Assignee: SILICONCH SYSTEMS PVT LTD
    Inventors: Kaustubh Kumar, Pavitra Balasubramanian
  • Patent number: 10802408
    Abstract: A method for improving the yield of a lithographic process, the method including: determining a parameter fingerprint of a performance parameter across a substrate, the parameter fingerprint including information relating to uncertainty in the performance parameter; determining a process window fingerprint of the performance parameter across the substrate, the process window being associated with an allowable range of the performance parameter; and determining a probability metric associated with the probability of the performance parameter being outside an allowable range. Optionally a correction to the lithographic process is determined based on the probability metric.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: October 13, 2020
    Assignee: ASML Netherlands B.V.
    Inventors: Everhardus Cornelis Mos, Jochem Sebastiaan Wildenberg, Erik Johannes Maria Wallerbos, Maurits Van Der Schaar, Frank Staals, Franciscus Hendricus Arnoldus Elich
  • Patent number: 10796044
    Abstract: This application discloses a computing system implementing a schematic capture tool to place and connect parts in a schematic design of a printed circuit board assembly. The computing system implementing the schematic capture tool can select a type of communication interface to connect the parts in the schematic design and identify an interface definition that corresponds to the selected type of communication interface. The schematic capture tool can locate a mapping that describes connectivity between the parts and the interface definition, and automatically modify the schematic design to include an instance of the interface definition in the schematic design and connect the parts in the schematic design to the instance of the interface definition based on the mapping. The schematic capture tool also can utilize the interface definition to set constraints for or add terminations to the connection between the parts in the schematic design.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: October 6, 2020
    Assignee: Mentor Graphics Corporation
    Inventors: Michał Paszek, Tomasz Zielski, Michał Ferdek, Pawel Cieslak, Marek Mossakowski
  • Patent number: 10796051
    Abstract: In the described examples, a model impact monitor can include an electronic design automation (EDA) manager that communicates with a plurality of EDA programs, wherein each EDA program generates a model set for a register-transfer level (RTL) design comprising a list of RTL operations. The model impact monitor can also include an adaptive model interface that records changes to the RTL operations of the RTL design and measures a change in performance characteristics of each of the plurality of EDA programs based on a respective one of the changes in the RTL operations of the RTL design.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: October 6, 2020
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Abner Luis Panho Marciano, Matheus Fonseca, Thamara Karen Cunha Andrade, Raquel Lara dos Santos Pereira, Fabiano Cruz Peixoto, Rodolfo Santos Teixeira, Rafael Gontijo Hamdan, Bruno Andrade Pereira
  • Patent number: 10796062
    Abstract: The independent claims of this patent signify a concise description of embodiments. Embodiments described herein are directed to a database-driven scheme for automating the process of VDRC checking in a full-custom EDA Design and Implementation tool.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: October 6, 2020
    Assignee: SYNOPSYS, INC.
    Inventors: Nabil Yazdani, Donald Oriordan, Jingyu Xu, Bulent Basaran, Larissa Nitchougovskaia
  • Patent number: 10754622
    Abstract: A workflow extraction method, system, and computer program product include analyzing, for each of the design screens, a relatability of one design screen to a previously analyzed design screen in the database and generating a tag that represents a workflow and creating a database linking the tag to a sequence of design screens from a transition graph that details how to move from one of the design screens to another.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: August 25, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kyungmin Lee, David M. Lubensky, Marco Pistoia, Stephen Wood
  • Patent number: 10747927
    Abstract: A method may designing electronic circuits is provided. The method may include generating a first user interface for displaying, at a client, a plurality of graphical elements for creating a state diagram. A scaffold may be added to the state diagram in response to the scaffold being selected from the plurality of graphical elements. A first state bubble may be attached to the scaffold in response to the first state bubble being selected from the plurality of graphical elements. A dimension of the scaffold and/or a position of the first state bubble on the scaffold may be adjusted in response to a second state bubble being added and/or removed from the state diagram. A second user interface may be generated for displaying, at the client, the state diagram. Related systems and articles of manufacture, including computer program products, are also provided.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: August 18, 2020
    Assignee: STARSYSTEMS, INC.
    Inventor: Fletcher McBeth
  • Patent number: 10725104
    Abstract: Disclosed is an apparatus including a datapath and a test circuit. The datapath is configured to transfer data between a memory core and an IO interface. The datapath includes a plurality of circuits, and a memory core interface. The plurality of circuits operates according to a supply voltage. The test circuit is coupled to the datapath, and configured to determine, from a set of operable voltage levels of the supply voltage, a first minimum operable voltage level for the datapath to operate for the data traversing the datapath at a first frequency.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: July 28, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Amandeep Kaur, Sridhar Yadala, Jayanth Mysore Thimmaiah, Ravindra Arjun Madpur
  • Patent number: 10726180
    Abstract: A computer executable processing component analyzes unknown (X) propagation from uninitialized latches in gate-level simulation and determines if the Xs cause false Xs to be generated due to X-pessimism. For Xs generated due to X-pessimism, simulation results are corrected and fixes are generated. Corrected simulation results match real hardware behavior and greatly reduces engineers' analysis effort on debugging X issues. A computer executable processing component analyzes unknown (X) propagation from sequential cells in gate-level logic simulation and determines if the Xs cause false Xs to be generated due to X-pessimism. For Xs generated due to X-pessimism, simulation results are corrected and fixes are generated. Corrected simulation results match real hardware behavior and greatly reduces engineers' analysis effort on debugging X issues.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: July 28, 2020
    Assignee: Avery Design Systems, Inc.
    Inventors: Kai-Hui Chang, Andrew Stein, Hong-zu Chou, Christopher S. Browy, Chi-Lai Huang
  • Patent number: 10719648
    Abstract: A method is disclosed that includes providing an IP bank, an application bank, and a technology bank; generating a hierarchical table based on the IP bank and the application bank; performing an estimation of at least one of a performance value, a power value, an area value and a cost value, which corresponds to the hierarchical table, by using the technology bank, to output an result data as a basis of fabrication of a system.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: July 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tze-Chiang Huang, Kai-Yuan Ting, Sandeep Kumar Goel, Yun-Han Lee, Shereef Shehata, Mei Wong
  • Patent number: 10713403
    Abstract: Apparatus and associated methods relate to controlling synthesis of an electronic design by tagging an intellectual property (IP) parameter such that changes to the tagged design parameter do not result in the entire electronic design being re-synthesized. In an illustrative example, a circuit may contain a number of hard blocks, which may be configured using an HDL design tool. Whenever an IP parameter of an HDL design is updated, place and route may go out of date, which may require the entire design to be re-synthesized. By tagging certain IP parameters with at least one tag, changes or alterations to these tagged IP parameters will not cause synthesis to occur (for output products associated with the at least one tag). Avoiding re-synthesis may save significant time for designers by performing re-synthesis only when necessary.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: July 14, 2020
    Assignee: XILINX, INC.
    Inventors: Shreegopal S. Agrawal, Jaipal R. Nareddy, Suman Kumar Timmireddy, Benjamin D. Curry, Siddharth Rele, Sozon Panou
  • Patent number: 10671792
    Abstract: Identifying and resolving issues with placement of plated through vias in voltage divider regions of a printed circuit board (“PCB”) layout. Search parameters indicate an area of the PCB layout to be analyzed, and vias meeting the search parameters are evaluated for placement issues. Upon detecting a placement issue for a via, a solution is determined that addresses and resolves the placement issue of the via. The resolution in an embodiment includes modifying an adjacent power shape, modifying a region between shapes, and/or modifying via placement to minimize risks that include potential shorting, partially-connected vias, and/or poor plated barrel adhesion.
    Type: Grant
    Filed: July 29, 2018
    Date of Patent: June 2, 2020
    Assignee: International Business Machines Corporation
    Inventors: Michael A. Christo, David L. Green, Julio A. Maldonado, Diana D. Zurovetz
  • Patent number: 10671395
    Abstract: The invention provides an application specific instruction set processor (ASIP) that uses a Very Long Instruction Word (VLIW) for simultaneously executing a plurality of operations. For simultaneously executing the plurality of operations, the ASIP processor comprises a fetching unit to fetch a long instruction word from an instruction memory unit and an instruction decoder unit that interfaces with the fetching unit and a program address counter. The instruction decoder unit decodes the long instruction word fetched from the instruction memory unit and enables a plurality of sub blocks responsible for execution of a plurality of simultaneous independent operations. The instruction decoder unit of the ASIP is capable of decoding a 32-bit instruction word and executing up to six simultaneous independent operations.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: June 2, 2020
    Assignee: The King Abdulaziz City for Science and Technology—KACST
    Inventors: Mohammed S BenSaleh, Abdulfattah M Obeid, Yousef A Alzahrani, Ahmed F Shalash, Hossam A Fahmy, Hossam A Sayed, Mohamed A Aly
  • Patent number: 10664563
    Abstract: A verification system comprises: a reconfigurable hardware modeling device programmed to implement a hardware model of a circuit design; a first computing unit configured to execute a first software program; and a second computing unit configured to execute a testbench model of a second software program. The execution of the first software program and the testbench model of the second software program generates first stimuli and second stimuli for an operation of the hardware model of the circuit design, respectively. The first stimuli and the second stimuli are transmitted to the hardware model of the circuit design through a communication interface.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: May 26, 2020
    Assignee: Mentor Graphics Corporation
    Inventors: Debdutta Bhattacharya, Ayub Akbar Khan, Charles W. Selvidge
  • Patent number: 10664377
    Abstract: Systems, methods, and software can be used to automate software verifications. In some aspects, one or more application program interface (API) call pairs are generated based on a source code of a user module that invokes an API. Each of the one or more API call pairs comprises a first API call that invokes the API followed by a second API call that invokes the API. One or more fragments are generated based on the one or more API calls pairs. Each of the one or more fragments represents an execution sequence that includes at least one of the one or more API call pairs. The one or more fragments are verified.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: May 26, 2020
    Assignee: BlackBerry Limited
    Inventors: Andrew James Malton, Daniel Lewis Neville
  • Patent number: 10628545
    Abstract: Systems and techniques are described for providing guidance to an equivalence checker when a design contains retimed registers. Some embodiments can perform at least a register retiming optimization on a first design to obtain a second design. Next, the embodiments can determine one or more codes to provide guidance for connecting the set/clear inputs of the retimed registers. The first design, the second design, and the one or more codes can then be provided to an equivalence checker, wherein providing the one or more codes to the equivalence checker reduces an amount of computation required by the equivalence checker to determine functional equivalence between the first design and the second design.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: April 21, 2020
    Assignee: Synopsys, Inc.
    Inventors: Muzaffer Hiraoglu, Darren Charles Cronquist, Peter Wilhelm Joseph Zepter, Navneet Kakkar, Sridhar Keladi
  • Patent number: 10628548
    Abstract: A system for verifying networking system-on-chip designs comprises a reconfigurable hardware modeling device programmed to implement circuitry hardware models and a traffic generation device communicating with the reconfigurable hardware modeling device. The circuitry hardware models comprise a hardware model of a circuit design and a hardware model of interface circuitry. The system employs a backpressure flow control independent of the communication protocol, which can cause the traffic generation device to suspend sending messages when one or more message buffers in the traffic generation device, the reconfigurable hardware modeling device, or both cannot accept more messages based on predetermined conditions.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: April 21, 2020
    Assignee: Mentor Graphics Corporation
    Inventors: Suresh Krishnamurthy, Deepak Kumar Garg, Ankit Garg, Saurabh Khaitan, Sanjay Gupta, John R. Stickley, Russell Elias Vreeland, III, Ronald James Squiers
  • Patent number: 10621299
    Abstract: Providing dynamic platform support for a programmable integrated circuit (IC) can include loading a circuit design for a programmable IC, wherein the circuit design specifies a link region coupled to a first infrastructure region by first connections, and a kernel region coupled to the first infrastructure region by second connections and generating a base platform from the circuit design by removing the first infrastructure region, the kernel region, and the second connections from the circuit design and adding a wrapper that includes the first connections. A new platform can be generated from the base platform where the new platform includes the link region and, within the wrapper, a second infrastructure region coupled to the link region by the first connections.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: April 14, 2020
    Assignee: XILINX, INC.
    Inventors: Hao Yu, Raymond Kong, Brian Martin, Jun Liu, Kevin Beazley
  • Patent number: 10611090
    Abstract: A computer-implemented layout tool includes a mechanical design engine for configuring mechanical design components to be included in a design, an electrical design engine for configuring electrical components to be included in the design, a constraint engine for identifying a three-dimensional (3D) printer to be used to print the design and to provide design constraints including feedback for inoperative or impermissible configurations of one or more mechanical components or electrical pathways associated with the design; and a simulation engine for simulating, at least, electrical performance of the design based on one or more electrical components added to the design after printing and proposed electrical pathways.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: April 7, 2020
    Assignee: Autodesk, Inc.
    Inventor: Karl Willis
  • Patent number: 10606972
    Abstract: A design method including a high level synthesis process that has (1) generating a hardware description of a circuit and high level synthesis report information from a source code based on a high level synthesis constraint, the hardware description describing a circuit including a plurality of stages and inter-stage registers; (2) determining a bypass stage selection pattern based on bypass constraint information including a constraint condition related to a bypass of the inter-stage register and the high level synthesis report information, the bypass stage selection pattern including a plurality of patterns each pattern having a combination of stages of inter-stage registers for which bypass setting is performed among stages of a bypass setting-capable inter-stage registers; and (3) generating bypass report information based on the bypass stage selection pattern, the bypass report information including combination information of the inter-stage registers for which the bypass is performed setting correspondin
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: March 31, 2020
    Assignee: SOCIONEXT INC.
    Inventor: Atsushi Yasunaka
  • Patent number: 10599802
    Abstract: An apparatus for IC design includes a memory configured to store an original Register Transfer Level (RTL) model, a corrected RTL model, and a translation of the original RTL model into a netlist. A processor is configured to identify in the original RTL model a flip-flop having a next-state function that is not equivalent to a corresponding next-state function of a corresponding flip-flop in the Corrected RTL model, to find a wire, which is the earliest ancestor of the flip-flop for which there is no equivalence between the original RTL model and the corrected RTL model, to check whether the wire has an equivalent net in the netlist, to identify, upon finding that the wire has no equivalent net, one or more ancestors of the wire, which do have equivalent nets in the netlist, and to modify the netlist to match the corrected RTL model.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: March 24, 2020
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Or Davidi, Roy Armoni
  • Patent number: 10592623
    Abstract: This application discloses a computing system to check and generate an assertion statement. The assertion statement, when executed during a simulation of a circuit design, can verify a simulated behavior of the circuit design. The computing system can extract sequence items from the assertion statement, and generate a state representation for the sequence items based on the simulated behavior of the circuit design. The state representation can identify states of the extracted sequence items at different clock ticks of the simulation. The computing system can locate an error in the assertion statement based on the state representation by generating patterns from sequence operators in the assertion statement and comparing the patterns to the state representation. The computing system can utilize the error in the assertion statement to generate a corrected assertion statement.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: March 17, 2020
    Assignee: Mentor Graphics Corporation
    Inventors: Moaz Magdy Mustafa, Mona Safar, Mohamed Dessouky
  • Patent number: 10592631
    Abstract: Disclosed is a method for performing netlist comparison based on a pin connection relationship of a component, comprising the steps: acquiring a schematic diagram netlist file generated by a schematic diagram, and acquiring a PCB netlist file generated by a PCB; reading a network in the schematic diagram netlist file, forming a netlist connection relationship corresponding to each network into a schematic diagram array, all schematic diagram arrays forming a schematic diagram array set; reading a network in the PCB netlist file, forming a netlist connection relationship corresponding to each network into a PCB array, all PCB arrays forming a PCB array set; and comparing the schematic diagram array set with the PCB array set, and outputting differences between the two array sets. The present disclosure merely compares the connection relationship of components.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: March 17, 2020
    Assignees: Guangzhou Fastprint Circuit Tech Co., Ltd., Shenzhen Fastprint Circuit Tech Co., Ltd.
    Inventors: Zhirui Liu, Zhongyu Mao
  • Patent number: 10586004
    Abstract: A method for designing a system on a target device includes performing one of synthesis, placement, and routing on the system. A designer is presented with a timing analysis of the system after one of the synthesis, placement, and routing, wherein the timing analysis reflects register retiming optimizations predicted to be implemented on the system. One of the synthesis, placement, and routing is modified in response to input provided by the designer after the presenting.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: March 10, 2020
    Assignee: Altera Corporation
    Inventors: Nishanth Sinnadurai, Benjamin Gamsa
  • Patent number: 10558773
    Abstract: A method, system, and computer program product provide the ability to simulate an electronic circuit. An analog model represents an analog circuit and is wrapped to serve as a module in an event based simulator. The module has a first start state and an input (controlled by the event based simulator). Upon a change in a value of the input, the analog model shows a transient behavior. The value of the input is changed to begin simulating the electronic circuit. In response to the changing of the value, if not already cached, the transient behavior is cached with a key consisting of a combination of the first start state and the value of the input. If already cached, the transient behavior is retrieved from the cache. The simulation of the circuit is output based on the cached transient behavior.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: February 11, 2020
    Assignee: AUTODESK, INC.
    Inventor: Karel Bruneel
  • Patent number: 10546087
    Abstract: A method for generating configuration information using a computer aided design (CAD) tool includes a step to receive an intellectual property block. The method also includes a step to receive a configuration and status register (CSR) data file. The configuration and status register data file includes a user selected portion of runtime features from all of the available runtime features of the intellectual property block. The method may also include a step to receive an additional intellectual property block and an additional configuration and status register data file. Based on the two intellectual property blocks and the configuration and status register data files, a consolidated configuration and status register block may be formed. These intellectual property block(s) and configuration status register block(s) are formed on an integrated circuit device.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: January 28, 2020
    Assignee: Altera Corporation
    Inventors: Sze Yin Lee, Arul Paniandi, Chong Tean Chuah, Siew Ling Yeoh, Yun Hui Moh
  • Patent number: 10540253
    Abstract: A system and method to verify software includes a debugger setting a breakpoint in the software. The breakpoint indicates a point at which to pause or stop execution of the software. The method also includes setting one or more anchor points associated with the breakpoint. Each of the one or more anchor points represents another point in the software that must be executed prior to pausing or stopping the execution of the software at the breakpoint.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: January 21, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Xiao Ling Chen, Chuan He, Yan Huang, Jiang Yi Liu, Wei Wu, Jian Xu
  • Patent number: 10541046
    Abstract: Creating genetic devices for use in micro-organisms or other biological systems is described. In an embodiment a computer system receives at a program editor, input specifying a plurality of part designs, at least some of which comprise part properties expressed as logical variables; and the input also specifies constraints on the logical variables. For example, the input is a computer program which specifies constraints on the logical variables which, for example, relate to properties of the DNA sequences such as reactions and biological behaviors. In an example, a compiler resolves the constraints using a database of genetic parts in order to generate candidate parts for the proposed genetic device. In examples the sequences of genetic parts are translated into reactions and simulated using an automated simulator and/or implemented in a living cell or other biological system. In embodiments the compiler also uses a database of reactions.
    Type: Grant
    Filed: September 2, 2009
    Date of Patent: January 21, 2020
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Andrew Nicholas John Brojer Phillips, Michael David Pedersen
  • Patent number: 10515160
    Abstract: Systems and methods are provided for executing a simulation of a physical system that includes a plurality of objects representing physical entities or phenomena. Parameters of objects currently present in a simulation are evaluated. When one of the parameters is in an invalid state, a first multi-layer context menu is provided having multiple selectable options on each layer on a graphical user interface, where a first layer includes a highlight indicating that an object needs fixed, and where a subsequent layer includes a highlight indicating an identity of the object that needs fixed. The objects currently present in the simulation are evaluated based on a task to be performed. When a required object for the task to be performed is missing from the simulation, a second multi-layer context menu having multiple selectable options on each layer is provided.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: December 24, 2019
    Assignee: Ansys, Inc.
    Inventor: Glyn Jarvis
  • Patent number: 10509658
    Abstract: A system, method, and computer program product are provided for simultaneously determining settings for a plurality of parameter variations. In use, a plurality of parameter variations associated with a device is identified. Additionally, settings for each of the plurality of parameter variations are determined simultaneously.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: December 17, 2019
    Assignee: NVIDIA CORPORATION
    Inventors: John F. Spitzer, Rev Lebaredian, Yury Uralsky
  • Patent number: 10496596
    Abstract: The invention provide an application specific instruction-set processor (ASIP) that uses a Very Long Instruction Word (VLIW) for executing atomic application specific instructions. The ASIP includes one or more units for executing a first set of atomic application specific instructions for receiving a first set of data across a plurality of input data ports in a first operation specified in an instruction word. Further, the one or more units execute a second set of atomic application specific instructions for outputting a second set of data across a plurality of output data ports in a second operation specified in the instruction word, wherein an input data port of the plurality of input data ports and a corresponding output data port of the plurality of output data ports share a same address location and are specified as operands in the instruction word. Thus, the first operation and the second operation can occur simultaneously.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: December 3, 2019
    Assignee: KING ABDULAZIZ CITY FOR SCIENCE AND TECHNOLOGY
    Inventors: Mohammed S BenSaleh, Abdulfattah M Obeid, Yousef A Alzahrani, Ahmed F Shalash, Hossam A Fahmy, Hossam A Sayed, Mohamed A Aly
  • Patent number: 10481929
    Abstract: A distributed execution environment can provide access to field-programmable device resources. The field-programmable device resources can be provided in association with one or more instances that are instantiated within the distributed execution environment upon request from a computing system. The computing system can be associated with a customer of the distributed execution environment. The customer can program the field-programmable device resources using designs created by or for the customer.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: November 19, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Paul William Berg, Eden Grail Adogla, Marc John Brooker, John Clark Coonley Duksta, Robert James Hanson, Jamie Hunter
  • Patent number: 10482207
    Abstract: A design verification support apparatus includes, a memory that stores circuit information and test pattern information, and a processor coupled to the memory. The processor performs a process including, acquiring the circuit information and the test pattern information from the memory, calculating a delay time occurring until the first clock signal reaches each of a plurality of memory circuits coupled in series and included in the scan chain from the clock source, based on the circuit information, selecting a first memory circuit whose first output value is to be changed by a shift operation among the plurality of memory circuits, based on the test pattern information at the cycle, and calculating the first output value of the first memory circuit when a second clock signal is supplied to the first memory circuit, the second clock signal being obtained by delaying the first clock signal by a delay time.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: November 19, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Osamu Sugahara