Design Entry Patents (Class 716/102)
  • Patent number: 11403202
    Abstract: This application is directed to a power monitoring system for virtual platform simulation. In one embodiment, a simulation system may comprise a virtual power monitor (VPMON) and a performance simulator. An example VPMON module may include at least a system agent (SA) module to receive virtual platform data from the performance simulator. The SA module may then be further to determine at least one component power model based on the virtual platform data, and may proceed to formulate a platform power model based on the at least one component power model. During simulation of the virtual platform, the SA module may be further to generate power data corresponding to the virtual platform based on the platform power model. For example, the SA module may obtain performance data from the performance simulator, and may provide the performance data to the platform power model to generate the power data.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: August 2, 2022
    Assignee: Intel Corporation
    Inventors: Parth Malani, Mangesh Tamhankar
  • Patent number: 11366936
    Abstract: A method of programming a device comprising acquiring configuration data, loading the configuration data onto a programmable device, processing at least a portion of the configuration data through a one way function to form processed configuration data, and configuring at least one configurable module of the programmable device using the processed configuration data from the processing step.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: June 21, 2022
    Assignee: NAGRAVISION S.A.
    Inventors: Andre Kudelski, Nicolas Fischer, Jerome Perrine
  • Patent number: 11341087
    Abstract: A heterogeneous multi-core integrated circuit comprising two or more processors, at least one of the processors being a general purpose CPU and at least one of the processors being a specialized hardware processing engine, the processors being connected by a processor local bus on the integrated circuit, wherein the general purpose CPU is configured to generate a first instruction for an atomic operation to be performed by a second processor, different from the general purpose CPU, the first instruction comprising an address of the second processor and a first command indicating a first action to be executed by the second processor, and transmit the first instruction to the second processor over the processor local bus. The first command may include the first action, or may be a descriptor of the first action or a pointer to where the first action may be found in a memory.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: May 24, 2022
    Assignee: DISPLAYLINK (UK) LIMITED
    Inventors: Robin Alexander Cawley, Colin Skinner, Eric Kenneth Hamaker
  • Patent number: 11327113
    Abstract: One embodiment of the present disclosure describes a memory system that may include one or more memory devices that may store data. The memory devices may receive command signals to access the stored data as a loopback signal. The memory devices may operate in a normal operational mode, a loopback operational mode, a retrieval operational mode, a non-inverting pass-through operational sub-mode, and an inverting pass-through operational sub-mode. The operational modes facilitate the transmission of the loopback signal for the purpose of monitoring of memory device operations. A selective inversion technique, which uses the operational modes, may protect the loopback signal integrity during transmission.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: May 10, 2022
    Assignee: Micron Technology, Inc.
    Inventor: David D. Wilmoth
  • Patent number: 11320886
    Abstract: Methods and apparatus relating to techniques for a dual path sequential element to reduce toggles in data path are described. In an embodiment, switching logic causes signals for a single data path of a processor to be directed to at least two separate data paths. At least one of the two separate data paths is power gated to reduce signal toggles in the at least one data path. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: May 3, 2022
    Assignee: INTEL CORPORATION
    Inventors: Subramaniam Maiyuran, Sanjeev S. Jahagirdar, Kiran C. Veernapu, Eric J. Asperheim, Altug Koker, Balaji Vembu, Joydeep Ray, Abhishek R. Appu
  • Patent number: 11275753
    Abstract: Various systems and methods are provided that display schematics and data associated with the various physical components in the schematics in an interactive user interface. For example, a computing device links data stored in one or more databases with schematics displayed in one or more interactive user interfaces. The computing device parses a digital image that depicts a schematic and identifies text visible in the digital image. Based on the identified text, the computing device recognizes representations of one or more physical components in the schematic and links the representations to data regarding the physical component in one or more databases, such as specification data, historical sensor data of the component, etc. The computing device modifies the digital image such that it becomes interactive and visible in a user interface in a manner that allows the user to select a physical component and view data associated with the selection.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: March 15, 2022
    Assignee: Palantir Technologies Inc.
    Inventors: Daniel Cervelli, David Tobin, Feridun Arda Kara, Trevor Sontag, David Skiff, John Carrino, Allen Chang, John Garrod, Agatha Yu
  • Patent number: 11269668
    Abstract: Computing systems, database systems, and related methods are provided for supporting dynamic validation workflows. One exemplary method involves a server of a database system receiving a graphical representation of a validation process from a client device coupled to a network, converting the graphical representation of the validation process into validation code, and storing the validation code at the database system in association with a database object type. Thereafter, the validation process is performed with respect to an instance of the database object type using the validation code in response to an action with respect to the instance of the database object type in a database of the database system. The action triggering the validation process can be based on user-configurable triggering criteria, and the validation process may generate user-configurable notifications based on one or more field values of the database object instance.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: March 8, 2022
    Assignee: salesforce.com, inc.
    Inventor: Samuel William Bailey
  • Patent number: 11243603
    Abstract: There is provided a method and system (200) for power management of an event-based processing system (100). The system (200) is configured to obtain information representing a history of arrival times of events, wherein the information comprises arrival timestamps of the events. The system (200) is configured to determine a measure for power management based on the timestamps of at least two events represented in the information. The system (200) is also configured to perform power management based on the determined measure.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: February 8, 2022
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Onar Olsen, Per Holmberg
  • Patent number: 11188702
    Abstract: Aspects of the present disclosure address systems and methods for local cluster refinement for integrated circuit (IC) designs using a dynamic weighting scheme. Initial cluster definitions are accessed. The initial cluster definitions define a plurality of clusters where each cluster includes a plurality of pins. Each cluster is evaluated with respect to one or more design rule constraints. Based on the evaluation, clusters are identified from the plurality of clusters. A set of refinement candidates are generated based on the one or more clusters. A scoring function that employs a dynamic weighting scheme is used to determine a refinement quality score for each refinement candidate in the set of candidates and one or more refinement candidates are selected from among the set of refinement candidates based on respective refinement quality scores. A refined clustering solution is generated based on the selected refinement candidates.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: November 30, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Bentian Jiang, Natarajan Viswanathan, William Robert Reece, Zhuo Li
  • Patent number: 11176730
    Abstract: Systems and methods are disclosed for secret sharing for secure collaborative graphical design. Graphical secret shares are generated from a three-dimensional graphical design and distributed to one or more contributor devices. Contributor graphical designs modifying graphical secret shares may be received from contributor devices. Various corresponding and related systems, methods, and software are described.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: November 16, 2021
    Assignee: Desprez, LLC
    Inventor: James L Jacobs, II
  • Patent number: 11157984
    Abstract: Means and a computerized method for recommending items such as books and audio compact disks. For each item, a user profile includes ratings provided by users of the system. Unlike present recommendation systems, the user profiles do not include pre-computed similarity factors measuring similarity between users. Rather, when an advisee requests a recommendation, similarity measures are computed comparing the advisee to other users, and the similarity measures are associated with the other users. A subset of the users is selected, where the subset includes the users most similar to the advisee. A recommendation is made based on the ratings by the members of the selected subset.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: October 26, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ralf Bertram, Gerhard Schrimpf, Hermann Stamm-Wilbrandt
  • Patent number: 11144648
    Abstract: A method and system for evaluating software tools that detect malicious hardware modifications is provided. In one embodiment, among others, a system comprises a computing device and an application. The application causes the computing device to at least receive hardware description language code that represents a circuit design and calculate a signal probability for one or more nodes in the circuit design. The application also causes the computing device to identify one or more rare nodes in the circuit design and generate a Trojan sample population. The application further causes the computing device to generate a feasible Trojan population and generate a Trojan test instance based at least in part on a random selection from the Trojan feasible population. Additionally, the application causes the computing device to generate modified hardware description code from the Trojan test instance.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: October 12, 2021
    Assignee: University of Florida Research Foundation, Inc.
    Inventors: Swarup Bhunia, Jonathan William Cruz, Prabhat Kumar Mishra
  • Patent number: 11132485
    Abstract: A method comprising using at least one hardware processor for: running a Monte Carlo simulation of possible integrated circuit (IC) process variations of each of a plurality of IC cell types, wherein each of the plurality of IC cell types is defined by multiple specific transistors and multiple specific interconnects; based on the results of the Monte Carlo simulation, creating a library of IC cell types and their corresponding behavioral values for each of the possible IC process variations, and storing the library in a non-transient memory; receiving an IC design embodied as a digital file; correlating the received IC design with the library; and predicting a frequency distribution and a power distribution of ICs manufactured according to the IC design.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: September 28, 2021
    Assignee: PROTEANTECS LTD.
    Inventors: Evelyn Landman, Yair Talker, Eyal Fayneh, Yahel David, Shai Cohen, Inbar Weintrob
  • Patent number: 11120541
    Abstract: A determination device that determines quality of target portion based on sensor data obtained by a sensor measuring the target object, includes one or more processors configured to acquire sensor data representing the target portion, acquire information indicating a changed portion, determine whether the target portion includes the changed portion based on acquired information, determine a first label of the target portion represented in the sensor data by using a determination model learned from a training dataset based on training target portions, the first label representing target portion as one of good, defect, and a defect candidate, accept a second label of the target portion input via a user interface when the target portion includes the changed portion or when the first label of the target portion is determined as the defect candidate, and perform quality determination of the target portion based on the first label and/or the second label.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: September 14, 2021
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Kimitake Mizobe, Taro Tanaka, Natsumi Mano, Hiroyuki Masuda
  • Patent number: 11100269
    Abstract: Simulation or calculation to estimate activity per unit in a chip design, combined with estimation of the specific location or region in which the unit logic will be finally placed, provides for calculation of an estimation of the activity distribution within the floorplan. Activity distribution estimation can be performed with fine granularity (at a gate level), at coarse granularity (at a macro level), or at an intermediate granularity (at a network-on-chip unit level). The estimation is displayed, visually, to a user of a design tool. Furthermore, the estimation is used to make manual or automatic optimizations of the floorplan and the location and configuration of units within the floorplan.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: August 24, 2021
    Assignee: ARTERIS, INC.
    Inventors: Jonah Probell, Monica Tang
  • Patent number: 11074381
    Abstract: A hardware design for a main data transformation component is verified. The main data transformation component is representable as a hierarchical set of data transformation components which includes (i) a plurality of leaf data transformation components which do not have children, and (ii) one or more parent data transformation components which each comprise one or more child data transformation components. For each of the plurality of leaf data transformation components, it is verified that an instantiation of the hardware design for the leaf data transformation component generates an expected output transaction in response to each of a plurality of test input transactions. For each of the one or more parent data transformation components, it is formally verified, using a formal verification tool, that an instantiation of an abstracted hardware design for the parent data transformation component generates an expected output transaction in response to each of a plurality of test input transactions.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: July 27, 2021
    Assignee: Imagination Technologies Limited
    Inventor: Sam Elliott
  • Patent number: 11048837
    Abstract: Systems and methods are disclosed for to generation of dynamic design flows for integrated circuits. For example, a method may include accessing a design flow configuration data structure, wherein the design flow configuration data structure is encoded in a tool control language; based on the design flow configuration data structure, selecting multiple flowmodules from a set of flowmodules, wherein each flowmodule provides an application programming interface, in the tool control language, to a respective electronic design automation tool; based on the design flow configuration data structure, generating a design flow as a directed acyclic graph including the selected flowmodules as vertices; and generating an output integrated circuit design data structure, based on one or more input integrated circuit design data structures, using the design flow to control the respective electronic design automation tools of the selected flowmodules.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: June 29, 2021
    Assignee: SiFive, Inc.
    Inventor: Han Chen
  • Patent number: 11030977
    Abstract: A processing system comprises a first IC chip and a second IC chip. The first IC chip comprises first image processing circuitry, first display panel driver circuitry, and first communication circuitry. The first image processing circuitry is configured to generate a first overlay image by overlaying a first partial input image with a first image element based on first partial input image data representing the first partial input image and first image element data representing the first image element. The first display panel driver circuitry is configured to drive a display panel based on the first overlay image. The first communication circuitry is configured to output second image element data representing a second image element to the second IC chip.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: June 8, 2021
    Assignee: Synaptics Incorporated
    Inventors: Akihito Kumamoto, Keiichi Hirano
  • Patent number: 11029964
    Abstract: Approaches for configuring a system-on-chip (SOC) include generating component images for components of the SOC. A first component image is for a platform management controller, a second component image is for programmable logic, and a third component image is for a processor subsystem. The plurality of component images are assembled into a programmable device image, and the programmable device image is input to the platform management controller. The platform management controller is booted from the first component image, the programmable logic is configured with the second component image by the platform management controller in executing the first component image, and the processor subsystem is configured with the third component image by the platform management controller in executing the first component image.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: June 8, 2021
    Assignee: XLNX, INC.
    Inventors: Siddharth Rele, Shreegopal S. Agrawal, Kaustuv Manji, Aditya Chaubal
  • Patent number: 11025491
    Abstract: Systems and methods are described for testing server configuration across a secured network edge. A server administrator submitting configuration instructions from an external network separated from an internal network by a network boundary device may not have adequate access for proper testing. A test platform within the internal network receives, from a management device in the external network, a test request indicating a client characteristic. The test platform generates a data request with origination information for a source of the data request conforming to the indicated client characteristic and transmits the generated data request to a data server within the internal network responsive to receiving the test request from the management device. The test platform then receives a response to the generated data request and provides, to the management device in the external network, a report based on the received response.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: June 1, 2021
    Assignee: Google LLC
    Inventors: Xi Leng, Timothy Olds
  • Patent number: 11003821
    Abstract: The present embodiments relate to static timing analysis (STA) of circuits. The STA can be carried out concurrently for multiple-mode-multiple-corners (MMMC) for circuits including combinational loops. The STA includes determining hard breaking points in the loop associated with each single-mode-single-corner (SMSC) view. The STA also includes merging constraints of all SMSC views to generate a merged set of constraints. The STA includes running MMMC STA for the circuit based on the merged set of constraints. The STA also includes determining a soft breaking point for the loop in the MMMC view for timing propagation and settling. The STA maintains consistency of breaking points across SMSC and MMMC views.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: May 11, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Sri Harsha Pothukuchi, Amit Dhuria
  • Patent number: 10990408
    Abstract: Methods for place-and-route aware data pipelining for an integrated circuit device are provided. In large integrated circuits, the physical distance a data signal must travel between a signal source in a master circuit block partition and a signal destination in a servant circuit block partition can exceed the distance the signal can travel in a single clock cycle. To maintain timing requirements of the integrated circuit, a longest physical distance and signal delay for a datapath between master and servant circuit block partitions can be determined and pipelining registers added. Datapaths of master circuit block partitions further away from the servant circuit block can have more pipelining registers added within the master circuit block than datapaths of master circuit block partitions that are closer to the servant circuit block.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: April 27, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Ron Diamant, Akshay Balasubramanian, Sundeep Amirineni
  • Patent number: 10949585
    Abstract: A system, and corresponding method, is described for using a model to predict the physical behavior of IP from an HDL representation of the IP. The system generated data for training and testing the model by treating the logical parameters and physical parameters subset as one for the IP block. The system digitizes the non-numerical parameters and compresses timing arcs. The system uses the trained model to predict performance, power, and area (PPA) behavior for an IP block directly from the combined vector of logical parameter values and physical parameter values.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: March 16, 2021
    Assignee: ARTERIS, INC.
    Inventor: Benny Winefeld
  • Patent number: 10929160
    Abstract: Systems and methods for just-in-time compilation are disclosed. The systems and methods can be used to generate composite blocks, reducing program execution time. The systems and methods can include generating single-trace blocks during program execution. Upon satisfaction of a trigger criterion, single-trace blocks can be selected for compilation into a composite block. The trigger criterion can be a number of executions of a trigger block. Selecting the single-trace blocks can include identifying blocks reachable from the trigger block, selecting a subset of the reachable blocks, and selecting an entry point for the composite block. The composite block can be generated from the single-trace blocks and incorporated into the program control flow, such that the composite block is executed in place of the selected single-trace blocks.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: February 23, 2021
    Assignee: The MathWorks, Inc.
    Inventors: Nikolay Mateev, Ayon Basumallik, Aaditya Kalsi, Prabhakar Kumar
  • Patent number: 10922469
    Abstract: Embodiments described herein provide a new layout editor tool allowing designers to concurrently edit various aspects of an electronic circuit layout, even at disparate hierarchical levels of the design. The new layout editor tool enables multiple electronic circuit designers to concurrently edit a layout a different hierarchical levels, by logically establishing editable child sub cell-level partitions within a parent layout-level partition, each of which representing various components of the same electronic circuit layout.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: February 16, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Yuan-Kai Pei, Gautam Kumar, Gerard Tarroux
  • Patent number: 10922457
    Abstract: The disclosure describes the implementation of automated techniques for optimizing quantum circuits of the size and type expected in quantum computations that outperform classical computers. The disclosure shows how to handle continuous gate parameters and report a collection of fast algorithms capable of optimizing large-scale-scale quantum circuits. For the suite of benchmarks considered, the techniques described obtain substantial reductions in gate counts. In particular, the techniques in this disclosure provide better optimization in significantly less time than previous approaches, while making minimal structural changes so as to preserve the basic layout of the underlying quantum algorithms.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: February 16, 2021
    Assignees: University of Maryland, IonQ Inc.
    Inventors: Yunseong Nam, Dmitri Maslov, Andrew Childs, Neil Julien Ross, Yuan Su
  • Patent number: 10915693
    Abstract: An embodiment herein provides a method for implementing verification IP for pre-silicon functional verification of a layered protocol. The method includes generating serially connected layer blocks. A layer block includes modular components that may be enabled or disabled to change a functionality of the layer block. The modular components include a layer core, a stimulus handler, one or more transmit routers and one or more receive routers. The layer core implements the complete functionality of the layer block. The stimulus handler drives input stimulus transactions into the layer core of the layer block. The one or more transmit routers routes one or more transmit core transactions from the layer core to the connected succeeding layer block. The one or more receive routers routes one or more receive core transactions from the succeeding layer block to the layer core.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: February 9, 2021
    Assignee: SILICONCH SYSTEMS PVT LTD
    Inventors: Kaustubh Kumar, Pavitra Balasubramanian
  • Patent number: 10896272
    Abstract: A high-level synthesis device executes high-level synthesis on a behavioral description including a plurality of loop descriptions and a logical description. An extraction unit extracts loop descriptions that can be merged with the logical description without changing a function, as loop description candidates, from the plurality of loop descriptions. The extraction unit also calculates characteristics of a circuit of a case where the logical description is merged with each of the loop description candidates, as circuit characteristics. A determination unit determines a loop description to be merged with the logical description, from the loop description candidates based on the circuit characteristics. A merge unit merges the logical description with the loop description determined by the determination unit.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: January 19, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Ryo Yamamoto
  • Patent number: 10895871
    Abstract: A method and system for automatically generating interactive wiring diagram in an industrial automation environment are disclosed. The method includes acquiring real-time data associated with devices commissioned in a plant from one or more sensing units disposed at the respective devices. The method also includes determining connections between the devices in the plant based on the acquired real-time data using a lookup table. The method includes generating a wiring diagram of the plant based on the determined connections between the devices. The wiring diagram represents the devices located in the plant and physical connections between the devices. The method includes dynamically generating interactive wiring diagrams by superimposing the wiring diagram with the device connectivity status information associated with respective connections between the devices.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: January 19, 2021
    Assignee: SIEMENS AKTIENGESELLSCHAFT
    Inventor: Mahantesh Ganachari
  • Patent number: 10885249
    Abstract: A system to develop an integrated circuit includes a child placement module that places in a parent macro a child macro that contains therein a child logic circuit component. The parent macro has a first hierarchical level assigned thereto and the child macro has a lower second hierarchical level assigned thereto. The system further includes a timing analysis module and a component targeting module. The timing analysis module detects a timing fault in response to performing a first parent-level optimization process on the parent macro. The component targeting module extracts from the child macro a targeted logic circuit component and places the targeted logic circuit component in the parent macro. The timing analysis module performs a second parent-level optimization process on the parent macro that resolves the timing fault based on the placement of the targeted logic circuit component in the parent macro.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: January 5, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nany Kollesar, Shawn Kollesar
  • Patent number: 10872186
    Abstract: Embodiments are directed towards a method to create a reconfigurable interconnect framework in an integrated circuit. The method includes accessing a configuration template directed toward the reconfigurable interconnect framework, editing parameters of the configuration template, functionally combining the configuration template with a plurality of modules from an IP library to produce a register transfer level (RTL) circuit model, generating at least one automated test-bench function, and generating at least one logic synthesis script. Editing parameters of the configuration template includes confirming a first number of output ports of a reconfigurable stream switch and confirming a second number of input ports of the reconfigurable stream switch. Each output port and each input port has a respective architectural composition. The output port architectural composition is defined by a plurality of N data paths including A data outputs and B control outputs.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: December 22, 2020
    Assignees: STMICROELECTRONICS S.R.L., STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Thomas Boesch, Giuseppe Desoli
  • Patent number: 10867091
    Abstract: A method of optimizing a power consumption of an integrated circuit design, includes dividing the integrated circuit design into N circuit partitions, supplying each circuit partition to a different one of N computer systems each associated with a different one of the N circuit partitions, training each of the N computer systems to reduce the power consumption of its associated circuit partition thereby to generate N training data, storing the N training data in a database, and applying the N training data to the integrated circuit design thereby to reduce the consumption of the integrated circuit design.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: December 15, 2020
    Assignee: Synopsys, Inc.
    Inventors: Nahmsuk Oh, Antun Domic
  • Patent number: 10846456
    Abstract: A method of generating a netlist of an IC device includes extracting dimensions of a gate region of the IC device, the dimensions including a width of the gate region, the width extending at least from a first edge of an active region to a second edge of the active region, and a distance from a first end of the width to a gate via positioned along the width. A first gate resistance value corresponding to the gate region is received, a second gate resistance value is determined based on the distance and the width, and the netlist is updated based on the first and second gate resistance values.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: November 24, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ke-Ying Su, Jon-Hsu Ho, Ke-Wei Su, Liang-Yi Chen, Wen-Hsing Hsieh, Wen-Koi Lai, Keng-Hua Kuo, KuoPei Lu, Lester Chang, Ze-Ming Wu
  • Patent number: 10846450
    Abstract: Described herein are a processor and a method of operating the processor to simulate a many-core target machine. The processor includes a plurality of processing cores arranged in a predetermined manner and a global target clock counter (GTCC) configured to count a number of simulated clock cycles in the target machine. A global stall controller (GSC) configured to halt execution of all the processing cores based on a determination of at least one processing core being in a fault condition; and wherein the processor acquires a base clock per instruction (CPI) of a target machine, the CPI corresponding to an average number of clock cycles required by the target machine to execute a single instruction, translates an application of the target machine to a compact executable trace to be executed by the processor, and adjusts a speed of simulation by adjusting an update rate of the global target clock counter.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: November 24, 2020
    Assignee: KING FAHD UNIVERSITY OF PETROLEUM AND MINERALS
    Inventors: Muhammad Elnasir Elrabaa, Ayman Ali Hroub
  • Patent number: 10839132
    Abstract: Cover points are automatically generated based on analysis of the hardware design represented in register transfer level (RTL) of a hardware description language. A cover point generator uses uncertainty of event occurrence, critical point analysis and redundancy elimination to determine consequential cover points for function verification. A user may provide input parameters to the cover point generator to define depth and width of cover events for generating cover points.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: November 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kousik Dan, Sandeep Korrapati
  • Patent number: 10831970
    Abstract: Techniques for generating a layout of a multi-port memory cell are provided. A specification describing at least on port within a memory cell is defined. A base memory cell including at least one extension point is modeled. A port that interfaces with the base memory cell is identified from the specification. An electrical interface between the identified port and an extension point of the base memory cell is modeled. In some embodiments, a design bucket is selected from among a predefined set of design buckets based on a count of ports within the memory cell, as described by the specification. Each design bucket corresponding to a respective layout template including the base memory cell and a respective maximum count of ports. Each electrical interface including a port described in the specification of the memory cell is modeled based on the selected design bucket and the respective layout template.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Rolf Sautter, Amira Rozenfeld, Shankar Kalyanasundaram, Ananth Nag Raja Darla, Rajesh Veerabhadraiah
  • Patent number: 10831959
    Abstract: An advanced timing mode has a path that originates from a host application-specific integrated circuit (ASIC) and terminates at a register inside an embedded field programmable gate array (FPGA), bypassing interface cluster registers. The terminating register may be present at a boundary between the host ASIC and the embedded FPGA or deep inside the embedded FPGA. In a clock trunk input with internal divergence timing scenario, a clock output from a phase-locked loop (PLL) in the host ASIC is driven through a clock trunk into the embedded FPGA and, from there, diverges into interface cluster registers and the boundary adjacent to the host ASIC. A clock trunk input with external divergence timing scenario is similar to the internal divergence scenario except that a clock divergence occurs before the clock enters a clock trunk of the embedded FPGA. In a boundary clock input scenario, a PLL drives both the host ASIC and the embedded FPGA interface clusters.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: November 10, 2020
    Assignee: Achronix Semiconductor Corporation
    Inventors: Namit Varma, Shirish Jawale
  • Patent number: 10816957
    Abstract: Disclosed is a method of integrating changes to a computer aided manufacturing software application file for a manufactured component comprising the steps of: obtaining a first computer aided design file for the manufactured component; displaying a first solid model of the manufactured component; obtaining a second computer aided design file for a revised version; displaying a second solid model of the revised version of the manufactured component; and matching at least one face on the second solid model to at least one face on the first solid model.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: October 27, 2020
    Inventor: Robert Kirkwood
  • Patent number: 10810336
    Abstract: Described is a method comprising a processing, an establishing, and/or a determining. In the processing, an inputted capabilities list including one or more hardware design capabilities may be processed. In the establishing, one or more candidate components for the one or more hardware design capabilities may be established. In the determining, a set of unique candidate netlists capable of satisfying the one or more hardware design capabilities may be determined, the set of unique candidate netlists being based upon the set of candidate components.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: October 20, 2020
    Assignee: zGlue, Inc.
    Inventors: Danielle Morton, Rick Yan
  • Patent number: 10810342
    Abstract: Capturing and processing a digital image of a pictorial (e.g., hand-drawn) representation of a schematic or block diagram as a digital image to aid in creation and maintenance of electrical designs is disclosed. Processing of the digital image includes processing to determine design parameters to create an informational format useful as input to other design software. Design parameters may include schematic layout and attributes such as maximum output voltage, minimum input voltage, ambient temperature, etc. The method and system also include storage of information accessible to refine designs and perform simulations of designs as part of an overall electrical design process. Associated devices and methods are disclosed as well.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: October 20, 2020
    Assignee: Texas Instruments Incorporated
    Inventor: Malcolm James Humphrey
  • Patent number: 10802408
    Abstract: A method for improving the yield of a lithographic process, the method including: determining a parameter fingerprint of a performance parameter across a substrate, the parameter fingerprint including information relating to uncertainty in the performance parameter; determining a process window fingerprint of the performance parameter across the substrate, the process window being associated with an allowable range of the performance parameter; and determining a probability metric associated with the probability of the performance parameter being outside an allowable range. Optionally a correction to the lithographic process is determined based on the probability metric.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: October 13, 2020
    Assignee: ASML Netherlands B.V.
    Inventors: Everhardus Cornelis Mos, Jochem Sebastiaan Wildenberg, Erik Johannes Maria Wallerbos, Maurits Van Der Schaar, Frank Staals, Franciscus Hendricus Arnoldus Elich
  • Patent number: 10803228
    Abstract: An embodiment herein provides a method for implementing verification IP for pre-silicon functional verification of a layered protocol. The method includes generating serially connected layer blocks. A layer block includes modular components that may be enabled or disabled to change a functionality of the layer block. The modular components include a layer core, a stimulus handler, one or more transmit routers and one or more receive routers. The layer core implements the complete functionality of the layer block. The stimulus handler drives input stimulus transactions into the layer core of the layer block. The one or more transmit routers routes one or more transmit core transactions from the layer core to the connected succeeding layer block. The one or more receive routers routes one or more receive core transactions from the succeeding layer block to the layer core.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: October 13, 2020
    Assignee: SILICONCH SYSTEMS PVT LTD
    Inventors: Kaustubh Kumar, Pavitra Balasubramanian
  • Patent number: 10796062
    Abstract: The independent claims of this patent signify a concise description of embodiments. Embodiments described herein are directed to a database-driven scheme for automating the process of VDRC checking in a full-custom EDA Design and Implementation tool.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: October 6, 2020
    Assignee: SYNOPSYS, INC.
    Inventors: Nabil Yazdani, Donald Oriordan, Jingyu Xu, Bulent Basaran, Larissa Nitchougovskaia
  • Patent number: 10796044
    Abstract: This application discloses a computing system implementing a schematic capture tool to place and connect parts in a schematic design of a printed circuit board assembly. The computing system implementing the schematic capture tool can select a type of communication interface to connect the parts in the schematic design and identify an interface definition that corresponds to the selected type of communication interface. The schematic capture tool can locate a mapping that describes connectivity between the parts and the interface definition, and automatically modify the schematic design to include an instance of the interface definition in the schematic design and connect the parts in the schematic design to the instance of the interface definition based on the mapping. The schematic capture tool also can utilize the interface definition to set constraints for or add terminations to the connection between the parts in the schematic design.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: October 6, 2020
    Assignee: Mentor Graphics Corporation
    Inventors: Michał Paszek, Tomasz Zielski, Michał Ferdek, Pawel Cieslak, Marek Mossakowski
  • Patent number: 10796051
    Abstract: In the described examples, a model impact monitor can include an electronic design automation (EDA) manager that communicates with a plurality of EDA programs, wherein each EDA program generates a model set for a register-transfer level (RTL) design comprising a list of RTL operations. The model impact monitor can also include an adaptive model interface that records changes to the RTL operations of the RTL design and measures a change in performance characteristics of each of the plurality of EDA programs based on a respective one of the changes in the RTL operations of the RTL design.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: October 6, 2020
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Abner Luis Panho Marciano, Matheus Fonseca, Thamara Karen Cunha Andrade, Raquel Lara dos Santos Pereira, Fabiano Cruz Peixoto, Rodolfo Santos Teixeira, Rafael Gontijo Hamdan, Bruno Andrade Pereira
  • Patent number: 10754622
    Abstract: A workflow extraction method, system, and computer program product include analyzing, for each of the design screens, a relatability of one design screen to a previously analyzed design screen in the database and generating a tag that represents a workflow and creating a database linking the tag to a sequence of design screens from a transition graph that details how to move from one of the design screens to another.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: August 25, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kyungmin Lee, David M. Lubensky, Marco Pistoia, Stephen Wood
  • Patent number: 10747927
    Abstract: A method may designing electronic circuits is provided. The method may include generating a first user interface for displaying, at a client, a plurality of graphical elements for creating a state diagram. A scaffold may be added to the state diagram in response to the scaffold being selected from the plurality of graphical elements. A first state bubble may be attached to the scaffold in response to the first state bubble being selected from the plurality of graphical elements. A dimension of the scaffold and/or a position of the first state bubble on the scaffold may be adjusted in response to a second state bubble being added and/or removed from the state diagram. A second user interface may be generated for displaying, at the client, the state diagram. Related systems and articles of manufacture, including computer program products, are also provided.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: August 18, 2020
    Assignee: STARSYSTEMS, INC.
    Inventor: Fletcher McBeth
  • Patent number: 10725104
    Abstract: Disclosed is an apparatus including a datapath and a test circuit. The datapath is configured to transfer data between a memory core and an IO interface. The datapath includes a plurality of circuits, and a memory core interface. The plurality of circuits operates according to a supply voltage. The test circuit is coupled to the datapath, and configured to determine, from a set of operable voltage levels of the supply voltage, a first minimum operable voltage level for the datapath to operate for the data traversing the datapath at a first frequency.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: July 28, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Amandeep Kaur, Sridhar Yadala, Jayanth Mysore Thimmaiah, Ravindra Arjun Madpur
  • Patent number: 10726180
    Abstract: A computer executable processing component analyzes unknown (X) propagation from uninitialized latches in gate-level simulation and determines if the Xs cause false Xs to be generated due to X-pessimism. For Xs generated due to X-pessimism, simulation results are corrected and fixes are generated. Corrected simulation results match real hardware behavior and greatly reduces engineers' analysis effort on debugging X issues. A computer executable processing component analyzes unknown (X) propagation from sequential cells in gate-level logic simulation and determines if the Xs cause false Xs to be generated due to X-pessimism. For Xs generated due to X-pessimism, simulation results are corrected and fixes are generated. Corrected simulation results match real hardware behavior and greatly reduces engineers' analysis effort on debugging X issues.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: July 28, 2020
    Assignee: Avery Design Systems, Inc.
    Inventors: Kai-Hui Chang, Andrew Stein, Hong-zu Chou, Christopher S. Browy, Chi-Lai Huang
  • Patent number: 10719648
    Abstract: A method is disclosed that includes providing an IP bank, an application bank, and a technology bank; generating a hierarchical table based on the IP bank and the application bank; performing an estimation of at least one of a performance value, a power value, an area value and a cost value, which corresponds to the hierarchical table, by using the technology bank, to output an result data as a basis of fabrication of a system.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: July 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tze-Chiang Huang, Kai-Yuan Ting, Sandeep Kumar Goel, Yun-Han Lee, Shereef Shehata, Mei Wong