Abstract: The present disclosure relates to defining and processing hardware description language (HDL) groups. Embodiments may include mapping, using a processor, a set of tool-specific objects into a group graph with one or more groups. Embodiments may also include generating a search order associated with each group. The search order associated with each group may be based upon the hierarchical design configuration of the group graph. Embodiments may further include identifying undefined references from within a first group within the group graph and binding defined references from within the first group to electronic circuit design components. Embodiments may include identifying the undefined references from within a second group within the group graph. The second group may be selected based upon the undefined references and the search order associated with the first group.

Abstract: Systems and methods for generating and deploying integrated circuit (IC) applications are provided. Global variable implementation logic may be used to optimize implementation, on an integrated circuit, of functionality represented by high-level code including global variables. A compiler's intermediate representation is analyzed for one or more characteristics that may be used to determine one or more initialization parameters, one or more scope parameters, one or more implementation parameters, or any combination thereof of the functionality. An HDL is generated based upon the one or more initialization parameters, the one or more scope parameters, the one or more implementation parameters, or the any combination thereof.

Abstract: Systems and methods automatically generate code from an executable model. The code may be generated from one or more in-memory representations constructed for the model. The in-memory representations may be analyzed, and portions that can be mapped to DSP slices of a programmable logic device may be identified. The portions may be modified based on information for a particular programmable logic device, such as the structure of the device's DSP slices. The modifications may ensure that elements of the generated code get mapped to DSP slices, when the generated code is used to synthesize the programmable logic device.

Abstract: In one aspect, electronic design automation systems, methods, and non-transitory computer readable media are presented for adding a memory built-in self-test (MBIST) logic at register transfer level (RTL) or at netlist level into an integrated circuit (IC) design. In some embodiments, the MBIST logic is coupled to a physical memory module via a logical boundary of an intermediate level module that contains the physical memory module. The MBIST logic helps to keep intact integrity of the intermediate level module, making it more likely to meet any specified performance of the intermediate level module and reduce area overhead.

Abstract: In a system and method for emulating a circuit design, an emulation system receives input instructions from a host device executing the emulation and returns test results and trace data. Channels of multiple buffers and associated processors implement the test operations. Compression units on each channel may compress the test and trace data to facilitate returning the results to the host device. Multiple channels may be used to compress data in parallel, thereby improving throughput.

Abstract: Systems and methods for implementing a scalable very-large-scale integration (VLSI) architecture to perform compressive sensing (CS) hardware reconstruction for data signals in accordance with embodiments of the invention are disclosed. The VLSI architecture is optimized for CS signal reconstruction by implementing a reformulation of the orthogonal matching pursuit (OMP) process and utilizing architecture resource sharing techniques. Typically, the VLSI architecture is a CS reconstruction engine that includes a vector and scalar computation cores where the cores can be time-multiplexed (via dynamic configuration) to perform each task associated with OMP. The vector core includes configurable processing elements (PEs) connected in parallel. Further, the cores can be linked by data-path memories, where complex data flow of OMP can be customized utilizing local memory controllers synchronized by a top-level finite-state machine.

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing engineering change orders (ECOs) with figure groups and virtual hierarchies. These techniques identify a schematic design and a layout having at least one virtual hierarchy of an electronic design. These techniques then implement an ECO to modify at least one layout circuit component design in a figure group, without considering a physical hierarchical structure of the layout. These techniques further check the figure group based in part or in whole upon one or more criteria and update one or more data structures for the at least one virtual hierarchy and the figure group based in part or in whole upon the ECO.

Abstract: An architecture for realizing a customer system on a cloud computing platform is defined in terms of a plurality of architecture types, each type (AT) defined by plural architecture type units (ATUs), each ATU comprising a set of ATU Details. The ATU Details are ordered into a series of discrete stages. Maturity of the architecture is determined as a single architecture pulse (AP) numeric value for each architecture type. The pulse reflects the extent to which the ATUs of the architecture type have reached a requisite level of quality, and an extent to which the ATUs are created in a sequence consistent with the series of discrete stages. The AP pulse values may be combined to form a single success platform pulse (SPP) for tracking overall condition of the platform architecture with a single numerical value.

Abstract: The testing and operating of remote devices are discussed. More particularly, signals are generated and/or received by remote devices, analyzed, logged, and displayed. Signals to remote devices are provided. Enhancements to the operability, capabilities, and functionality of such previously available testing equipment, are provided, via the operation of a remote, portable, and lightweight test bed. The test bed is operated and controlled remotely via a user-computing device. The test bed senses, probes, and/or controls a remote device and test data is automatically generated and/or acquired. The test data is provided to the user-computing device for automated analysis, visualization, and test report generation.

Abstract: A method for assigning nets to wiring planes for generating a chip design includes executing, by a computer, a zero wire load timing session for a placed but unbufferred chip design. All nets of the chip design are set to a single wide wiring track without wiring plane assignments. A delta time delay is added to each sink of each of the nets to represent an estimated time of flight (TOF) delay. The nets wiring plane or width type for a particular pin is upgraded to a type having improved TOF characteristics. Each of the nets are compared against new predetermined slack and distance targets and new assigned wiring plane or width type determined to consume additional wiring track resources, and based on results, the upgrade is repeated or a design for session timing state for the nets is output to represent the unbufferred chip design.

Abstract: Disclosed embodiments relate to an apparatus for managing a study mode in an energy management system. In some embodiments, the apparatus includes: a control unit configured to process data collected from a power system and operate an energy management system; a study file creator configured to create a study file based on data being currently operated in the control unit; and a study control unit configured to copy the study file and create a study database for study mode execution.

Abstract: A computer-implemented method for managing device configurations at various levels of abstraction may include (1) receiving a request to transform configuration details of at least one computing device into configuration details for an abstraction of the computing device, (2) using at least one compiler to transform the configuration details of the computing device into configuration details of the abstraction, and (3) returning the configuration details of the abstraction. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: An image sensor for converting incident light into digital signals is disclosed. In one aspect, the image sensor includes a matrix of light-sensitive pixels arranged in a plurality of pixel columns each having a predetermined lateral extent. The image sensor includes an analog-to-digital converter block including a plurality of analog-to-digital converters (ADCs). Each of the plurality of ADCs includes an analog processing portion adapted to receive at least one analog signal from a pixel column of the matrix and to generate at least one digital signal from the received analog signal. Each of the plurality of ADCs includes a digital processing portion adapted to receive said at least one digital signal from said corresponding analog processing portion. The lateral extent of at least one of the digital processing portions is greater than the lateral extent of its corresponding analog processing portion.

Abstract: A wireless communication terminal apparatus wherein even when a SC-FDMA signal is divided into a plurality of clusters and the plurality of clusters are then mapped to respective discontinuous frequency bands (when C-SC-FDMA is used), the improvement effect of system throughput can be maintained, while the user throughput can be improved. In the apparatus, a DFT unit (210) subjects a symbol sequence of time domain to a DFT process, thereby generating signals of frequency domain. A setting unit (211) divides the signals input from the DFT unit (210) into a plurality of clusters according to a cluster pattern that is in accordance with an MCS set, an encoding size, or the number of Ranks occurring during MIMO transmissions, which is indicated in those signals input, and then maps the plurality of clusters to the respective ones of a plurality of discontinuous frequency resources, thereby setting a constellation of the plurality of clusters in the frequency domain.

Abstract: Embodiments of the present invention include an apparatus that receives date from multiple lanes, which are then aligned and synchronized for transcoding and encoding.

Abstract: A processor includes an innovation engine, a non-volatile memory, a reserved device, one or more user-defined devices, and logic to execute the user-defined devices. The processor also includes a debug engine with logic to monitor the processor for trigger conditions and record data associated with the trigger conditions. The innovation further includes logic to selectively load the debug engine.

Abstract: A first circuit design description may have registers and combinational gates. Circuit design computing equipment may perform register retiming on the first circuit design description, whereby registers are moved across combinational gates during a first circuit design implementation. An engineering-change-order (ECO) of the first circuit design may result in a second circuit design. The differences between the first and second circuit designs may be confined to a region-of-change. The circuit design computing equipment may preserve the results from the first circuit design implementation and re-use portions of these results during the implementation of the second circuit design.

Abstract: A system and method for enabling the estimation and mitigation of self-heating in chip designs at a much earlier stage in a design flow. The system and method provides unique characterization of each standard cell in a library for its effective thermal resistance based on the topology and layout of the cell, and brings this per standard cell instance based delta-T to be available for the timing closure tools when completing a synthesized design. Thus, at the timing closure process, the generated design is free of self heating violations. The method computes a unique thermal resistance characterization on per standard cell manner—based on the topology, function and layout of the standard cell, and uses that to compute the deltaT per instance of the design. This information is presented to a violation mitigation tool which changes the power levels of the cells, logic function to mitigate the self heating violations.

Abstract: Various systems and methods are provided that display schematics and data associated with the various physical components in the schematics in an interactive user interface. For example, a computing device links data stored in one or more databases with schematics displayed in one or more interactive user interfaces. The computing device parses a digital image that depicts a schematic and identifies text visible in the digital image. Based on the identified text, the computing device recognizes representations of one or more physical components in the schematic and links the representations to data regarding the physical component in one or more databases, such as specification data, historical sensor data of the component, etc. The computing device modifies the digital image such that it becomes interactive and visible in a user interface in a manner that allows the user to select a physical component and view data associated with the selection.

Abstract: Technologies for optimizing sparse matrix code include a target computing device having a processor and a field-programmable gate array (FPGA). A compiler identifies a performance-critical loop in a sparse matrix source code and generates optimized executable code, including processor code and FPGA code. The target computing device executes the optimized executable code, using the processor for the processor code and the FPGA for the FPGA code. The processor executes a first iteration of the loop, generates reusable optimization data in response to executing the first iteration, and stores the reusable optimization data in a shared memory. The FPGA accesses the optimization data in the shared memory, executes additional iterations of the loop, and optimizes the additional iterations of the loop based on the optimization data. The optimization data may include, for example, loop-invariant data, reordered data, or alternate data storage representations. Other embodiments are described and claimed.

Abstract: Aspects include techniques for selective boundary overlay insertion for hierarchical circuit design. A method may include determining, by a processing device, a block type of a child block. The method may further include electively inserting, by the processing device, at least one of an instantiated boundary overlay and a merged boundary overlay into the hierarchical circuit design based on the block type of the child block. The instantiated boundary overlay enables a parent block to pass a testing at an out-of-context level, and the merged boundary overlay enables the parent block to continue to pass the testing when the child block is inserted into the parent block associated with the child block.

Abstract: The present disclosure relates to a system and method for simulating channels in an electronic circuit design. Embodiments may include receiving, at one or more computing devices, an electronic circuit design including at least one channel. Embodiments may further include transmitting two or more inputs from two or more transmitter drivers on two or more wires to the at least one channel. In some embodiments, the inputs may be distributed across the wires based upon a chordal code. Embodiments may also include generating simulated waveforms based upon the inputs. Embodiments may further include transmitting the simulated waveforms from the channel on the wires to a comparator block. Embodiments may also include comparing the simulated waveforms on the wires at the comparator block to produce two or more simulated outputs. Embodiments may include transmitting the simulated outputs from the comparator block on the wires to two or more post-comparator receivers.

Abstract: A method for automated debugging of a design under test (DUT), including using a processor, (a) identifying a value of a signal at a specific time instance in which a user has indicated interest; (b) performing driver tracing based on structural analysis and signal analysis to determine one or a plurality of drivers of the identified value in the signal; (c) if the driver tracing returns a single driver of said one or a plurality of drivers, presenting the returned single driver to the user via an output device; and (d) if the driver tracing returns a plurality of drivers of said one or a plurality of drivers, performing formal analysis on a compiled sub-structure of the DUT to which all of said returned plurality of drivers are related to determine a single driver from said returned plurality of drivers, and presenting the determined single driver from said returned plurality of drivers to the user via the output device.

Abstract: Systems and methods for designing reconfigurable integrated circuits receive target data and training data; and generate a circuit design for implementing the target data which is over-provisioned with respect to the target data according to the training data.

Abstract: Described herein is a method of designing micro-fluidic devices. A target cost function based on device design parameters is chosen. The performance of one or more design candidates is run in a simulation model. A design candidate with a cost function closest to the target cost function is chosen and modified in an optimization routine to provide a modified design candidate having modified device design parameters. The cost function for the modified initial design candidate is computed, and when the modified design candidate has a computed cost function that meets the target cost function, optimized device design parameters of an optimized device design are obtained. Additional optimization iterations may be performed as needed to arrive at an optimized device design. A micro-fluidic device based on the optimized device design is manufactured.

Abstract: A system, method, and computer program product for generating executable code for performing large integer operations on a parallel processing unit is disclosed. The method includes the steps of compiling a source code linked to a large integer library to generate an executable file and executing the executable file to perform a large integer operation using a parallel processing unit. The large integer library includes functions for processing large integers that are optimized for the parallel processing unit.

Abstract: A host system for transferring data to a target system is provided. The host system may include a layout database for storing mask layout data representing an integrated circuit (IC) in terms of planar geometric shapes. The hosts system may further include a processor configured to import the mask layout data from the layout database to a memory-mapped disk in the host system. The processor is further configured to translate the mask layout data into one or more cell views according to a table hierarchy in the memory-mapped disk. The processor is further configured to transmit the one or more cell views from the memory-mapped disk to a magnetic disk of the target system.

Abstract: Aspects of the invention relate to techniques for fault diagnosis based on dynamic circuit design partitioning. According to various implementations of the invention, a sub-circuit is extracted from a circuit design based on failure information of one or more integrated circuit devices. The extraction process may comprise combining fan-in cones of failing observation points included in the failure information. The extraction process may further comprise adding fan-in cones of one or more passing observation points to the combined fan-in cones of the failing observation points. Clock information of test patterns and/or layout information of the circuit design may be extracted and used in the sub-circuit extraction process. The extracted sub-circuit may then be used for diagnosing the one or more integrated circuit devices.

Abstract: Methods, systems, and devices are disclosed for automatically generating physical layouts of integrated circuits. A circuit is partitioned into one or more cells based on a circuit description. The method further checks availability of a layout of a cell for all the cells generated during the partition step. If a layout of a cell is not available, the method generates a layout of the cell by an automatic tool, and packages the generated layout in a form of a standard cell compatible with a standard cell placement and routing tool. Afterwards, the generated layout may be exported to the standard cell placement and routing tool. Finally, the standard cell placement and routing tool may merge individual layouts of the one or more cells of the circuit to generate a layout for the circuit.

Abstract: Disclosed is an approach to implement a requirements-driven analog verification flow. Disparate islands of verification tasks are performed with individual cellviews to be set into an overarching and closed loop verification flow context for a project or a complex verification task.

Abstract: Methods and systems of an electronic circuit design system described herein provide a new layout editor tool to make edits in an electronic circuit layout. A plurality of partitions is created in the electronic circuit layout. The new layout editor tool enables multiple electronic circuit designers to edit a different partition of the plurality of partitions of the same electronic circuit layout at the same time and save the edited partition locally.

Abstract: A system and method for providing sets of partition placements, the system and method including, receiving at least one placement request for a set of partitions of a volume. Based at least in part on counts of pairs of partitions hosted by pairs of computing devices, the system and method further includes determining how suitable the pairs of computing devices are for placement of partitions of the set of partitions, generating a set of placements based at least in part on the determination, and providing the set of placements in response to the at least one placement request.

Abstract: Methods for performing design rule checking of a circuit design are provided. The methods include, for instance: providing a circuit design for an integrated circuit layer, in which the circuit design includes a plurality of design lines oriented in a particular direction; and automatically performing a design rule check of the circuit design, which may include forming a verification pattern for the circuit design, the verification pattern comprising a plurality of verification lines and a plurality of verification regions, wherein one or more verification regions are associated with and connected to one verification line of the plurality of verification lines, and checking the verification pattern for any verification line overlapping a verification region. The circuit design may be considered to fail the design rule check if an end of one verification line overlaps any verification region associated with another verification line of the verification pattern.

Abstract: Methods for specification based augmented search. The specification based augmented search includes determining input characteristics based on a design and a user, identifying design rules associated with the input characteristics, traversing a library for library nodes including specifications that contain the design rules, displaying a plurality of library elements that correspond to the library nodes including the specifications that contain the design rules, receiving a selection of a library element from the plurality of library elements displayed, and returning a library object associated with the library element.

Abstract: A method includes generating a schematic of an integrated circuit (IC), the IC having a circuit component. The method also includes searching a database having one or more configurations of the circuit component, each of the one or more configurations of the circuit component having a corresponding estimated resistance capacitance (RC) value and an assigned color scheme based on the estimated RC value. The method further includes displaying the circuit component in the schematic as a symbol representing the circuit component, the symbol representing the circuit component being displayed having the assigned color scheme of a selected circuit component configuration.

Abstract: A user specified high level design selects a plurality of IP cores for placement in a customized system on a chip. A single integrated service automatically performs each of a design integration phase, specification phase, and verification phase for the user specified high level design to generate an integration file specifying stitching between a plurality of pins of each of the plurality of IP cores, a specification file specifying one or more characteristics of the customized system on a chip based on the user specified high level design, and a verification testbench for verification of the user specified high level design.

Abstract: A software security layer may be used to protect a system against exploitation of a hardware encoder accelerator by malicious data embedded in the one or more frames of encoded digital streaming data. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: Various implementations described herein are directed to a system and methods for generating timing data for an integrated circuit. In one implementation, the method may include generating first timing data for the integrated circuit, and the first timing data may be related to one or more variations of operating conditions for the integrated circuit. Further, the method may include extracting parameter values from the first timing data in association with the one or more variations of operating conditions. Further, the method may include generating second timing data for the integrated circuit, and the second timing data may be based on the extracted parameter values.

Abstract: The method includes identifying a register-transfer level design description for a design. The method further includes identifying one or more tests to perform on the register-transfer level design description. The method includes generating a table of commands from the one or more tests to perform on the register-transfer level design description. The method includes generating a register-transfer level design description from the table of commands for at least one of a set of components including: a test driver for the design, a monitor for the design, and a checker for the design, wherein the register-transfer level design description assigns commands in the generated table of commands to be performed by a corresponding component in the set of components. The method includes simulating the identified one or more tests utilizing the generated register-transfer level design descriptions for at least one of the test driver, the checker, and the monitor.

Abstract: Systems and techniques are described for designing an integrated circuit (IC). Some embodiments explicitly represent wide-buses as distinct objects in an IC design data model. One or more IC design representations that are used in an IC design flow may natively support such wide-bus objects. These new objects can enable rapid access and preservation of wide-buses, thereby improving the runtime and/or quality of results (QoR) of an IC design system.

Abstract: A computer system includes a processor and an electronic storage. The processor provides a service composition tree of services which are offered, wherein the tree is hierarchical and specifies relationships of the services which are offered within the service composition tree to each other; translates service composition trees and the relationships of the services represented in the trees into a directed acyclic graph (DAG) that represents the service composition trees, the DAG being redundancy-free; and performs a transitive traversal within the DAG among the services represented in the DAG to locate information, within the DAG, regarding the services, in relation to each other. The electronic storage stores the DAG accessed by the processor. A method according to the above will perform a transitive traversal service discovery of a DAG that is redundancy-free, and optionally is minimal weighted. A non-transitory computer-readable medium can perform the method.

Abstract: Embodiments relate to cross-hierarchy interconnect adjustment. An aspect includes receiving chip layout data corresponding to a chip design, wherein a first portion of a metal stack of the chip design is assigned to a first hierarchy and a second portion of the metal stack is assigned to a second hierarchy based on a contract between the first and second hierarchy. Another aspect includes determining an unused portion of the first portion of the metal stack. Another aspect includes moving an interconnect of the second hierarchy from the second portion of the metal stack that is assigned to the second hierarchy to the unused portion of the first portion of the metal stack in the chip layout data. Another aspect includes performing power recovery on the chip layout data after moving the interconnect based on an amount of slack margin generated in the chip design by the moving of the interconnect.

Abstract: A user specified high level design selects a plurality of IP cores for placement in a customized system on a chip. A single integrated service automatically performs each of a design integration phase, specification phase, and verification phase for the user specified high level design to generate an integration file specifying stitching between a plurality of pins of each of the plurality of IP cores, a specification file specifying one or more characteristics of the customized system on a chip based on the user specified high level design, and a verification testbench for verification of the user specified high level design.

Abstract: Techniques are provided to assign a set/reset signal of a user design to global set/reset (GSR) resources of a programmable logic device (PLD). By assigning a set/reset signal of the user design to the GSR resources during synthesis and prior to mapping, configurable resources consumed by the design may be reduced. In one example, a method includes receiving a user design for a programmable logic device (PLD) that comprises a plurality of configurable resources and global set/reset (GSR) resources. The method also includes identifying a plurality of set/reset signals of the user design. The method also includes determining, for each set/reset signal, a measurement of configurable resource savings associated with an assignment of the set/reset signal to the GSR resources. The method also includes assigning a selected one of the set/reset signals to the GSR resources based on the associated measurement. Additional methods and related systems are also provided.

Abstract: Embodiments herein describe performing an engineering change order (ECO) after a physical design team has begun (or finished) a physical design (PD) netlist. However, the ECO may describe changes or additions to the logic and/or nets using component names found in a design netlist that is different than the PD netlist. Embodiments herein rely on generating an equivalents nets file that the maps the components in the design netlist to the components in the PD netlist. When performing an ECO, the PD team can use this file to map the components in the ECO (which are based on the design netlist) to all the equivalent components in the PD netlist. The PD team then selects one of the equivalent components to alter as indicated in the ECO.

Abstract: A computer-implemented method includes obtaining a first representation of a system, obtaining a set of test obligations, and automatically generating one or more test cases from the first representation based on the set of test obligations. The method further includes obtaining a second representation that is related to the first representation, obtaining an analysis criterion for the second representation, and assessing the analysis criterion using the one or more test cases applied to the second representation. Based on the assessing, one or more additional test obligations may be identified and a second set of one or more test cases may be generated based on the one or more additional test obligations.

Abstract: A computer-implemented method, computer program product, and computing system for identifying one or more variables included within at least a portion of a simulation modeling file. Comment data is inserted into the at least a portion of the simulation modeling file to define one or more values for each of one or more variables.

Abstract: The present disclosure relates to a computer-implemented method for electronic design simulation. The method may include receiving, using at least one processor, an electronic design and displaying, at a graphical user interface, at least a portion of the electronic design. Embodiments may also include allowing a user to select at least one design variable at the graphical user interface. Embodiments may also include simulating the electronic design, based upon, at least in part, the selected at least one design variable and in response to the simulation, automatically displaying an updated value at the graphical user interface.

Abstract: A system comprises a processor-implemented tool configured to generate a layout of an integrated circuit (IC) die. At least one non-transitory machine readable storage medium includes a first portion encoded with a first gate-level description of first and second circuit patterns to be formed on first and second integrated circuit (IC) dies, respectively, and a second portion encoded with a second gate level description of the first and second circuit patterns received from the processor implemented tool. The second gate level description includes power and ground ports, and the first gate level description does not include power and ground ports. A processor-implemented first verification module is provided for comparing the first and second gate level descriptions and outputting a verified second gate-level description of the first and second circuit patterns.

Abstract: A system, method and/or computer program for optimizing a circuit design. In some embodiments, a target block with an external boundary and external boundary pins is identified in an integrated circuit design. An area outside the target block is converted into a first macro, wherein the first macro has a physical library and a timing library and wherein the physical library has an internal boundary that corresponds to the external boundary of the target block and wherein the physical library has internal boundary pins that correspond to the external boundary pins of the target block. The target block is represented as a single block netlist and the block netlist is optimized with respect to the first macro. The steps may be repeated with respect to a master and clone(s) on the same integrated circuit enabling a single block netlist to be optimized for multiple instances of the same design IP.